Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * EDAC driver for DMC-520 memory controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * The driver supports 10 interrupt lines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * though only dram_ecc_errc and dram_ecc_errd are currently handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Authors:	Rui Zhao <ruizhao@microsoft.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *		Lei Wang <lewan@microsoft.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *		Shiping Ji <shji@microsoft.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "edac_mc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* DMC-520 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_OFFSET_FEATURE_CONFIG			0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define REG_OFFSET_ECC_ERRC_COUNT_31_00		0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define REG_OFFSET_ECC_ERRC_COUNT_63_32		0x15C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define REG_OFFSET_ECC_ERRD_COUNT_31_00		0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define REG_OFFSET_ECC_ERRD_COUNT_63_32		0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define REG_OFFSET_INTERRUPT_CONTROL			0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define REG_OFFSET_INTERRUPT_CLR			0x508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define REG_OFFSET_INTERRUPT_STATUS			0x510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_31_00	0x528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_63_32	0x52C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_31_00	0x530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_63_32	0x534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define REG_OFFSET_ADDRESS_CONTROL_NOW			0x1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define REG_OFFSET_MEMORY_TYPE_NOW			0x1128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define REG_OFFSET_SCRUB_CONTROL0_NOW			0x1170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define REG_OFFSET_FORMAT_CONTROL			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* DMC-520 types, masks and bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RAM_ECC_INT_CE_BIT			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define RAM_ECC_INT_UE_BIT			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DRAM_ECC_INT_CE_BIT			BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define DRAM_ECC_INT_UE_BIT			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define FAILED_ACCESS_INT_BIT			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define FAILED_PROG_INT_BIT			BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define LINK_ERR_INT_BIT			BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TEMPERATURE_EVENT_INT_BIT		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define ARCH_FSM_INT_BIT			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PHY_REQUEST_INT_BIT			BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MEMORY_WIDTH_MASK			GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SCRUB_TRIGGER0_NEXT_MASK		GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define REG_FIELD_DRAM_ECC_ENABLED		GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define REG_FIELD_MEMORY_TYPE			GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define REG_FIELD_DEVICE_WIDTH			GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define REG_FIELD_ADDRESS_CONTROL_COL		GENMASK(2,  0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define REG_FIELD_ADDRESS_CONTROL_ROW		GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define REG_FIELD_ADDRESS_CONTROL_BANK		GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define REG_FIELD_ADDRESS_CONTROL_RANK		GENMASK(25, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define REG_FIELD_ERR_INFO_LOW_VALID		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define REG_FIELD_ERR_INFO_LOW_COL		GENMASK(10, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define REG_FIELD_ERR_INFO_LOW_ROW		GENMASK(28, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define REG_FIELD_ERR_INFO_LOW_RANK		GENMASK(31, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define REG_FIELD_ERR_INFO_HIGH_BANK		GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define REG_FIELD_ERR_INFO_HIGH_VALID		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DRAM_ADDRESS_CONTROL_MIN_COL_BITS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define DRAM_ADDRESS_CONTROL_MIN_ROW_BITS	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DMC520_SCRUB_TRIGGER_ERR_DETECT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DMC520_SCRUB_TRIGGER_IDLE		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* Driver settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * The max-length message would be: "rank:7 bank:15 row:262143 col:1023".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * Max length is 34. Using a 40-size buffer is enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define DMC520_MSG_BUF_SIZE			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define EDAC_MOD_NAME				"dmc520-edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define EDAC_CTL_NAME				"dmc520"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* the data bus width for the attached memory chips. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) enum dmc520_mem_width {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	MEM_WIDTH_X32 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	MEM_WIDTH_X64 = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* memory type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) enum dmc520_mem_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	MEM_TYPE_DDR3 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	MEM_TYPE_DDR4 = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* memory device width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) enum dmc520_dev_width {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	DEV_WIDTH_X4 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	DEV_WIDTH_X8 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	DEV_WIDTH_X16 = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct ecc_error_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u32 col;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	u32 row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	u32 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u32 rank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* The interrupt config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct dmc520_irq_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* The interrupt mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct dmc520_irq_config dmc520_irq_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.name = "ram_ecc_errc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.mask = RAM_ECC_INT_CE_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		.name = "ram_ecc_errd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		.mask = RAM_ECC_INT_UE_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.name = "dram_ecc_errc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.mask = DRAM_ECC_INT_CE_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.name = "dram_ecc_errd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.mask = DRAM_ECC_INT_UE_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.name = "failed_access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.mask = FAILED_ACCESS_INT_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.name = "failed_prog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.mask = FAILED_PROG_INT_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.name = "link_err",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.mask = LINK_ERR_INT_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.name = "temperature_event",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.mask = TEMPERATURE_EVENT_INT_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.name = "arch_fsm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.mask = ARCH_FSM_INT_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		.name = "phy_request",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.mask = PHY_REQUEST_INT_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define NUMBER_OF_IRQS				ARRAY_SIZE(dmc520_irq_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * The EDAC driver private data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * error_lock is to protect concurrent writes to the mci->error_desc through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * edac_mc_handle_error().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct dmc520_edac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	spinlock_t error_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u32 mem_width_in_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	int irqs[NUMBER_OF_IRQS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int masks[NUMBER_OF_IRQS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int dmc520_mc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static u32 dmc520_read_reg(struct dmc520_edac *pvt, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	return readl(pvt->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void dmc520_write_reg(struct dmc520_edac *pvt, u32 val, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	writel(val, pvt->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static u32 dmc520_calc_dram_ecc_error(u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	u32 total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* Each rank's error counter takes one byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	while (value > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		total += (value & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		value >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static u32 dmc520_get_dram_ecc_error_count(struct dmc520_edac *pvt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 					    bool is_ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	u32 reg_offset_low, reg_offset_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	u32 err_low, err_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u32 err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	reg_offset_low = is_ce ? REG_OFFSET_ECC_ERRC_COUNT_31_00 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				 REG_OFFSET_ECC_ERRD_COUNT_31_00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	reg_offset_high = is_ce ? REG_OFFSET_ECC_ERRC_COUNT_63_32 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				  REG_OFFSET_ECC_ERRD_COUNT_63_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	err_low = dmc520_read_reg(pvt, reg_offset_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	err_high = dmc520_read_reg(pvt, reg_offset_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/* Reset error counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	dmc520_write_reg(pvt, 0, reg_offset_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	dmc520_write_reg(pvt, 0, reg_offset_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	err_count = dmc520_calc_dram_ecc_error(err_low) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		   dmc520_calc_dram_ecc_error(err_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void dmc520_get_dram_ecc_error_info(struct dmc520_edac *pvt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 					    bool is_ce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 					    struct ecc_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	u32 reg_offset_low, reg_offset_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	u32 reg_val_low, reg_val_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	bool valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	reg_offset_low = is_ce ? REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_31_00 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 				 REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_31_00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	reg_offset_high = is_ce ? REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_63_32 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 				  REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_63_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	reg_val_low = dmc520_read_reg(pvt, reg_offset_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	reg_val_high = dmc520_read_reg(pvt, reg_offset_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	valid = (FIELD_GET(REG_FIELD_ERR_INFO_LOW_VALID, reg_val_low) != 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		(FIELD_GET(REG_FIELD_ERR_INFO_HIGH_VALID, reg_val_high) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		info->col = FIELD_GET(REG_FIELD_ERR_INFO_LOW_COL, reg_val_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		info->row = FIELD_GET(REG_FIELD_ERR_INFO_LOW_ROW, reg_val_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		info->rank = FIELD_GET(REG_FIELD_ERR_INFO_LOW_RANK, reg_val_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		info->bank = FIELD_GET(REG_FIELD_ERR_INFO_HIGH_BANK, reg_val_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		memset(info, 0, sizeof(*info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static bool dmc520_is_ecc_enabled(void __iomem *reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	u32 reg_val = readl(reg_base + REG_OFFSET_FEATURE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return FIELD_GET(REG_FIELD_DRAM_ECC_ENABLED, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static enum scrub_type dmc520_get_scrub_type(struct dmc520_edac *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	enum scrub_type type = SCRUB_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	u32 reg_val, scrub_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_SCRUB_CONTROL0_NOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	scrub_cfg = FIELD_GET(SCRUB_TRIGGER0_NEXT_MASK, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (scrub_cfg == DMC520_SCRUB_TRIGGER_ERR_DETECT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	    scrub_cfg == DMC520_SCRUB_TRIGGER_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		type = SCRUB_HW_PROG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Get the memory data bus width, in number of bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static u32 dmc520_get_memory_width(struct dmc520_edac *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	enum dmc520_mem_width mem_width_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	u32 mem_width_in_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_FORMAT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	mem_width_field = FIELD_GET(MEMORY_WIDTH_MASK, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (mem_width_field == MEM_WIDTH_X32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		mem_width_in_bytes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	else if (mem_width_field == MEM_WIDTH_X64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		mem_width_in_bytes = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return mem_width_in_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static enum mem_type dmc520_get_mtype(struct dmc520_edac *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	enum mem_type mt = MEM_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	enum dmc520_mem_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	type = FIELD_GET(REG_FIELD_MEMORY_TYPE, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	case MEM_TYPE_DDR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		mt = MEM_DDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	case MEM_TYPE_DDR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		mt = MEM_DDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	return mt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static enum dev_type dmc520_get_dtype(struct dmc520_edac *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	enum dmc520_dev_width device_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	enum dev_type dt = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	device_width = FIELD_GET(REG_FIELD_DEVICE_WIDTH, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	switch (device_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	case DEV_WIDTH_X4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		dt = DEV_X4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	case DEV_WIDTH_X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		dt = DEV_X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	case DEV_WIDTH_X16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		dt = DEV_X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	return dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static u32 dmc520_get_rank_count(void __iomem *reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	u32 reg_val, rank_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	reg_val = readl(reg_base + REG_OFFSET_ADDRESS_CONTROL_NOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	rank_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_RANK, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	return BIT(rank_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static u64 dmc520_get_rank_size(struct dmc520_edac *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	u32 reg_val, col_bits, row_bits, bank_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_ADDRESS_CONTROL_NOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	col_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_COL, reg_val) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		   DRAM_ADDRESS_CONTROL_MIN_COL_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	row_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_ROW, reg_val) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		   DRAM_ADDRESS_CONTROL_MIN_ROW_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	bank_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_BANK, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	return (u64)pvt->mem_width_in_bytes << (col_bits + row_bits + bank_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void dmc520_handle_dram_ecc_errors(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 					   bool is_ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	struct dmc520_edac *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	char message[DMC520_MSG_BUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	struct ecc_error_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	dmc520_get_dram_ecc_error_info(pvt, is_ce, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	cnt = dmc520_get_dram_ecc_error_count(pvt, is_ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (!cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	snprintf(message, ARRAY_SIZE(message),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		 "rank:%d bank:%d row:%d col:%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		 info.rank, info.bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		 info.row, info.col);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	spin_lock(&pvt->error_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	edac_mc_handle_error((is_ce ? HW_EVENT_ERR_CORRECTED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			     HW_EVENT_ERR_UNCORRECTED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			     mci, cnt, 0, 0, 0, info.rank, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			     message, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	spin_unlock(&pvt->error_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static irqreturn_t dmc520_edac_dram_ecc_isr(int irq, struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 					     bool is_ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	struct dmc520_edac *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	u32 i_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	i_mask = is_ce ? DRAM_ECC_INT_CE_BIT : DRAM_ECC_INT_UE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	dmc520_handle_dram_ecc_errors(mci, is_ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	dmc520_write_reg(pvt, i_mask, REG_OFFSET_INTERRUPT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static irqreturn_t dmc520_edac_dram_all_isr(int irq, struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 					     u32 irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	struct dmc520_edac *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	irqreturn_t irq_ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	status = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if ((irq_mask & DRAM_ECC_INT_CE_BIT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		(status & DRAM_ECC_INT_CE_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		irq_ret = dmc520_edac_dram_ecc_isr(irq, mci, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	if ((irq_mask & DRAM_ECC_INT_UE_BIT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		(status & DRAM_ECC_INT_UE_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		irq_ret = dmc520_edac_dram_ecc_isr(irq, mci, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	return irq_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static irqreturn_t dmc520_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	struct mem_ctl_info *mci = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	struct dmc520_edac *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		if (pvt->irqs[idx] == irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 			mask = pvt->masks[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	return dmc520_edac_dram_all_isr(irq, mci, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void dmc520_init_csrow(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	struct dmc520_edac *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	struct csrow_info *csi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	u32 pages_per_rank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	enum dev_type dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	enum mem_type mt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	int row, ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	u64 rs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	dt = dmc520_get_dtype(pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	mt = dmc520_get_mtype(pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	rs = dmc520_get_rank_size(pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	pages_per_rank = rs >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	for (row = 0; row < mci->nr_csrows; row++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		csi = mci->csrows[row];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		for (ch = 0; ch < csi->nr_channels; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 			dimm		= csi->channels[ch]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 			dimm->grain	= pvt->mem_width_in_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 			dimm->dtype	= dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 			dimm->mtype	= mt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 			dimm->edac_mode	= EDAC_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 			dimm->nr_pages	= pages_per_rank / csi->nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int dmc520_edac_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	bool registered[NUMBER_OF_IRQS] = { false };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	int irqs[NUMBER_OF_IRQS] = { -ENXIO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	int masks[NUMBER_OF_IRQS] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	struct edac_mc_layer layers[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	struct dmc520_edac *pvt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	u32 irq_mask_all = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	int ret, idx, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	/* Parse the device node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		irq = platform_get_irq_byname(pdev, dmc520_irq_configs[idx].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		irqs[idx] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		masks[idx] = dmc520_irq_configs[idx].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		if (irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 			irq_mask_all |= dmc520_irq_configs[idx].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 			edac_dbg(0, "Discovered %s, irq: %d.\n", dmc520_irq_configs[idx].name, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	if (!irq_mask_all) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 		edac_printk(KERN_ERR, EDAC_MOD_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 			    "At least one valid interrupt line is expected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	/* Initialize dmc520 edac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	reg_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	if (IS_ERR(reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		return PTR_ERR(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	if (!dmc520_is_ecc_enabled(reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	layers[0].size = dmc520_get_rank_count(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	mci = edac_mc_alloc(dmc520_mc_idx++, ARRAY_SIZE(layers), layers, sizeof(*pvt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	if (!mci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		edac_printk(KERN_ERR, EDAC_MOD_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 			    "Failed to allocate memory for mc instance\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	pvt->reg_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	spin_lock_init(&pvt->error_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	memcpy(pvt->irqs, irqs, sizeof(irqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	memcpy(pvt->masks, masks, sizeof(masks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	platform_set_drvdata(pdev, mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	mci->pdev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	mci->mtype_cap		= MEM_FLAG_DDR3 | MEM_FLAG_DDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	mci->edac_ctl_cap	= EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	mci->edac_cap		= EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	mci->scrub_cap		= SCRUB_FLAG_HW_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	mci->scrub_mode		= dmc520_get_scrub_type(pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	mci->ctl_name		= EDAC_CTL_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	mci->dev_name		= dev_name(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	mci->mod_name		= EDAC_MOD_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	edac_op_state = EDAC_OPSTATE_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	pvt->mem_width_in_bytes = dmc520_get_memory_width(pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	dmc520_init_csrow(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	/* Clear interrupts, not affecting other unrelated interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	dmc520_write_reg(pvt, reg_val & (~irq_mask_all),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 			 REG_OFFSET_INTERRUPT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	dmc520_write_reg(pvt, irq_mask_all, REG_OFFSET_INTERRUPT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 		irq = irqs[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 		if (irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 			ret = devm_request_irq(&pdev->dev, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 					       dmc520_isr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 					       dev_name(&pdev->dev), mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 			if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 				edac_printk(KERN_ERR, EDAC_MC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 					    "Failed to request irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 				goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 			registered[idx] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	/* Reset DRAM CE/UE counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	if (irq_mask_all & DRAM_ECC_INT_CE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 		dmc520_get_dram_ecc_error_count(pvt, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	if (irq_mask_all & DRAM_ECC_INT_UE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 		dmc520_get_dram_ecc_error_count(pvt, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	ret = edac_mc_add_mc(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 		edac_printk(KERN_ERR, EDAC_MOD_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 			    "Failed to register with EDAC core\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	/* Enable interrupts, not affecting other unrelated interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	dmc520_write_reg(pvt, reg_val | irq_mask_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 			 REG_OFFSET_INTERRUPT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 		if (registered[idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 			devm_free_irq(&pdev->dev, pvt->irqs[idx], mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	if (mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 		edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int dmc520_edac_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	u32 reg_val, idx, irq_mask_all = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	struct dmc520_edac *pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	mci = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	/* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	dmc520_write_reg(pvt, reg_val & (~irq_mask_all),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 			 REG_OFFSET_INTERRUPT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	/* free irq's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 		if (pvt->irqs[idx] >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 			irq_mask_all |= pvt->masks[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 			devm_free_irq(&pdev->dev, pvt->irqs[idx], mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static const struct of_device_id dmc520_edac_driver_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 	{ .compatible = "arm,dmc-520", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	{ /* end of table */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MODULE_DEVICE_TABLE(of, dmc520_edac_driver_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static struct platform_driver dmc520_edac_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 		.name = "dmc520",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 		.of_match_table = dmc520_edac_driver_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 	.probe = dmc520_edac_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 	.remove = dmc520_edac_remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) module_platform_driver(dmc520_edac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) MODULE_AUTHOR("Rui Zhao <ruizhao@microsoft.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) MODULE_AUTHOR("Lei Wang <lewan@microsoft.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) MODULE_AUTHOR("Shiping Ji <shji@microsoft.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) MODULE_DESCRIPTION("DMC-520 ECC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) MODULE_LICENSE("GPL v2");