^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * cpc925_edac.c, EDAC driver for IBM CPC925 Bridge and Memory Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008 Wind River Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Cao Qingtao <qingtao.cao@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CPC925_EDAC_REVISION " Ver: 1.0.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CPC925_EDAC_MOD_STR "cpc925_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define cpc925_printk(level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) edac_printk(level, "CPC925", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define cpc925_mc_printk(mci, level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) edac_mc_chipset_printk(mci, level, "CPC925", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * CPC925 registers are of 32 bits with bit0 defined at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * most significant bit and bit31 at that of least significant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CPC925_BITS_PER_REG 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CPC925_BIT(nr) (1UL << (CPC925_BITS_PER_REG - 1 - nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * EDAC device names for the error detections of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * CPU Interface and Hypertransport Link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CPC925_CPU_ERR_DEV "cpu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CPC925_HT_LINK_DEV "htlink"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Suppose DDR Refresh cycle is 15.6 microsecond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CPC925_REF_FREQ 0xFA69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CPC925_SCRUB_BLOCK_SIZE 64 /* bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CPC925_NR_CSROWS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * All registers and bits definitions are taken from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * "CPC925 Bridge and Memory Controller User Manual, SA14-2761-02".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * CPU and Memory Controller Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Processor Interface Exception Mask Register (APIMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_APIMASK_OFFSET 0x30070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum apimask_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) APIMASK_DART = CPC925_BIT(0), /* DART Exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) APIMASK_ADI0 = CPC925_BIT(1), /* Handshake Error on PI0_ADI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) APIMASK_ADI1 = CPC925_BIT(2), /* Handshake Error on PI1_ADI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) APIMASK_STAT = CPC925_BIT(3), /* Status Exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) APIMASK_DERR = CPC925_BIT(4), /* Data Error Exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) APIMASK_ADRS0 = CPC925_BIT(5), /* Addressing Exception on PI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) APIMASK_ADRS1 = CPC925_BIT(6), /* Addressing Exception on PI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* BIT(7) Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) APIMASK_ECC_UE_H = CPC925_BIT(8), /* UECC upper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) APIMASK_ECC_CE_H = CPC925_BIT(9), /* CECC upper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) APIMASK_ECC_UE_L = CPC925_BIT(10), /* UECC lower */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) APIMASK_ECC_CE_L = CPC925_BIT(11), /* CECC lower */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) CPU_MASK_ENABLE = (APIMASK_DART | APIMASK_ADI0 | APIMASK_ADI1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) APIMASK_STAT | APIMASK_DERR | APIMASK_ADRS0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) APIMASK_ADRS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ECC_MASK_ENABLE = (APIMASK_ECC_UE_H | APIMASK_ECC_CE_H |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) APIMASK_ECC_UE_L | APIMASK_ECC_CE_L),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define APIMASK_ADI(n) CPC925_BIT(((n)+1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Processor Interface Exception Register (APIEXCP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define REG_APIEXCP_OFFSET 0x30060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) enum apiexcp_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) APIEXCP_DART = CPC925_BIT(0), /* DART Exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) APIEXCP_ADI0 = CPC925_BIT(1), /* Handshake Error on PI0_ADI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) APIEXCP_ADI1 = CPC925_BIT(2), /* Handshake Error on PI1_ADI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) APIEXCP_STAT = CPC925_BIT(3), /* Status Exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) APIEXCP_DERR = CPC925_BIT(4), /* Data Error Exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) APIEXCP_ADRS0 = CPC925_BIT(5), /* Addressing Exception on PI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) APIEXCP_ADRS1 = CPC925_BIT(6), /* Addressing Exception on PI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* BIT(7) Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) APIEXCP_ECC_UE_H = CPC925_BIT(8), /* UECC upper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) APIEXCP_ECC_CE_H = CPC925_BIT(9), /* CECC upper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) APIEXCP_ECC_UE_L = CPC925_BIT(10), /* UECC lower */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) APIEXCP_ECC_CE_L = CPC925_BIT(11), /* CECC lower */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CPU_EXCP_DETECTED = (APIEXCP_DART | APIEXCP_ADI0 | APIEXCP_ADI1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) APIEXCP_STAT | APIEXCP_DERR | APIEXCP_ADRS0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) APIEXCP_ADRS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) UECC_EXCP_DETECTED = (APIEXCP_ECC_UE_H | APIEXCP_ECC_UE_L),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) CECC_EXCP_DETECTED = (APIEXCP_ECC_CE_H | APIEXCP_ECC_CE_L),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ECC_EXCP_DETECTED = (UECC_EXCP_DETECTED | CECC_EXCP_DETECTED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Memory Bus Configuration Register (MBCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define REG_MBCR_OFFSET 0x2190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MBCR_64BITCFG_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MBCR_64BITCFG_MASK (1UL << MBCR_64BITCFG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MBCR_64BITBUS_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MBCR_64BITBUS_MASK (1UL << MBCR_64BITBUS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Memory Bank Mode Register (MBMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define REG_MBMR_OFFSET 0x21C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MBMR_MODE_MAX_VALUE 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MBMR_MODE_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MBMR_MODE_MASK (MBMR_MODE_MAX_VALUE << MBMR_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MBMR_BBA_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MBMR_BBA_MASK (1UL << MBMR_BBA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Memory Bank Boundary Address Register (MBBAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define REG_MBBAR_OFFSET 0x21D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MBBAR_BBA_MAX_VALUE 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MBBAR_BBA_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MBBAR_BBA_MASK (MBBAR_BBA_MAX_VALUE << MBBAR_BBA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Memory Scrub Control Register (MSCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define REG_MSCR_OFFSET 0x2400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MSCR_SCRUB_MOD_MASK 0xC0000000 /* scrub_mod - bit0:1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MSCR_BACKGR_SCRUB 0x40000000 /* 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MSCR_SI_SHIFT 16 /* si - bit8:15*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MSCR_SI_MAX_VALUE 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MSCR_SI_MASK (MSCR_SI_MAX_VALUE << MSCR_SI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Memory Scrub Range Start Register (MSRSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define REG_MSRSR_OFFSET 0x2410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Memory Scrub Range End Register (MSRER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define REG_MSRER_OFFSET 0x2420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Memory Scrub Pattern Register (MSPR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define REG_MSPR_OFFSET 0x2430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Memory Check Control Register (MCCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define REG_MCCR_OFFSET 0x2440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) enum mccr_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MCCR_ECC_EN = CPC925_BIT(0), /* ECC high and low check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Memory Check Range End Register (MCRER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define REG_MCRER_OFFSET 0x2450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Memory Error Address Register (MEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define REG_MEAR_OFFSET 0x2460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MEAR_BCNT_MAX_VALUE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MEAR_BCNT_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MEAR_BCNT_MASK (MEAR_BCNT_MAX_VALUE << MEAR_BCNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MEAR_RANK_MAX_VALUE 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MEAR_RANK_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MEAR_RANK_MASK (MEAR_RANK_MAX_VALUE << MEAR_RANK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MEAR_COL_MAX_VALUE 0x7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MEAR_COL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MEAR_COL_MASK (MEAR_COL_MAX_VALUE << MEAR_COL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MEAR_BANK_MAX_VALUE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MEAR_BANK_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MEAR_BANK_MASK (MEAR_BANK_MAX_VALUE << MEAR_BANK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MEAR_ROW_MASK 0x00003FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Memory Error Syndrome Register (MESR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define REG_MESR_OFFSET 0x2470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MESR_ECC_SYN_H_MASK 0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MESR_ECC_SYN_L_MASK 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Memory Mode Control Register (MMCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define REG_MMCR_OFFSET 0x2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) enum mmcr_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MMCR_REG_DIMM_MODE = CPC925_BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * HyperTransport Link Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * Error Handling/Enumeration Scratch Pad Register (ERRCTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define REG_ERRCTRL_OFFSET 0x70140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) enum errctrl_bits { /* nonfatal interrupts for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ERRCTRL_SERR_NF = CPC925_BIT(0), /* system error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ERRCTRL_CRC_NF = CPC925_BIT(1), /* CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ERRCTRL_RSP_NF = CPC925_BIT(2), /* Response error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ERRCTRL_EOC_NF = CPC925_BIT(3), /* End-Of-Chain error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ERRCTRL_OVF_NF = CPC925_BIT(4), /* Overflow error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ERRCTRL_PROT_NF = CPC925_BIT(5), /* Protocol error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ERRCTRL_RSP_ERR = CPC925_BIT(6), /* Response error received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ERRCTRL_CHN_FAL = CPC925_BIT(7), /* Sync flooding detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) HT_ERRCTRL_ENABLE = (ERRCTRL_SERR_NF | ERRCTRL_CRC_NF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ERRCTRL_RSP_NF | ERRCTRL_EOC_NF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ERRCTRL_OVF_NF | ERRCTRL_PROT_NF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) HT_ERRCTRL_DETECTED = (ERRCTRL_RSP_ERR | ERRCTRL_CHN_FAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Link Configuration and Link Control Register (LINKCTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define REG_LINKCTRL_OFFSET 0x70110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) enum linkctrl_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) LINKCTRL_CRC_ERR = (CPC925_BIT(22) | CPC925_BIT(23)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) LINKCTRL_LINK_FAIL = CPC925_BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) HT_LINKCTRL_DETECTED = (LINKCTRL_CRC_ERR | LINKCTRL_LINK_FAIL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Link FreqCap/Error/Freq/Revision ID Register (LINKERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define REG_LINKERR_OFFSET 0x70120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) enum linkerr_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) LINKERR_EOC_ERR = CPC925_BIT(17), /* End-Of-Chain error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) LINKERR_OVF_ERR = CPC925_BIT(18), /* Receive Buffer Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) LINKERR_PROT_ERR = CPC925_BIT(19), /* Protocol error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) HT_LINKERR_DETECTED = (LINKERR_EOC_ERR | LINKERR_OVF_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) LINKERR_PROT_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Bridge Control Register (BRGCTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define REG_BRGCTRL_OFFSET 0x70300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) enum brgctrl_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) BRGCTRL_DETSERR = CPC925_BIT(0), /* SERR on Secondary Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) BRGCTRL_SECBUSRESET = CPC925_BIT(9), /* Secondary Bus Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Private structure for edac memory controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct cpc925_mc_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void __iomem *vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long total_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int edac_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Private structure for common edac device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct cpc925_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void __iomem *vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) char *ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int edac_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct edac_device_ctl_info *edac_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) void (*init)(struct cpc925_dev_info *dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) void (*exit)(struct cpc925_dev_info *dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) void (*check)(struct edac_device_ctl_info *edac_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Get total memory size from Open Firmware DTB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void get_total_mem(struct cpc925_mc_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct device_node *np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) const unsigned int *reg, *reg_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int len, sw, aw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long start, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) np = of_find_node_by_type(NULL, "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) aw = of_n_addr_cells(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) sw = of_n_size_cells(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) reg = (const unsigned int *)of_get_property(np, "reg", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) reg_end = reg + len/4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pdata->total_mem = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) start = of_read_number(reg, aw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) reg += aw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) size = of_read_number(reg, sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) reg += sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) edac_dbg(1, "start 0x%lx, size 0x%lx\n", start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pdata->total_mem += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) } while (reg < reg_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) edac_dbg(0, "total_mem 0x%lx\n", pdata->total_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static void cpc925_init_csrows(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct cpc925_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct csrow_info *csrow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) enum dev_type dtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int index, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 mbmr, mbbar, bba, grain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned long row_size, nr_pages, last_nr_pages = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) get_total_mem(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) for (index = 0; index < mci->nr_csrows; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mbmr = __raw_readl(pdata->vbase + REG_MBMR_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0x20 * index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mbbar = __raw_readl(pdata->vbase + REG_MBBAR_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0x20 + index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) bba = (((mbmr & MBMR_BBA_MASK) >> MBMR_BBA_SHIFT) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ((mbbar & MBBAR_BBA_MASK) >> MBBAR_BBA_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (bba == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) continue; /* not populated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) csrow = mci->csrows[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) row_size = bba * (1UL << 28); /* 256M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) csrow->first_page = last_nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) nr_pages = row_size >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) csrow->last_page = csrow->first_page + nr_pages - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) last_nr_pages = csrow->last_page + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) switch (csrow->nr_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case 1: /* Single channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) grain = 32; /* four-beat burst of 32 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case 2: /* Dual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) grain = 64; /* four-beat burst of 64 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) switch ((mbmr & MBMR_MODE_MASK) >> MBMR_MODE_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case 6: /* 0110, no way to differentiate X8 VS X16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case 5: /* 0101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case 8: /* 1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dtype = DEV_X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case 7: /* 0111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case 9: /* 1001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dtype = DEV_X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dtype = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) for (j = 0; j < csrow->nr_channels; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dimm = csrow->channels[j]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dimm->nr_pages = nr_pages / csrow->nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dimm->mtype = MEM_RDDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dimm->edac_mode = EDAC_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dimm->grain = grain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dimm->dtype = dtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Enable memory controller ECC detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void cpc925_mc_init(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct cpc925_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 apimask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 mccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Enable various ECC error exceptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) apimask = __raw_readl(pdata->vbase + REG_APIMASK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if ((apimask & ECC_MASK_ENABLE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) apimask |= ECC_MASK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __raw_writel(apimask, pdata->vbase + REG_APIMASK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Enable ECC detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mccr = __raw_readl(pdata->vbase + REG_MCCR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if ((mccr & MCCR_ECC_EN) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) mccr |= MCCR_ECC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __raw_writel(mccr, pdata->vbase + REG_MCCR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Disable memory controller ECC detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void cpc925_mc_exit(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * WARNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * We are supposed to clear the ECC error detection bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * and it will be no problem to do so. However, once they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * are cleared here if we want to re-install CPC925 EDAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * module later, setting them up in cpc925_mc_init() will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * trigger machine check exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Also, it's ok to leave ECC error detection bits enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * since they are reset to 1 by default or by boot loader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * Revert DDR column/row/bank addresses into page frame number and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * offset in page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * Suppose memory mode is 0x0111(128-bit mode, identical DIMM pairs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * physical address(PA) bits to column address(CA) bits mappings are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * CA 0 1 2 3 4 5 6 7 8 9 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * PA 59 58 57 56 55 54 53 52 51 50 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * physical address(PA) bits to bank address(BA) bits mappings are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * BA 0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * PA 43 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * physical address(PA) bits to row address(RA) bits mappings are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * RA 0 1 2 3 4 5 6 7 8 9 10 11 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * PA 36 35 34 48 47 46 45 40 41 42 39 38 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void cpc925_mc_get_pfn(struct mem_ctl_info *mci, u32 mear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned long *pfn, unsigned long *offset, int *csrow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 bcnt, rank, col, bank, row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned long pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) bcnt = (mear & MEAR_BCNT_MASK) >> MEAR_BCNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) rank = (mear & MEAR_RANK_MASK) >> MEAR_RANK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) col = (mear & MEAR_COL_MASK) >> MEAR_COL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) bank = (mear & MEAR_BANK_MASK) >> MEAR_BANK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) row = mear & MEAR_ROW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) *csrow = rank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #ifdef CONFIG_EDAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (mci->csrows[rank]->first_page == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) cpc925_mc_printk(mci, KERN_ERR, "ECC occurs in a "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "non-populated csrow, broken hardware?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Revert csrow number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pa = mci->csrows[rank]->first_page << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Revert column address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) col += bcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) for (i = 0; i < 11; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) c = col & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) col >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pa |= c << (14 - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Revert bank address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pa |= bank << 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Revert row address, in 4 steps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) c = row & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) row >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pa |= c << (26 - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) c = row & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) row >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pa |= c << (21 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) c = row & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) row >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pa |= c << (18 - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) c = row & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) row >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pa |= c << (29 - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) *offset = pa & (PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) *pfn = pa >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) edac_dbg(0, "ECC physical address 0x%lx\n", pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int cpc925_mc_find_channel(struct mem_ctl_info *mci, u16 syndrome)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if ((syndrome & MESR_ECC_SYN_H_MASK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if ((syndrome & MESR_ECC_SYN_L_MASK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) cpc925_mc_printk(mci, KERN_INFO, "Unexpected syndrome value: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) syndrome);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Check memory controller registers for ECC errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static void cpc925_mc_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct cpc925_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 apiexcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 mear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 mesr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u16 syndrome;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned long pfn = 0, offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int csrow = 0, channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* APIEXCP is cleared when read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) apiexcp = __raw_readl(pdata->vbase + REG_APIEXCP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if ((apiexcp & ECC_EXCP_DETECTED) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) mesr = __raw_readl(pdata->vbase + REG_MESR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) syndrome = mesr | (MESR_ECC_SYN_H_MASK | MESR_ECC_SYN_L_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mear = __raw_readl(pdata->vbase + REG_MEAR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Revert column/row addresses into page frame number, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) cpc925_mc_get_pfn(mci, mear, &pfn, &offset, &csrow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (apiexcp & CECC_EXCP_DETECTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) cpc925_mc_printk(mci, KERN_INFO, "DRAM CECC Fault\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) channel = cpc925_mc_find_channel(mci, syndrome);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pfn, offset, syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) csrow, channel, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mci->ctl_name, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (apiexcp & UECC_EXCP_DETECTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) cpc925_mc_printk(mci, KERN_INFO, "DRAM UECC Fault\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) pfn, offset, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) csrow, -1, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mci->ctl_name, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) cpc925_mc_printk(mci, KERN_INFO, "Dump registers:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) cpc925_mc_printk(mci, KERN_INFO, "APIMASK 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) __raw_readl(pdata->vbase + REG_APIMASK_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) cpc925_mc_printk(mci, KERN_INFO, "APIEXCP 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) apiexcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Ctrl 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) __raw_readl(pdata->vbase + REG_MSCR_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge Start 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) __raw_readl(pdata->vbase + REG_MSRSR_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge End 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) __raw_readl(pdata->vbase + REG_MSRER_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Pattern 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) __raw_readl(pdata->vbase + REG_MSPR_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Ctrl 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) __raw_readl(pdata->vbase + REG_MCCR_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Rge End 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) __raw_readl(pdata->vbase + REG_MCRER_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) cpc925_mc_printk(mci, KERN_INFO, "Mem Err Address 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mesr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) cpc925_mc_printk(mci, KERN_INFO, "Mem Err Syndrome 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) syndrome);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /******************** CPU err device********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static u32 cpc925_cpu_mask_disabled(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct device_node *cpunode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* use cached value if available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (mask != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mask = APIMASK_ADI0 | APIMASK_ADI1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) for_each_of_cpu_node(cpunode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) const u32 *reg = of_get_property(cpunode, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (reg == NULL || *reg > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cpc925_printk(KERN_ERR, "Bad reg value at %pOF\n", cpunode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mask &= ~APIMASK_ADI(*reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (mask != (APIMASK_ADI0 | APIMASK_ADI1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* We assume that each CPU sits on it's own PI and that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * for present CPUs the reg property equals to the PI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * interface id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) cpc925_printk(KERN_WARNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) "Assuming PI id is equal to CPU MPIC id!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Enable CPU Errors detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static void cpc925_cpu_init(struct cpc925_dev_info *dev_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 apimask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u32 cpumask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) cpumask = cpc925_cpu_mask_disabled();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (apimask & cpumask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) cpc925_printk(KERN_WARNING, "CPU(s) not present, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "but enabled in APIMASK, disabling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) apimask &= ~cpumask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if ((apimask & CPU_MASK_ENABLE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) apimask |= CPU_MASK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) __raw_writel(apimask, dev_info->vbase + REG_APIMASK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Disable CPU Errors detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static void cpc925_cpu_exit(struct cpc925_dev_info *dev_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * WARNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * We are supposed to clear the CPU error detection bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * and it will be no problem to do so. However, once they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * are cleared here if we want to re-install CPC925 EDAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * module later, setting them up in cpc925_cpu_init() will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * trigger machine check exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * Also, it's ok to leave CPU error detection bits enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * since they are reset to 1 by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Check for CPU Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static void cpc925_cpu_check(struct edac_device_ctl_info *edac_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct cpc925_dev_info *dev_info = edac_dev->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 apiexcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u32 apimask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* APIEXCP is cleared when read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) apiexcp = __raw_readl(dev_info->vbase + REG_APIEXCP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if ((apiexcp & CPU_EXCP_DETECTED) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if ((apiexcp & ~cpc925_cpu_mask_disabled()) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) cpc925_printk(KERN_INFO, "Processor Interface Fault\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) "Processor Interface register dump:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) cpc925_printk(KERN_INFO, "APIMASK 0x%08x\n", apimask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) cpc925_printk(KERN_INFO, "APIEXCP 0x%08x\n", apiexcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /******************** HT Link err device****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Enable HyperTransport Link Error detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static void cpc925_htlink_init(struct cpc925_dev_info *dev_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u32 ht_errctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if ((ht_errctrl & HT_ERRCTRL_ENABLE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ht_errctrl |= HT_ERRCTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Disable HyperTransport Link Error detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static void cpc925_htlink_exit(struct cpc925_dev_info *dev_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u32 ht_errctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ht_errctrl &= ~HT_ERRCTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Check for HyperTransport Link errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static void cpc925_htlink_check(struct edac_device_ctl_info *edac_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct cpc925_dev_info *dev_info = edac_dev->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u32 brgctrl = __raw_readl(dev_info->vbase + REG_BRGCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 linkctrl = __raw_readl(dev_info->vbase + REG_LINKCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u32 errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u32 linkerr = __raw_readl(dev_info->vbase + REG_LINKERR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (!((brgctrl & BRGCTRL_DETSERR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) (linkctrl & HT_LINKCTRL_DETECTED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) (errctrl & HT_ERRCTRL_DETECTED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) (linkerr & HT_LINKERR_DETECTED)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) cpc925_printk(KERN_INFO, "HT Link Fault\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) "HT register dump:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) cpc925_printk(KERN_INFO, "Bridge Ctrl 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) brgctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) cpc925_printk(KERN_INFO, "Link Config Ctrl 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) linkctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) cpc925_printk(KERN_INFO, "Error Enum and Ctrl 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) errctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) cpc925_printk(KERN_INFO, "Link Error 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) linkerr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Clear by write 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (brgctrl & BRGCTRL_DETSERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) __raw_writel(BRGCTRL_DETSERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dev_info->vbase + REG_BRGCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (linkctrl & HT_LINKCTRL_DETECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) __raw_writel(HT_LINKCTRL_DETECTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev_info->vbase + REG_LINKCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Initiate Secondary Bus Reset to clear the chain failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (errctrl & ERRCTRL_CHN_FAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) __raw_writel(BRGCTRL_SECBUSRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_info->vbase + REG_BRGCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (errctrl & ERRCTRL_RSP_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) __raw_writel(ERRCTRL_RSP_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev_info->vbase + REG_ERRCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (linkerr & HT_LINKERR_DETECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) __raw_writel(HT_LINKERR_DETECTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_info->vbase + REG_LINKERR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static struct cpc925_dev_info cpc925_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .ctl_name = CPC925_CPU_ERR_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .init = cpc925_cpu_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .exit = cpc925_cpu_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .check = cpc925_cpu_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .ctl_name = CPC925_HT_LINK_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .init = cpc925_htlink_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .exit = cpc925_htlink_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .check = cpc925_htlink_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * Add CPU Err detection and HyperTransport Link Err detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * as common "edac_device", they have no corresponding device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * nodes in the Open Firmware DTB and we have to add platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * devices for them. Also, they will share the MMIO with that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * of memory controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static void cpc925_add_edac_devices(void __iomem *vbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct cpc925_dev_info *dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (!vbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) cpc925_printk(KERN_ERR, "MMIO not established yet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_info->vbase = vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dev_info->pdev = platform_device_register_simple(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev_info->ctl_name, 0, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (IS_ERR(dev_info->pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) cpc925_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "Can't register platform device for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * Don't have to allocate private structure but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * make use of cpc925_devs[] instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dev_info->edac_idx = edac_device_alloc_index();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_info->edac_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) edac_device_alloc_ctl_info(0, dev_info->ctl_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 1, NULL, 0, 0, NULL, 0, dev_info->edac_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (!dev_info->edac_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) cpc925_printk(KERN_ERR, "No memory for edac device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev_info->edac_dev->pvt_info = dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_info->edac_dev->dev = &dev_info->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_info->edac_dev->ctl_name = dev_info->ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev_info->edac_dev->mod_name = CPC925_EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev_info->edac_dev->dev_name = dev_name(&dev_info->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (edac_op_state == EDAC_OPSTATE_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dev_info->edac_dev->edac_check = dev_info->check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (dev_info->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dev_info->init(dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (edac_device_add_device(dev_info->edac_dev) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) cpc925_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) "Unable to add edac device for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) edac_dbg(0, "Successfully added edac device for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (dev_info->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev_info->exit(dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) edac_device_free_ctl_info(dev_info->edac_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) platform_device_unregister(dev_info->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * Delete the common "edac_device" for CPU Err Detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * and HyperTransport Link Err Detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static void cpc925_del_edac_devices(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct cpc925_dev_info *dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (dev_info->edac_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) edac_device_del_device(dev_info->edac_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) edac_device_free_ctl_info(dev_info->edac_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) platform_device_unregister(dev_info->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (dev_info->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) dev_info->exit(dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) edac_dbg(0, "Successfully deleted edac device for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Convert current back-ground scrub rate into byte/sec bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct cpc925_mc_pdata *pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u32 mscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u8 si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) edac_dbg(0, "Mem Scrub Ctrl Register 0x%x\n", mscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) (si == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) cpc925_mc_printk(mci, KERN_INFO, "Scrub mode not enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) bw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) bw = CPC925_SCRUB_BLOCK_SIZE * 0xFA67 / si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* Return 0 for single channel; 1 for dual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static int cpc925_mc_get_channels(void __iomem *vbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int dual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u32 mbcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) mbcr = __raw_readl(vbase + REG_MBCR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * Dual channel only when 128-bit wide physical bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * and 128-bit configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (((mbcr & MBCR_64BITCFG_MASK) == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ((mbcr & MBCR_64BITBUS_MASK) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dual = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) edac_dbg(0, "%s channel\n", (dual > 0) ? "Dual" : "Single");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return dual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static int cpc925_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int edac_mc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) void __iomem *vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct cpc925_mc_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int res = 0, nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) edac_dbg(0, "%s platform device found!\n", pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (!devres_open_group(&pdev->dev, cpc925_probe, GFP_KERNEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) res = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) cpc925_printk(KERN_ERR, "Unable to get resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) res = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (!devm_request_mem_region(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) r->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) resource_size(r),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) pdev->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) cpc925_printk(KERN_ERR, "Unable to request mem region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) res = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) vbase = devm_ioremap(&pdev->dev, r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (!vbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) cpc925_printk(KERN_ERR, "Unable to ioremap device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) res = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) nr_channels = cpc925_mc_get_channels(vbase) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) layers[0].size = CPC925_NR_CSROWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) layers[1].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) layers[1].size = nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) layers[1].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) sizeof(struct cpc925_mc_pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (!mci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) cpc925_printk(KERN_ERR, "No memory for mem_ctl_info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) res = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) pdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) pdata->vbase = vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) pdata->edac_idx = edac_mc_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) pdata->name = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) platform_set_drvdata(pdev, mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) mci->dev_name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) mci->edac_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) mci->mod_name = CPC925_EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) mci->ctl_name = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (edac_op_state == EDAC_OPSTATE_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) mci->edac_check = cpc925_mc_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) mci->scrub_mode = SCRUB_SW_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) mci->set_sdram_scrub_rate = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) mci->get_sdram_scrub_rate = cpc925_get_sdram_scrub_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) cpc925_init_csrows(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* Setup memory controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) cpc925_mc_init(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (edac_mc_add_mc(mci) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) cpc925_mc_printk(mci, KERN_ERR, "Failed edac_mc_add_mc()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) goto err3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) cpc925_add_edac_devices(vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* get this far and it's successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) edac_dbg(0, "success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) err3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) cpc925_mc_exit(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) devm_release_mem_region(&pdev->dev, r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) devres_release_group(&pdev->dev, cpc925_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static int cpc925_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct mem_ctl_info *mci = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * Delete common edac devices before edac mc, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * the former share the MMIO of the latter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) cpc925_del_edac_devices();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) cpc925_mc_exit(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static struct platform_driver cpc925_edac_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .probe = cpc925_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .remove = cpc925_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .name = "cpc925_edac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static int __init cpc925_edac_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) printk(KERN_INFO "IBM CPC925 EDAC driver " CPC925_EDAC_REVISION "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* Only support POLL mode so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) edac_op_state = EDAC_OPSTATE_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ret = platform_driver_register(&cpc925_edac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) printk(KERN_WARNING "Failed to register %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) CPC925_EDAC_MOD_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static void __exit cpc925_edac_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) platform_driver_unregister(&cpc925_edac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) module_init(cpc925_edac_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) module_exit(cpc925_edac_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) MODULE_DESCRIPTION("IBM CPC925 Bridge and MC EDAC kernel module");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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