Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Cell MIC driver for ECC counting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *                <benh@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This file may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/stop_machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/cell-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) struct cell_edac_priv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct cbe_mic_tm_regs __iomem	*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	int				node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	int				chanmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u64				prev_fir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct cell_edac_priv		*priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct csrow_info		*csrow = mci->csrows[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned long			address, pfn, offset, syndrome;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	dev_dbg(mci->pdev, "ECC CE err on node %d, channel %d, ar = 0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		priv->node, chan, ar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	/* Address decoding is likely a bit bogus, to dbl check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	address = (ar & 0xffffffffe0000000ul) >> 29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	if (priv->chanmask == 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		address = (address << 1) | chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	pfn = address >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	offset = address & ~PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	syndrome = (ar & 0x000000001fe00000ul) >> 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	/* TODO: Decoding of the error address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			     csrow->first_page + pfn, offset, syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			     0, chan, -1, "", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct cell_edac_priv		*priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct csrow_info		*csrow = mci->csrows[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned long			address, pfn, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	dev_dbg(mci->pdev, "ECC UE err on node %d, channel %d, ar = 0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		priv->node, chan, ar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	/* Address decoding is likely a bit bogus, to dbl check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	address = (ar & 0xffffffffe0000000ul) >> 29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (priv->chanmask == 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		address = (address << 1) | chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	pfn = address >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	offset = address & ~PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* TODO: Decoding of the error address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			     csrow->first_page + pfn, offset, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			     0, chan, -1, "", "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static void cell_edac_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct cell_edac_priv		*priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u64				fir, addreg, clear = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	fir = in_be64(&priv->regs->mic_fir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (fir != priv->prev_fir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		dev_dbg(mci->pdev, "fir change : 0x%016lx\n", fir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		priv->prev_fir = fir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_SINGLE_0_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		clear |= CBE_MIC_FIR_ECC_SINGLE_0_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		cell_edac_count_ce(mci, 0, addreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_SINGLE_1_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		clear |= CBE_MIC_FIR_ECC_SINGLE_1_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		cell_edac_count_ce(mci, 1, addreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_MULTI_0_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		clear |= CBE_MIC_FIR_ECC_MULTI_0_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		cell_edac_count_ue(mci, 0, addreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_MULTI_1_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		clear |= CBE_MIC_FIR_ECC_MULTI_1_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		cell_edac_count_ue(mci, 1, addreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	/* The procedure for clearing FIR bits is a bit ... weird */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (clear) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		fir &= ~(CBE_MIC_FIR_ECC_ERR_MASK | CBE_MIC_FIR_ECC_SET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		fir |= CBE_MIC_FIR_ECC_RESET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		fir &= ~clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		out_be64(&priv->regs->mic_fir, fir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		(void)in_be64(&priv->regs->mic_fir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		mb();	/* sync up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		fir = in_be64(&priv->regs->mic_fir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		dev_dbg(mci->pdev, "fir clear  : 0x%016lx\n", fir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void cell_edac_init_csrows(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct csrow_info		*csrow = mci->csrows[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct dimm_info		*dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct cell_edac_priv		*priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct device_node		*np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	int				j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u32				nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	for_each_node_by_name(np, "memory") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		/* We "know" that the Cell firmware only creates one entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		 * in the "memory" nodes. If that changes, this code will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		 * need to be adapted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		if (of_address_to_resource(np, 0, &r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		if (of_node_to_nid(np) != priv->node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		csrow->first_page = r.start >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		nr_pages = resource_size(&r) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		csrow->last_page = csrow->first_page + nr_pages - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		for (j = 0; j < csrow->nr_channels; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			dimm = csrow->channels[j]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			dimm->mtype = MEM_XDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			dimm->edac_mode = EDAC_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			dimm->nr_pages = nr_pages / csrow->nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		dev_dbg(mci->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			"Initialized on node %d, chanmask=0x%x,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			" first_page=0x%lx, nr_pages=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			priv->node, priv->chanmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			csrow->first_page, nr_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int cell_edac_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct cbe_mic_tm_regs __iomem	*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct mem_ctl_info		*mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct edac_mc_layer		layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct cell_edac_priv		*priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u64				reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	int				rc, chanmask, num_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	regs = cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(pdev->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (regs == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	edac_op_state = EDAC_OPSTATE_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* Get channel population */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	reg = in_be64(&regs->mic_mnt_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	dev_dbg(&pdev->dev, "MIC_MNT_CFG = 0x%016llx\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	chanmask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (reg & CBE_MIC_MNT_CFG_CHAN_0_POP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		chanmask |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (reg & CBE_MIC_MNT_CFG_CHAN_1_POP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		chanmask |= 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (chanmask == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			 "Yuck ! No channel populated ? Aborting !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	dev_dbg(&pdev->dev, "Initial FIR = 0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		in_be64(&regs->mic_fir));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/* Allocate & init EDAC MC data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	num_chans = chanmask == 3 ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	layers[0].size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	layers[1].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	layers[1].size = num_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	layers[1].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			    sizeof(struct cell_edac_priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (mci == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	priv->regs = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	priv->node = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	priv->chanmask = chanmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	mci->mtype_cap = MEM_FLAG_XDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	mci->edac_cap = EDAC_FLAG_EC | EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	mci->mod_name = "cell_edac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	mci->ctl_name = "MIC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	mci->dev_name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	mci->edac_check = cell_edac_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	cell_edac_init_csrows(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* Register with EDAC core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	rc = edac_mc_add_mc(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		dev_err(&pdev->dev, "failed to register with EDAC core\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int cell_edac_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct platform_driver cell_edac_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.name	= "cbe-mic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.probe		= cell_edac_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.remove		= cell_edac_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int __init cell_edac_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* Sanity check registers data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			      mic_df_ecc_address_0) != 0xf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			      mic_df_ecc_address_1) != 0x1b8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			      mic_df_config) != 0x218);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			      mic_fir) != 0x230);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			      mic_mnt_cfg) != 0x210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			      mic_exc) != 0x208);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return platform_driver_register(&cell_edac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void __exit cell_edac_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	platform_driver_unregister(&cell_edac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) module_init(cell_edac_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) module_exit(cell_edac_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_DESCRIPTION("ECC counting for Cell MIC");