Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Bluefield-specific EDAC driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2019 Mellanox Technologies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DRIVER_NAME		"bluefield-edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * Mellanox BlueField EMI (External Memory Interface) register definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MLXBF_ECC_CNT 0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MLXBF_ECC_CNT__SERR_CNT GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MLXBF_ECC_CNT__DERR_CNT GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MLXBF_ECC_ERR 0x348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MLXBF_ECC_ERR__SECC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MLXBF_ECC_ERR__DECC BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MLXBF_ECC_LATCH_SEL 0x354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MLXBF_ECC_LATCH_SEL__START BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MLXBF_ERR_ADDR_0 0x358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MLXBF_ERR_ADDR_1 0x37c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MLXBF_SYNDROM 0x35c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MLXBF_SYNDROM__DERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MLXBF_SYNDROM__SERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MLXBF_SYNDROM__SYN GENMASK(25, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MLXBF_ADD_INFO 0x364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MLXBF_ADD_INFO__ERR_PRANK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MLXBF_EDAC_MAX_DIMM_PER_MC	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MLXBF_EDAC_ERROR_GRAIN		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * Request MLNX_SIP_GET_DIMM_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * Retrieve information about DIMM on a certain slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * Call register usage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * a0: MLNX_SIP_GET_DIMM_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * a1: (Memory controller index) << 16 | (Dimm index in memory controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * a2-7: not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * Return status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * a0: MLXBF_DIMM_INFO defined below describing the DIMM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * a1-3: not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MLNX_SIP_GET_DIMM_INFO		0x82000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* Format for the SMC response about the memory information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MLXBF_DIMM_INFO__SIZE_GB GENMASK_ULL(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MLXBF_DIMM_INFO__IS_RDIMM BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MLXBF_DIMM_INFO__IS_LRDIMM BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MLXBF_DIMM_INFO__IS_NVDIMM BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MLXBF_DIMM_INFO__RANKS GENMASK_ULL(23, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MLXBF_DIMM_INFO__PACKAGE_X GENMASK_ULL(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) struct bluefield_edac_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	int dimm_ranks[MLXBF_EDAC_MAX_DIMM_PER_MC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	void __iomem *emi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int dimm_per_mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static u64 smc_call1(u64 smc_op, u64 smc_arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	arm_smccc_smc(smc_op, smc_arg, 0, 0, 0, 0, 0, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * Gather the ECC information from the External Memory Interface registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * and report it to the edac handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static void bluefield_gather_report_ecc(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 					int error_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 					int is_single_ecc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct bluefield_edac_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u32 dram_additional_info, err_prank, edea0, edea1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u32 ecc_latch_select, dram_syndrom, serr, derr, syndrom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	enum hw_event_mc_err_type ecc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u64 ecc_dimm_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	int ecc_dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ecc_type = is_single_ecc ? HW_EVENT_ERR_CORRECTED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				   HW_EVENT_ERR_UNCORRECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 * Tell the External Memory Interface to populate the relevant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 * registers with information about the last ECC error occurrence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	ecc_latch_select = MLXBF_ECC_LATCH_SEL__START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	writel(ecc_latch_select, priv->emi_base + MLXBF_ECC_LATCH_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 * Verify that the ECC reported info in the registers is of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 * same type as the one asked to report. If not, just report the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 * error without the detailed information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	dram_syndrom = readl(priv->emi_base + MLXBF_SYNDROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	serr = FIELD_GET(MLXBF_SYNDROM__SERR, dram_syndrom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	derr = FIELD_GET(MLXBF_SYNDROM__DERR, dram_syndrom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	syndrom = FIELD_GET(MLXBF_SYNDROM__SYN, dram_syndrom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if ((is_single_ecc && !serr) || (!is_single_ecc && !derr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		edac_mc_handle_error(ecc_type, mci, error_cnt, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				     0, 0, -1, mci->ctl_name, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	dram_additional_info = readl(priv->emi_base + MLXBF_ADD_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	err_prank = FIELD_GET(MLXBF_ADD_INFO__ERR_PRANK, dram_additional_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ecc_dimm = (err_prank >= 2 && priv->dimm_ranks[0] <= 2) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	edea0 = readl(priv->emi_base + MLXBF_ERR_ADDR_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	edea1 = readl(priv->emi_base + MLXBF_ERR_ADDR_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ecc_dimm_addr = ((u64)edea1 << 32) | edea0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	edac_mc_handle_error(ecc_type, mci, error_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			     PFN_DOWN(ecc_dimm_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			     offset_in_page(ecc_dimm_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			     syndrom, ecc_dimm, 0, 0, mci->ctl_name, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void bluefield_edac_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct bluefield_edac_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	u32 ecc_count, single_error_count, double_error_count, ecc_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * The memory controller might not be initialized by the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 * when there isn't memory, which may lead to bad register readings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (mci->edac_cap == EDAC_FLAG_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	ecc_count = readl(priv->emi_base + MLXBF_ECC_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	single_error_count = FIELD_GET(MLXBF_ECC_CNT__SERR_CNT, ecc_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	double_error_count = FIELD_GET(MLXBF_ECC_CNT__DERR_CNT, ecc_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (single_error_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		ecc_error |= MLXBF_ECC_ERR__SECC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		bluefield_gather_report_ecc(mci, single_error_count, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (double_error_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		ecc_error |= MLXBF_ECC_ERR__DECC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		bluefield_gather_report_ecc(mci, double_error_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Write to clear reported errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (ecc_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		writel(ecc_error, priv->emi_base + MLXBF_ECC_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Initialize the DIMMs information for the given memory controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void bluefield_edac_init_dimms(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct bluefield_edac_priv *priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int mem_ctrl_idx = mci->mc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u64 smc_info, smc_arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	int is_empty = 1, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	for (i = 0; i < priv->dimm_per_mc; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		dimm = mci->dimms[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		smc_arg = mem_ctrl_idx << 16 | i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		smc_info = smc_call1(MLNX_SIP_GET_DIMM_INFO, smc_arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		if (!FIELD_GET(MLXBF_DIMM_INFO__SIZE_GB, smc_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			dimm->mtype = MEM_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		is_empty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		dimm->edac_mode = EDAC_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		if (FIELD_GET(MLXBF_DIMM_INFO__IS_NVDIMM, smc_info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			dimm->mtype = MEM_NVDIMM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		else if (FIELD_GET(MLXBF_DIMM_INFO__IS_LRDIMM, smc_info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			dimm->mtype = MEM_LRDDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		else if (FIELD_GET(MLXBF_DIMM_INFO__IS_RDIMM, smc_info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			dimm->mtype = MEM_RDDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			dimm->mtype = MEM_DDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		dimm->nr_pages =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			FIELD_GET(MLXBF_DIMM_INFO__SIZE_GB, smc_info) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			(SZ_1G / PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		dimm->grain = MLXBF_EDAC_ERROR_GRAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		/* Mem controller for BlueField only supports x4, x8 and x16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		switch (FIELD_GET(MLXBF_DIMM_INFO__PACKAGE_X, smc_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			dimm->dtype = DEV_X4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			dimm->dtype = DEV_X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			dimm->dtype = DEV_X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			dimm->dtype = DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		priv->dimm_ranks[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			FIELD_GET(MLXBF_DIMM_INFO__RANKS, smc_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (is_empty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		mci->edac_cap = EDAC_FLAG_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		mci->edac_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int bluefield_edac_mc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct bluefield_edac_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct edac_mc_layer layers[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct resource *emi_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	unsigned int mc_idx, dimm_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	int rc, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* Read the MSS (Memory SubSystem) index from ACPI table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (device_property_read_u32(dev, "mss_number", &mc_idx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		dev_warn(dev, "bf_edac: MSS number unknown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	/* Read the DIMMs per MC from ACPI table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (device_property_read_u32(dev, "dimm_per_mc", &dimm_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		dev_warn(dev, "bf_edac: DIMMs per MC unknown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (dimm_count > MLXBF_EDAC_MAX_DIMM_PER_MC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		dev_warn(dev, "bf_edac: DIMMs per MC not valid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	emi_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (!emi_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	layers[0].type = EDAC_MC_LAYER_SLOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	layers[0].size = dimm_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	mci = edac_mc_alloc(mc_idx, ARRAY_SIZE(layers), layers, sizeof(*priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	priv = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	priv->dimm_per_mc = dimm_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	priv->emi_base = devm_ioremap_resource(dev, emi_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (IS_ERR(priv->emi_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		dev_err(dev, "failed to map EMI IO resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		ret = PTR_ERR(priv->emi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	mci->pdev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_RDDR4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			 MEM_FLAG_LRDDR4 | MEM_FLAG_NVDIMM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	mci->mod_name = DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	mci->ctl_name = "BlueField_Memory_Controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	mci->dev_name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	mci->edac_check = bluefield_edac_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	/* Initialize mci with the actual populated DIMM information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	bluefield_edac_init_dimms(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	platform_set_drvdata(pdev, mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	/* Register with EDAC core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	rc = edac_mc_add_mc(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		dev_err(dev, "failed to register with EDAC core\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		ret = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	/* Only POLL mode supported so far. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	edac_op_state = EDAC_OPSTATE_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int bluefield_edac_mc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct acpi_device_id bluefield_mc_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{"MLNXBF08", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_DEVICE_TABLE(acpi, bluefield_mc_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static struct platform_driver bluefield_edac_mc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.acpi_match_table = bluefield_mc_acpi_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.probe = bluefield_edac_mc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	.remove = bluefield_edac_mc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) module_platform_driver(bluefield_edac_mc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MODULE_DESCRIPTION("Mellanox BlueField memory edac driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MODULE_AUTHOR("Mellanox Technologies");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MODULE_LICENSE("GPL v2");