^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 Pengutronix, Jan Luebbe <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/hardware/cache-aurora-l2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "edac_mc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "edac_device.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /************************ EDAC MC (DDR RAM) ********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SDRAM_NUM_CS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SDRAM_CONFIG_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SDRAM_CONFIG_ECC_MASK BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SDRAM_CONFIG_REGISTERED_MASK BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SDRAM_CONFIG_BUS_WIDTH_MASK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SDRAM_ADDR_CTRL_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SDRAM_ADDR_CTRL_SIZE_HIGH_OFFSET(cs) (20+cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SDRAM_ADDR_CTRL_SIZE_HIGH_MASK(cs) (0x1 << SDRAM_ADDR_CTRL_SIZE_HIGH_OFFSET(cs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SDRAM_ADDR_CTRL_ADDR_SEL_MASK(cs) BIT(16+cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SDRAM_ADDR_CTRL_SIZE_LOW_OFFSET(cs) (cs*4+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SDRAM_ADDR_CTRL_SIZE_LOW_MASK(cs) (0x3 << SDRAM_ADDR_CTRL_SIZE_LOW_OFFSET(cs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SDRAM_ADDR_CTRL_STRUCT_OFFSET(cs) (cs*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SDRAM_ADDR_CTRL_STRUCT_MASK(cs) (0x3 << SDRAM_ADDR_CTRL_STRUCT_OFFSET(cs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SDRAM_ERR_DATA_H_REG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SDRAM_ERR_DATA_L_REG 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SDRAM_ERR_RECV_ECC_REG 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SDRAM_ERR_RECV_ECC_VALUE_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SDRAM_ERR_CALC_ECC_REG 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SDRAM_ERR_CALC_ECC_ROW_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SDRAM_ERR_CALC_ECC_ROW_MASK (0xffff << SDRAM_ERR_CALC_ECC_ROW_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SDRAM_ERR_CALC_ECC_VALUE_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SDRAM_ERR_ADDR_REG 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SDRAM_ERR_ADDR_BANK_OFFSET 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SDRAM_ERR_ADDR_BANK_MASK (0x7 << SDRAM_ERR_ADDR_BANK_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SDRAM_ERR_ADDR_COL_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SDRAM_ERR_ADDR_COL_MASK (0x7fff << SDRAM_ERR_ADDR_COL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SDRAM_ERR_ADDR_CS_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SDRAM_ERR_ADDR_CS_MASK (0x3 << SDRAM_ERR_ADDR_CS_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SDRAM_ERR_ADDR_TYPE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SDRAM_ERR_CTRL_REG 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SDRAM_ERR_CTRL_THR_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SDRAM_ERR_CTRL_THR_MASK (0xff << SDRAM_ERR_CTRL_THR_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SDRAM_ERR_CTRL_PROP_MASK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SDRAM_ERR_SBE_COUNT_REG 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SDRAM_ERR_DBE_COUNT_REG 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SDRAM_ERR_CAUSE_ERR_REG 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SDRAM_ERR_CAUSE_MSG_REG 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SDRAM_ERR_CAUSE_DBE_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SDRAM_ERR_CAUSE_SBE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SDRAM_RANK_CTRL_REG 0x1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SDRAM_RANK_CTRL_EXIST_MASK(cs) BIT(cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct axp_mc_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* width in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* bank interleaving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bool cs_addr_sel[SDRAM_NUM_CS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) char msg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* derived from "DRAM Address Multiplexing" in the ARMADA XP Functional Spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static uint32_t axp_mc_calc_address(struct axp_mc_drvdata *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) uint8_t cs, uint8_t bank, uint16_t row,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) uint16_t col)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (drvdata->width == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* 64 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (drvdata->cs_addr_sel[cs])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* bank interleaved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return (((row & 0xfff8) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ((bank & 0x7) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ((row & 0x7) << 13) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ((col & 0x3ff) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return (((row & 0xffff << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ((bank & 0x7) << 13) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ((col & 0x3ff)) << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } else if (drvdata->width == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (drvdata->cs_addr_sel[cs])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* bank interleaved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return (((row & 0xfff0) << 15) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ((bank & 0x7) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ((row & 0xf) << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ((col & 0x3ff) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return (((row & 0xffff << 15) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ((bank & 0x7) << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ((col & 0x3ff)) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (drvdata->cs_addr_sel[cs])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* bank interleaved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return (((row & 0xffe0) << 14) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ((bank & 0x7) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ((row & 0x1f) << 11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ((col & 0x3ff) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return (((row & 0xffff << 14) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ((bank & 0x7) << 11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ((col & 0x3ff)) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void axp_mc_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct axp_mc_drvdata *drvdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) uint32_t data_h, data_l, recv_ecc, calc_ecc, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uint32_t cnt_sbe, cnt_dbe, cause_err, cause_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) uint32_t row_val, col_val, bank_val, addr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) uint8_t syndrome_val, cs_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) char *msg = drvdata->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) data_h = readl(drvdata->base + SDRAM_ERR_DATA_H_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) data_l = readl(drvdata->base + SDRAM_ERR_DATA_L_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) recv_ecc = readl(drvdata->base + SDRAM_ERR_RECV_ECC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) calc_ecc = readl(drvdata->base + SDRAM_ERR_CALC_ECC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) addr = readl(drvdata->base + SDRAM_ERR_ADDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) cnt_sbe = readl(drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) cnt_dbe = readl(drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) cause_err = readl(drvdata->base + SDRAM_ERR_CAUSE_ERR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) cause_msg = readl(drvdata->base + SDRAM_ERR_CAUSE_MSG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* clear cause registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) drvdata->base + SDRAM_ERR_CAUSE_ERR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) drvdata->base + SDRAM_ERR_CAUSE_MSG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* clear error counter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (cnt_sbe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) writel(0, drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (cnt_dbe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writel(0, drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!cnt_sbe && !cnt_dbe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!(addr & SDRAM_ERR_ADDR_TYPE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (cnt_sbe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) cnt_sbe--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_warn(mci->pdev, "inconsistent SBE count detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (cnt_dbe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) cnt_dbe--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev_warn(mci->pdev, "inconsistent DBE count detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* report earlier errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (cnt_sbe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) cnt_sbe, /* error count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 0, 0, 0, /* pfn, offset, syndrome */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) -1, -1, -1, /* top, mid, low layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mci->ctl_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "details unavailable (multiple errors)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (cnt_dbe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) cnt_dbe, /* error count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 0, 0, 0, /* pfn, offset, syndrome */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) -1, -1, -1, /* top, mid, low layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mci->ctl_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "details unavailable (multiple errors)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* report details for most recent error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cs_val = (addr & SDRAM_ERR_ADDR_CS_MASK) >> SDRAM_ERR_ADDR_CS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) bank_val = (addr & SDRAM_ERR_ADDR_BANK_MASK) >> SDRAM_ERR_ADDR_BANK_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) row_val = (calc_ecc & SDRAM_ERR_CALC_ECC_ROW_MASK) >> SDRAM_ERR_CALC_ECC_ROW_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) col_val = (addr & SDRAM_ERR_ADDR_COL_MASK) >> SDRAM_ERR_ADDR_COL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) syndrome_val = (recv_ecc ^ calc_ecc) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) addr_val = axp_mc_calc_address(drvdata, cs_val, bank_val, row_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) col_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) msg += sprintf(msg, "row=0x%04x ", row_val); /* 11 chars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) msg += sprintf(msg, "bank=0x%x ", bank_val); /* 9 chars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) msg += sprintf(msg, "col=0x%04x ", col_val); /* 11 chars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) msg += sprintf(msg, "cs=%d", cs_val); /* 4 chars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!(addr & SDRAM_ERR_ADDR_TYPE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 1, /* error count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) addr_val >> PAGE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) addr_val & ~PAGE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) syndrome_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) cs_val, -1, -1, /* top, mid, low layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mci->ctl_name, drvdata->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 1, /* error count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) addr_val >> PAGE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) addr_val & ~PAGE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) syndrome_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cs_val, -1, -1, /* top, mid, low layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mci->ctl_name, drvdata->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void axp_mc_read_config(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct axp_mc_drvdata *drvdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) uint32_t config, addr_ctrl, rank_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int i, cs_struct, cs_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) config = readl(drvdata->base + SDRAM_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (config & SDRAM_CONFIG_BUS_WIDTH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* 64 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) drvdata->width = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) drvdata->width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) addr_ctrl = readl(drvdata->base + SDRAM_ADDR_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) rank_ctrl = readl(drvdata->base + SDRAM_RANK_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) for (i = 0; i < SDRAM_NUM_CS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dimm = mci->dimms[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!(rank_ctrl & SDRAM_RANK_CTRL_EXIST_MASK(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) drvdata->cs_addr_sel[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) !!(addr_ctrl & SDRAM_ADDR_CTRL_ADDR_SEL_MASK(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) cs_struct = (addr_ctrl & SDRAM_ADDR_CTRL_STRUCT_MASK(i)) >> SDRAM_ADDR_CTRL_STRUCT_OFFSET(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) cs_size = ((addr_ctrl & SDRAM_ADDR_CTRL_SIZE_HIGH_MASK(i)) >> (SDRAM_ADDR_CTRL_SIZE_HIGH_OFFSET(i) - 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ((addr_ctrl & SDRAM_ADDR_CTRL_SIZE_LOW_MASK(i)) >> SDRAM_ADDR_CTRL_SIZE_LOW_OFFSET(i)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) switch (cs_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case 0: /* 2GBit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dimm->nr_pages = 524288;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case 1: /* 256MBit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dimm->nr_pages = 65536;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case 2: /* 512MBit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dimm->nr_pages = 131072;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case 3: /* 1GBit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dimm->nr_pages = 262144;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case 4: /* 4GBit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dimm->nr_pages = 1048576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case 5: /* 8GBit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dimm->nr_pages = 2097152;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dimm->grain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dimm->dtype = cs_struct ? DEV_X16 : DEV_X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dimm->mtype = (config & SDRAM_CONFIG_REGISTERED_MASK) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MEM_RDDR3 : MEM_DDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dimm->edac_mode = EDAC_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct of_device_id axp_mc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {.compatible = "marvell,armada-xp-sdram-controller",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_DEVICE_TABLE(of, axp_mc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int axp_mc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct axp_mc_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct edac_mc_layer layers[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) uint32_t config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_err(&pdev->dev, "Unable to get mem resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_err(&pdev->dev, "Unable to map regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) config = readl(base + SDRAM_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!(config & SDRAM_CONFIG_ECC_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_warn(&pdev->dev, "SDRAM ECC is not enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) layers[0].size = SDRAM_NUM_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*drvdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) drvdata = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) drvdata->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) platform_set_drvdata(pdev, mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) id = of_match_device(axp_mc_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mci->edac_check = axp_mc_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mci->mtype_cap = MEM_FLAG_DDR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mci->edac_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mci->mod_name = pdev->dev.driver->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mci->ctl_name = id ? id->compatible : "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mci->dev_name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mci->scrub_mode = SCRUB_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) axp_mc_read_config(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* These SoCs have a reduced width bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (of_machine_is_compatible("marvell,armada380") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) of_machine_is_compatible("marvell,armadaxp-98dx3236"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) drvdata->width /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* configure SBE threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* it seems that SBEs are not captured otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* clear cause registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK), drvdata->base + SDRAM_ERR_CAUSE_ERR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK), drvdata->base + SDRAM_ERR_CAUSE_MSG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* clear counter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) writel(0, drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) writel(0, drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (edac_mc_add_mc(mci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) edac_op_state = EDAC_OPSTATE_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int axp_mc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct mem_ctl_info *mci = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) platform_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct platform_driver axp_mc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .probe = axp_mc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .remove = axp_mc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .name = "armada_xp_mc_edac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .of_match_table = of_match_ptr(axp_mc_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /************************ EDAC Device (L2 Cache) ***************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct aurora_l2_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) char msg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* error injection via debugfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) uint32_t inject_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) uint32_t inject_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) uint8_t inject_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct dentry *debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #ifdef CONFIG_EDAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static void aurora_l2_inject(struct aurora_l2_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) drvdata->inject_addr &= AURORA_ERR_INJECT_CTL_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) drvdata->inject_ctl &= AURORA_ERR_INJECT_CTL_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) writel(0, drvdata->base + AURORA_ERR_INJECT_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) writel(drvdata->inject_mask, drvdata->base + AURORA_ERR_INJECT_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) writel(drvdata->inject_addr | drvdata->inject_ctl, drvdata->base + AURORA_ERR_INJECT_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void aurora_l2_check(struct edac_device_ctl_info *dci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct aurora_l2_drvdata *drvdata = dci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) uint32_t cnt, src, txn, err, attr_cap, addr_cap, way_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int cnt_ce, cnt_ue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) char *msg = drvdata->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) size_t size = sizeof(drvdata->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) size_t len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) cnt = readl(drvdata->base + AURORA_ERR_CNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) attr_cap = readl(drvdata->base + AURORA_ERR_ATTR_CAP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) addr_cap = readl(drvdata->base + AURORA_ERR_ADDR_CAP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) way_cap = readl(drvdata->base + AURORA_ERR_WAY_CAP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cnt_ce = (cnt & AURORA_ERR_CNT_CE_MASK) >> AURORA_ERR_CNT_CE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) cnt_ue = (cnt & AURORA_ERR_CNT_UE_MASK) >> AURORA_ERR_CNT_UE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* clear error counter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (cnt_ce || cnt_ue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) writel(AURORA_ERR_CNT_CLR, drvdata->base + AURORA_ERR_CNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!(attr_cap & AURORA_ERR_ATTR_CAP_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) goto clear_remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) src = (attr_cap & AURORA_ERR_ATTR_SRC_MSK) >> AURORA_ERR_ATTR_SRC_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (src <= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) len += scnprintf(msg+len, size-len, "src=CPU%d ", src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) len += scnprintf(msg+len, size-len, "src=IO ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) txn = (attr_cap & AURORA_ERR_ATTR_TXN_MSK) >> AURORA_ERR_ATTR_TXN_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) switch (txn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) len += scnprintf(msg+len, size-len, "txn=Data-Read ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) len += scnprintf(msg+len, size-len, "txn=Isn-Read ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) len += scnprintf(msg+len, size-len, "txn=Clean-Flush ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) len += scnprintf(msg+len, size-len, "txn=Eviction ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) len += scnprintf(msg+len, size-len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) "txn=Read-Modify-Write ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) err = (attr_cap & AURORA_ERR_ATTR_ERR_MSK) >> AURORA_ERR_ATTR_ERR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) switch (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) len += scnprintf(msg+len, size-len, "err=CorrECC ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) len += scnprintf(msg+len, size-len, "err=UnCorrECC ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) len += scnprintf(msg+len, size-len, "err=TagParity ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) len += scnprintf(msg+len, size-len, "addr=0x%x ", addr_cap & AURORA_ERR_ADDR_CAP_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) len += scnprintf(msg+len, size-len, "index=0x%x ", (way_cap & AURORA_ERR_WAY_IDX_MSK) >> AURORA_ERR_WAY_IDX_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) len += scnprintf(msg+len, size-len, "way=0x%x", (way_cap & AURORA_ERR_WAY_CAP_WAY_MASK) >> AURORA_ERR_WAY_CAP_WAY_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* clear error capture registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) writel(AURORA_ERR_ATTR_CAP_VALID, drvdata->base + AURORA_ERR_ATTR_CAP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* UnCorrECC or TagParity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (cnt_ue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) cnt_ue--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) edac_device_handle_ue(dci, 0, 0, drvdata->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (cnt_ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) cnt_ce--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) edac_device_handle_ce(dci, 0, 0, drvdata->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) clear_remaining:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* report remaining errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) while (cnt_ue--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) edac_device_handle_ue(dci, 0, 0, "details unavailable (multiple errors)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) while (cnt_ce--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) edac_device_handle_ue(dci, 0, 0, "details unavailable (multiple errors)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static void aurora_l2_poll(struct edac_device_ctl_info *dci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #ifdef CONFIG_EDAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct aurora_l2_drvdata *drvdata = dci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) aurora_l2_check(dci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #ifdef CONFIG_EDAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) aurora_l2_inject(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const struct of_device_id aurora_l2_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {.compatible = "marvell,aurora-system-cache",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MODULE_DEVICE_TABLE(of, aurora_l2_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int aurora_l2_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct aurora_l2_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct edac_device_ctl_info *dci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) uint32_t l2x0_aux_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(&pdev->dev, "Unable to get mem resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_err(&pdev->dev, "Unable to map regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) l2x0_aux_ctrl = readl(base + L2X0_AUX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!(l2x0_aux_ctrl & AURORA_ACR_PARITY_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dev_warn(&pdev->dev, "tag parity is not enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!(l2x0_aux_ctrl & AURORA_ACR_ECC_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_warn(&pdev->dev, "data ECC is not enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dci = edac_device_alloc_ctl_info(sizeof(*drvdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) "cpu", 1, "L", 1, 2, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!dci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) drvdata = dci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) drvdata->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dci->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) platform_set_drvdata(pdev, dci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) id = of_match_device(aurora_l2_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dci->edac_check = aurora_l2_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dci->mod_name = pdev->dev.driver->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dci->ctl_name = id ? id->compatible : "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dci->dev_name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* clear registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) writel(AURORA_ERR_CNT_CLR, drvdata->base + AURORA_ERR_CNT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) writel(AURORA_ERR_ATTR_CAP_VALID, drvdata->base + AURORA_ERR_ATTR_CAP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (edac_device_add_device(dci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) edac_device_free_ctl_info(dci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #ifdef CONFIG_EDAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) drvdata->debugfs = edac_debugfs_create_dir(dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (drvdata->debugfs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) edac_debugfs_create_x32("inject_addr", 0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) drvdata->debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) &drvdata->inject_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) edac_debugfs_create_x32("inject_mask", 0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) drvdata->debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) &drvdata->inject_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) edac_debugfs_create_x8("inject_ctl", 0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) drvdata->debugfs, &drvdata->inject_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int aurora_l2_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #ifdef CONFIG_EDAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct aurora_l2_drvdata *drvdata = dci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) edac_debugfs_remove_recursive(drvdata->debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) edac_device_del_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) edac_device_free_ctl_info(dci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) platform_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static struct platform_driver aurora_l2_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .probe = aurora_l2_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .remove = aurora_l2_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .name = "aurora_l2_edac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .of_match_table = of_match_ptr(aurora_l2_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /************************ Driver registration ******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static struct platform_driver * const drivers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) &axp_mc_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) &aurora_l2_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int __init armada_xp_edac_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* only polling is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) edac_op_state = EDAC_OPSTATE_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) res = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) pr_warn("Armada XP EDAC drivers fail to register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) module_init(armada_xp_edac_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static void __exit armada_xp_edac_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) module_exit(armada_xp_edac_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MODULE_AUTHOR("Pengutronix");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MODULE_DESCRIPTION("EDAC Drivers for Marvell Armada XP SDRAM and L2 Cache Controller");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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