^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * amd8131_edac.h, EDAC defs for AMD8131 hypertransport chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008 Wind River Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Cao Qingtao <qingtao.cao@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Benjamin Walsh <benjamin.walsh@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Hu Yongqi <yongqi.hu@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef _AMD8131_EDAC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _AMD8131_EDAC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DEVFN_PCIX_BRIDGE_NORTH_A 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DEVFN_PCIX_BRIDGE_NORTH_B 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DEVFN_PCIX_BRIDGE_SOUTH_A 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DEVFN_PCIX_BRIDGE_SOUTH_B 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * PCI-X Bridge Status and Command Register, DevA:0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_STS_CMD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum sts_cmd_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) STS_CMD_SSE = BIT(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) STS_CMD_SERREN = BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * PCI-X Bridge Interrupt and Bridge Control Register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_INT_CTLR 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum int_ctlr_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) INT_CTLR_DTSE = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) INT_CTLR_DTS = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) INT_CTLR_SERR = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) INT_CTLR_PERR = BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * PCI-X Bridge Memory Base-Limit Register, DevA:0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REG_MEM_LIM 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) enum mem_limit_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MEM_LIMIT_DPE = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MEM_LIMIT_RSE = BIT(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MEM_LIMIT_RMA = BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MEM_LIMIT_RTA = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MEM_LIMIT_STA = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MEM_LIMIT_MDPE = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MEM_LIMIT_MASK = MEM_LIMIT_DPE|MEM_LIMIT_RSE|MEM_LIMIT_RMA|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MEM_LIMIT_RTA|MEM_LIMIT_STA|MEM_LIMIT_MDPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Link Configuration And Control Register, side A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_LNK_CTRL_A 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Link Configuration And Control Register, side B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_LNK_CTRL_B 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum lnk_ctrl_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) LNK_CTRL_CRCERR_A = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) LNK_CTRL_CRCERR_B = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) LNK_CTRL_CRCFEN = BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) enum pcix_bridge_inst {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) NORTH_A = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) NORTH_B = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SOUTH_A = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SOUTH_B = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) NO_BRIDGE = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct amd8131_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) enum pcix_bridge_inst inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int edac_idx; /* pci device index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) char *ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct edac_pci_ctl_info *edac_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * AMD8131 chipset has two pairs of PCIX Bridge and related IOAPIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Controller, and ATCA-6101 has two AMD8131 chipsets, so there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * four PCIX Bridges on ATCA-6101 altogether.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * These PCIX Bridges share the same PCI Device ID and are all of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Function Zero, they could be discrimated by their pci_dev->devfn.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * They share the same set of init/check/exit methods, and their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * private structures are collected in the devices[] array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct amd8131_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u16 err_dev; /* PCI Device ID for AMD8131 APIC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct amd8131_dev_info *devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void (*init)(struct amd8131_dev_info *dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void (*exit)(struct amd8131_dev_info *dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void (*check)(struct edac_pci_ctl_info *edac_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif /* _AMD8131_EDAC_H_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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