Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * amd8131_edac.c, AMD8131 hypertransport chip EDAC kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2008 Wind River Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Authors:	Cao Qingtao <qingtao.cao@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * 		Benjamin Walsh <benjamin.walsh@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * 		Hu Yongqi <yongqi.hu@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "amd8131_edac.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AMD8131_EDAC_REVISION	" Ver: 1.0.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AMD8131_EDAC_MOD_STR	"amd8131_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* Wrapper functions for accessing PCI configuration space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static void edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	ret = pci_read_config_dword(dev, reg, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		printk(KERN_ERR AMD8131_EDAC_MOD_STR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			" PCI Access Read Error at 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	ret = pci_write_config_dword(dev, reg, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		printk(KERN_ERR AMD8131_EDAC_MOD_STR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			" PCI Access Write Error at 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* Support up to two AMD8131 chipsets on a platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static struct amd8131_dev_info amd8131_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	.inst = NORTH_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.devfn = DEVFN_PCIX_BRIDGE_NORTH_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.ctl_name = "AMD8131_PCIX_NORTH_A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.inst = NORTH_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.devfn = DEVFN_PCIX_BRIDGE_NORTH_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.ctl_name = "AMD8131_PCIX_NORTH_B",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.inst = SOUTH_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.devfn = DEVFN_PCIX_BRIDGE_SOUTH_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.ctl_name = "AMD8131_PCIX_SOUTH_A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.inst = SOUTH_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.devfn = DEVFN_PCIX_BRIDGE_SOUTH_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.ctl_name = "AMD8131_PCIX_SOUTH_B",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{.inst = NO_BRIDGE,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static void amd8131_pcix_init(struct amd8131_dev_info *dev_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct pci_dev *dev = dev_info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/* First clear error detection flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (val32 & MEM_LIMIT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		edac_pci_write_dword(dev, REG_MEM_LIM, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* Clear Discard Timer Timedout flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (val32 & INT_CTLR_DTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		edac_pci_write_dword(dev, REG_INT_CTLR, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* Clear CRC Error flag on link side A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (val32 & LNK_CTRL_CRCERR_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* Clear CRC Error flag on link side B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (val32 & LNK_CTRL_CRCERR_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * Then enable all error detections.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 * Setup Discard Timer Sync Flood Enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 * System Error Enable and Parity Error Enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	val32 |= INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	edac_pci_write_dword(dev, REG_INT_CTLR, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* Enable overall SERR Error detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	edac_pci_read_dword(dev, REG_STS_CMD, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	val32 |= STS_CMD_SERREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	edac_pci_write_dword(dev, REG_STS_CMD, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	/* Setup CRC Flood Enable for link side A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	val32 |= LNK_CTRL_CRCFEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* Setup CRC Flood Enable for link side B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	val32 |= LNK_CTRL_CRCFEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void amd8131_pcix_exit(struct amd8131_dev_info *dev_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct pci_dev *dev = dev_info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* Disable SERR, PERR and DTSE Error detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	val32 &= ~(INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	edac_pci_write_dword(dev, REG_INT_CTLR, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* Disable overall System Error detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	edac_pci_read_dword(dev, REG_STS_CMD, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	val32 &= ~STS_CMD_SERREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	edac_pci_write_dword(dev, REG_STS_CMD, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* Disable CRC Sync Flood on link side A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	val32 &= ~LNK_CTRL_CRCFEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* Disable CRC Sync Flood on link side B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	val32 &= ~LNK_CTRL_CRCFEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void amd8131_pcix_check(struct edac_pci_ctl_info *edac_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct amd8131_dev_info *dev_info = edac_dev->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct pci_dev *dev = dev_info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* Check PCI-X Bridge Memory Base-Limit Register for errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (val32 & MEM_LIMIT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		printk(KERN_INFO "Error(s) in mem limit register "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			"on %s bridge\n", dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			"RTA: %d, STA: %d, MDPE: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			val32 & MEM_LIMIT_DPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			val32 & MEM_LIMIT_RSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			val32 & MEM_LIMIT_RMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			val32 & MEM_LIMIT_RTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			val32 & MEM_LIMIT_STA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			val32 & MEM_LIMIT_MDPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		val32 |= MEM_LIMIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		edac_pci_write_dword(dev, REG_MEM_LIM, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* Check if Discard Timer timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (val32 & INT_CTLR_DTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		printk(KERN_INFO "Error(s) in interrupt and control register "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			"on %s bridge\n", dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		printk(KERN_INFO "DTS: %d\n", val32 & INT_CTLR_DTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		val32 |= INT_CTLR_DTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		edac_pci_write_dword(dev, REG_INT_CTLR, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* Check if CRC error happens on link side A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (val32 & LNK_CTRL_CRCERR_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		printk(KERN_INFO "Error(s) in link conf and control register "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			"on %s bridge\n", dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		val32 |= LNK_CTRL_CRCERR_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	/* Check if CRC error happens on link side B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (val32 & LNK_CTRL_CRCERR_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		printk(KERN_INFO "Error(s) in link conf and control register "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			"on %s bridge\n", dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		val32 |= LNK_CTRL_CRCERR_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct amd8131_info amd8131_chipset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.err_dev = PCI_DEVICE_ID_AMD_8131_APIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.devices = amd8131_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.init = amd8131_pcix_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.exit = amd8131_pcix_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.check = amd8131_pcix_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  * There are 4 PCIX Bridges on ATCA-6101 that share the same PCI Device ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * so amd8131_probe() would be called by kernel 4 times, with different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  * address of pci_dev for each of them each time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int amd8131_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct amd8131_dev_info *dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		dev_info++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		if (dev_info->devfn == dev->devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (dev_info->inst == NO_BRIDGE) /* should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 * We can't call pci_get_device() as we are used to do because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 * there are 4 of them but pci_dev_get() instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	dev_info->dev = pci_dev_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (pci_enable_device(dev_info->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		pci_dev_put(dev_info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		printk(KERN_ERR "failed to enable:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			"vendor %x, device %x, devfn %x, name %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			PCI_VENDOR_ID_AMD, amd8131_chipset.err_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			dev_info->devfn, dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 * we do not allocate extra private structure for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 * edac_pci_ctl_info, but make use of existing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 * one instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	dev_info->edac_idx = edac_pci_alloc_index();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	dev_info->edac_dev = edac_pci_alloc_ctl_info(0, dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (!dev_info->edac_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	dev_info->edac_dev->pvt_info = dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	dev_info->edac_dev->dev = &dev_info->dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	dev_info->edac_dev->mod_name = AMD8131_EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	dev_info->edac_dev->ctl_name = dev_info->ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	dev_info->edac_dev->dev_name = dev_name(&dev_info->dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (edac_op_state == EDAC_OPSTATE_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		dev_info->edac_dev->edac_check = amd8131_chipset.check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (amd8131_chipset.init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		amd8131_chipset.init(dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (edac_pci_add_device(dev_info->edac_dev, dev_info->edac_idx) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		printk(KERN_ERR "failed edac_pci_add_device() for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		edac_pci_free_ctl_info(dev_info->edac_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	printk(KERN_INFO "added one device on AMD8131 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		"vendor %x, device %x, devfn %x, name %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		PCI_VENDOR_ID_AMD, amd8131_chipset.err_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		dev_info->devfn, dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void amd8131_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct amd8131_dev_info *dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		dev_info++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		if (dev_info->devfn == dev->devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (dev_info->inst == NO_BRIDGE) /* should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (dev_info->edac_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		edac_pci_del_device(dev_info->edac_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		edac_pci_free_ctl_info(dev_info->edac_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (amd8131_chipset.exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		amd8131_chipset.exit(dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	pci_dev_put(dev_info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct pci_device_id amd8131_edac_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	PCI_VEND_DEV(AMD, 8131_BRIDGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.class = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.class_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.driver_data = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	}			/* table is NULL-terminated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MODULE_DEVICE_TABLE(pci, amd8131_edac_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static struct pci_driver amd8131_edac_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.name = AMD8131_EDAC_MOD_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.probe = amd8131_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.remove = amd8131_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	.id_table = amd8131_edac_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int __init amd8131_edac_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	printk(KERN_INFO "AMD8131 EDAC driver " AMD8131_EDAC_REVISION "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	/* Only POLL mode supported so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	edac_op_state = EDAC_OPSTATE_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return pci_register_driver(&amd8131_edac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void __exit amd8131_edac_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	pci_unregister_driver(&amd8131_edac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) module_init(amd8131_edac_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) module_exit(amd8131_edac_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MODULE_DESCRIPTION("AMD8131 HyperTransport PCI-X Tunnel EDAC kernel module");