^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * amd8111_edac.h, EDAC defs for AMD8111 hypertransport chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008 Wind River Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Cao Qingtao <qingtao.cao@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Benjamin Walsh <benjamin.walsh@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Hu Yongqi <yongqi.hu@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef _AMD8111_EDAC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _AMD8111_EDAC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * PCI Bridge Status and Command Register, DevA:0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define REG_PCI_STSCMD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum pci_stscmd_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PCI_STSCMD_SSE = BIT(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PCI_STSCMD_RMA = BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PCI_STSCMD_RTA = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PCI_STSCMD_SERREN = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PCI_STSCMD_CLEAR_MASK = (PCI_STSCMD_SSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PCI_STSCMD_RMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PCI_STSCMD_RTA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * PCI Bridge Memory Base-Limit Register, DevA:0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_MEM_LIM 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum mem_limit_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MEM_LIMIT_DPE = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MEM_LIMIT_RSE = BIT(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MEM_LIMIT_RMA = BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MEM_LIMIT_RTA = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MEM_LIMIT_STA = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MEM_LIMIT_MDPE = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MEM_LIMIT_CLEAR_MASK = (MEM_LIMIT_DPE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MEM_LIMIT_RSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MEM_LIMIT_RMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MEM_LIMIT_RTA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MEM_LIMIT_STA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MEM_LIMIT_MDPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * HyperTransport Link Control Register, DevA:0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_HT_LINK 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) enum ht_link_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) HT_LINK_LKFAIL = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) HT_LINK_CRCFEN = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) HT_LINK_CLEAR_MASK = (HT_LINK_LKFAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * PCI Bridge Interrupt and Bridge Control, DevA:0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_PCI_INTBRG_CTRL 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) enum pci_intbrg_ctrl_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PCI_INTBRG_CTRL_DTSERREN = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PCI_INTBRG_CTRL_DTSTAT = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PCI_INTBRG_CTRL_MARSP = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PCI_INTBRG_CTRL_SERREN = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PCI_INTBRG_CTRL_PEREN = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PCI_INTBRG_CTRL_CLEAR_MASK = (PCI_INTBRG_CTRL_DTSTAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PCI_INTBRG_CTRL_POLL_MASK = (PCI_INTBRG_CTRL_DTSERREN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PCI_INTBRG_CTRL_MARSP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PCI_INTBRG_CTRL_SERREN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * I/O Control 1 Register, DevB:0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_IO_CTRL_1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) enum io_ctrl_1_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) IO_CTRL_1_NMIONERR = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) IO_CTRL_1_LPC_ERR = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) IO_CTRL_1_PW2LPC = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) IO_CTRL_1_CLEAR_MASK = (IO_CTRL_1_LPC_ERR | IO_CTRL_1_PW2LPC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Legacy I/O Space Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define REG_AT_COMPAT 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) enum at_compat_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) AT_COMPAT_SERR = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) AT_COMPAT_IOCHK = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) AT_COMPAT_CLRIOCHK = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) AT_COMPAT_CLRSERR = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct amd8111_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u16 err_dev; /* PCI Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int edac_idx; /* device index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) char *ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct edac_device_ctl_info *edac_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void (*init)(struct amd8111_dev_info *dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void (*exit)(struct amd8111_dev_info *dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void (*check)(struct edac_device_ctl_info *edac_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct amd8111_pci_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u16 err_dev; /* PCI Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int edac_idx; /* pci index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const char *ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct edac_pci_ctl_info *edac_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void (*init)(struct amd8111_pci_info *dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void (*exit)(struct amd8111_pci_info *dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void (*check)(struct edac_pci_ctl_info *edac_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif /* _AMD8111_EDAC_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags