^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * amd8111_edac.c, AMD8111 Hyper Transport chip EDAC kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008 Wind River Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Cao Qingtao <qingtao.cao@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Benjamin Walsh <benjamin.walsh@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Hu Yongqi <yongqi.hu@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "amd8111_edac.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AMD8111_EDAC_REVISION " Ver: 1.0.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AMD8111_EDAC_MOD_STR "amd8111_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCI_DEVICE_ID_AMD_8111_PCI 0x7460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum amd8111_edac_devs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) LPC_BRIDGE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum amd8111_edac_pcis {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PCI_BRIDGE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Wrapper functions for accessing PCI configuration space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ret = pci_read_config_dword(dev, reg, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) printk(KERN_ERR AMD8111_EDAC_MOD_STR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) " PCI Access Read Error at 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void edac_pci_read_byte(struct pci_dev *dev, int reg, u8 *val8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ret = pci_read_config_byte(dev, reg, val8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) printk(KERN_ERR AMD8111_EDAC_MOD_STR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) " PCI Access Read Error at 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = pci_write_config_dword(dev, reg, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) printk(KERN_ERR AMD8111_EDAC_MOD_STR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) " PCI Access Write Error at 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void edac_pci_write_byte(struct pci_dev *dev, int reg, u8 val8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = pci_write_config_byte(dev, reg, val8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) printk(KERN_ERR AMD8111_EDAC_MOD_STR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) " PCI Access Write Error at 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * device-specific methods for amd8111 PCI Bridge Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Error Reporting and Handling for amd8111 chipset could be found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * in its datasheet 3.1.2 section, P37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void amd8111_pci_bridge_init(struct amd8111_pci_info *pci_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct pci_dev *dev = pci_info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* First clear error detection flags on the host interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Clear SSE/SMA/STA flags in the global status register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (val32 & PCI_STSCMD_CLEAR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Clear CRC and Link Fail flags in HT Link Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) edac_pci_read_dword(dev, REG_HT_LINK, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (val32 & HT_LINK_CLEAR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) edac_pci_write_dword(dev, REG_HT_LINK, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Second clear all fault on the secondary interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Clear error flags in the memory-base limit reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (val32 & MEM_LIMIT_CLEAR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) edac_pci_write_dword(dev, REG_MEM_LIM, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Clear Discard Timer Expired flag in Interrupt/Bridge Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (val32 & PCI_INTBRG_CTRL_CLEAR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Last enable error detections */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (edac_op_state == EDAC_OPSTATE_POLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Enable System Error reporting in global status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val32 |= PCI_STSCMD_SERREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Enable CRC Sync flood packets to HyperTransport Link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) edac_pci_read_dword(dev, REG_HT_LINK, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val32 |= HT_LINK_CRCFEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) edac_pci_write_dword(dev, REG_HT_LINK, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Enable SSE reporting etc in Interrupt control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val32 |= PCI_INTBRG_CTRL_POLL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void amd8111_pci_bridge_exit(struct amd8111_pci_info *pci_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct pci_dev *dev = pci_info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (edac_op_state == EDAC_OPSTATE_POLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Disable System Error reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val32 &= ~PCI_STSCMD_SERREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Disable CRC flood packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) edac_pci_read_dword(dev, REG_HT_LINK, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) val32 &= ~HT_LINK_CRCFEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) edac_pci_write_dword(dev, REG_HT_LINK, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Disable DTSERREN/MARSP/SERREN in Interrupt Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) val32 &= ~PCI_INTBRG_CTRL_POLL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void amd8111_pci_bridge_check(struct edac_pci_ctl_info *edac_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct amd8111_pci_info *pci_info = edac_dev->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct pci_dev *dev = pci_info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 val32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Check out PCI Bridge Status and Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (val32 & PCI_STSCMD_CLEAR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) printk(KERN_INFO "Error(s) in PCI bridge status and command"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "register on device %s\n", pci_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) printk(KERN_INFO "SSE: %d, RMA: %d, RTA: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) (val32 & PCI_STSCMD_SSE) != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) (val32 & PCI_STSCMD_RMA) != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) (val32 & PCI_STSCMD_RTA) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) val32 |= PCI_STSCMD_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Check out HyperTransport Link Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) edac_pci_read_dword(dev, REG_HT_LINK, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (val32 & HT_LINK_LKFAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) printk(KERN_INFO "Error(s) in hypertransport link control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "register on device %s\n", pci_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) printk(KERN_INFO "LKFAIL: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) (val32 & HT_LINK_LKFAIL) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) val32 |= HT_LINK_LKFAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) edac_pci_write_dword(dev, REG_HT_LINK, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Check out PCI Interrupt and Bridge Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (val32 & PCI_INTBRG_CTRL_DTSTAT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) printk(KERN_INFO "Error(s) in PCI interrupt and bridge control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "register on device %s\n", pci_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) printk(KERN_INFO "DTSTAT: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) (val32 & PCI_INTBRG_CTRL_DTSTAT) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) val32 |= PCI_INTBRG_CTRL_DTSTAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Check out PCI Bridge Memory Base-Limit Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (val32 & MEM_LIMIT_CLEAR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "Error(s) in mem limit register on %s device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pci_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "RTA: %d, STA: %d, MDPE: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) (val32 & MEM_LIMIT_DPE) != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) (val32 & MEM_LIMIT_RSE) != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) (val32 & MEM_LIMIT_RMA) != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) (val32 & MEM_LIMIT_RTA) != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) (val32 & MEM_LIMIT_STA) != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) (val32 & MEM_LIMIT_MDPE) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) val32 |= MEM_LIMIT_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) edac_pci_write_dword(dev, REG_MEM_LIM, val32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct resource *legacy_io_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int at_compat_reg_broken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define LEGACY_NR_PORTS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* device-specific methods for amd8111 LPC Bridge device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void amd8111_lpc_bridge_init(struct amd8111_dev_info *dev_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 val8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct pci_dev *dev = dev_info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* First clear REG_AT_COMPAT[SERR, IOCHK] if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) legacy_io_res = request_region(REG_AT_COMPAT, LEGACY_NR_PORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) AMD8111_EDAC_MOD_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!legacy_io_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) printk(KERN_INFO "%s: failed to request legacy I/O region "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "start %d, len %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) REG_AT_COMPAT, LEGACY_NR_PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) val8 = __do_inb(REG_AT_COMPAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (val8 == 0xff) { /* buggy port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) printk(KERN_INFO "%s: port %d is buggy, not supported"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) " by hardware?\n", __func__, REG_AT_COMPAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) at_compat_reg_broken = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) release_region(REG_AT_COMPAT, LEGACY_NR_PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) legacy_io_res = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 out8 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (val8 & AT_COMPAT_SERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) out8 = AT_COMPAT_CLRSERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (val8 & AT_COMPAT_IOCHK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) out8 |= AT_COMPAT_CLRIOCHK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (out8 > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __do_outb(out8, REG_AT_COMPAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Second clear error flags on LPC bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) edac_pci_read_byte(dev, REG_IO_CTRL_1, &val8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (val8 & IO_CTRL_1_CLEAR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) edac_pci_write_byte(dev, REG_IO_CTRL_1, val8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void amd8111_lpc_bridge_exit(struct amd8111_dev_info *dev_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (legacy_io_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) release_region(REG_AT_COMPAT, LEGACY_NR_PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void amd8111_lpc_bridge_check(struct edac_device_ctl_info *edac_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct amd8111_dev_info *dev_info = edac_dev->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct pci_dev *dev = dev_info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 val8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) edac_pci_read_byte(dev, REG_IO_CTRL_1, &val8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (val8 & IO_CTRL_1_CLEAR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "Error(s) in IO control register on %s device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) printk(KERN_INFO "LPC ERR: %d, PW2LPC: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) (val8 & IO_CTRL_1_LPC_ERR) != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) (val8 & IO_CTRL_1_PW2LPC) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) val8 |= IO_CTRL_1_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) edac_pci_write_byte(dev, REG_IO_CTRL_1, val8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (at_compat_reg_broken == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u8 out8 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) val8 = __do_inb(REG_AT_COMPAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (val8 & AT_COMPAT_SERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) out8 = AT_COMPAT_CLRSERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (val8 & AT_COMPAT_IOCHK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) out8 |= AT_COMPAT_CLRIOCHK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (out8 > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) __do_outb(out8, REG_AT_COMPAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) edac_device_handle_ue(edac_dev, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) edac_dev->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* General devices represented by edac_device_ctl_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct amd8111_dev_info amd8111_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) [LPC_BRIDGE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .err_dev = PCI_DEVICE_ID_AMD_8111_LPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .ctl_name = "lpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .init = amd8111_lpc_bridge_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .exit = amd8111_lpc_bridge_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .check = amd8111_lpc_bridge_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* PCI controllers represented by edac_pci_ctl_info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct amd8111_pci_info amd8111_pcis[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [PCI_BRIDGE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .err_dev = PCI_DEVICE_ID_AMD_8111_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .ctl_name = "AMD8111_PCI_Controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .init = amd8111_pci_bridge_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .exit = amd8111_pci_bridge_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .check = amd8111_pci_bridge_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int amd8111_dev_probe(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct amd8111_dev_info *dev_info = &amd8111_devices[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_info->dev = pci_get_device(PCI_VENDOR_ID_AMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_info->err_dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!dev_info->dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) printk(KERN_ERR "EDAC device not found:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "vendor %x, device %x, name %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PCI_VENDOR_ID_AMD, dev_info->err_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (pci_enable_device(dev_info->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) printk(KERN_ERR "failed to enable:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "vendor %x, device %x, name %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PCI_VENDOR_ID_AMD, dev_info->err_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) goto err_dev_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * we do not allocate extra private structure for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * edac_device_ctl_info, but make use of existing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * one instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_info->edac_idx = edac_device_alloc_index();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_info->edac_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) edac_device_alloc_ctl_info(0, dev_info->ctl_name, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) NULL, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) NULL, 0, dev_info->edac_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (!dev_info->edac_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) goto err_dev_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_info->edac_dev->pvt_info = dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_info->edac_dev->dev = &dev_info->dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_info->edac_dev->mod_name = AMD8111_EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_info->edac_dev->ctl_name = dev_info->ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_info->edac_dev->dev_name = dev_name(&dev_info->dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (edac_op_state == EDAC_OPSTATE_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_info->edac_dev->edac_check = dev_info->check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (dev_info->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_info->init(dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (edac_device_add_device(dev_info->edac_dev) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) printk(KERN_ERR "failed to add edac_dev for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto err_edac_free_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) printk(KERN_INFO "added one edac_dev on AMD8111 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "vendor %x, device %x, name %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PCI_VENDOR_ID_AMD, dev_info->err_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) err_edac_free_ctl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) edac_device_free_ctl_info(dev_info->edac_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) err_dev_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pci_dev_put(dev_info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static void amd8111_dev_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct amd8111_dev_info *dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) for (dev_info = amd8111_devices; dev_info->err_dev; dev_info++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (dev_info->dev->device == dev->device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!dev_info->err_dev) /* should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (dev_info->edac_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) edac_device_del_device(dev_info->edac_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) edac_device_free_ctl_info(dev_info->edac_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (dev_info->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_info->exit(dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pci_dev_put(dev_info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int amd8111_pci_probe(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct amd8111_pci_info *pci_info = &amd8111_pcis[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pci_info->dev = pci_get_device(PCI_VENDOR_ID_AMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pci_info->err_dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!pci_info->dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) printk(KERN_ERR "EDAC device not found:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) "vendor %x, device %x, name %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PCI_VENDOR_ID_AMD, pci_info->err_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pci_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (pci_enable_device(pci_info->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) printk(KERN_ERR "failed to enable:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "vendor %x, device %x, name %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PCI_VENDOR_ID_AMD, pci_info->err_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pci_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) goto err_dev_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * we do not allocate extra private structure for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * edac_pci_ctl_info, but make use of existing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * one instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pci_info->edac_idx = edac_pci_alloc_index();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pci_info->edac_dev = edac_pci_alloc_ctl_info(0, pci_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!pci_info->edac_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) goto err_dev_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pci_info->edac_dev->pvt_info = pci_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pci_info->edac_dev->dev = &pci_info->dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pci_info->edac_dev->mod_name = AMD8111_EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pci_info->edac_dev->ctl_name = pci_info->ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pci_info->edac_dev->dev_name = dev_name(&pci_info->dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (edac_op_state == EDAC_OPSTATE_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pci_info->edac_dev->edac_check = pci_info->check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (pci_info->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pci_info->init(pci_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (edac_pci_add_device(pci_info->edac_dev, pci_info->edac_idx) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) printk(KERN_ERR "failed to add edac_pci for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pci_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) goto err_edac_free_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) printk(KERN_INFO "added one edac_pci on AMD8111 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "vendor %x, device %x, name %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PCI_VENDOR_ID_AMD, pci_info->err_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pci_info->ctl_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) err_edac_free_ctl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) edac_pci_free_ctl_info(pci_info->edac_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) err_dev_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pci_dev_put(pci_info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static void amd8111_pci_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct amd8111_pci_info *pci_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) for (pci_info = amd8111_pcis; pci_info->err_dev; pci_info++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (pci_info->dev->device == dev->device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (!pci_info->err_dev) /* should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (pci_info->edac_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) edac_pci_del_device(pci_info->edac_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) edac_pci_free_ctl_info(pci_info->edac_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (pci_info->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pci_info->exit(pci_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pci_dev_put(pci_info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* PCI Device ID talbe for general EDAC device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const struct pci_device_id amd8111_edac_dev_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PCI_VEND_DEV(AMD, 8111_LPC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .class = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .class_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .driver_data = LPC_BRIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) } /* table is NULL-terminated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MODULE_DEVICE_TABLE(pci, amd8111_edac_dev_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct pci_driver amd8111_edac_dev_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .name = "AMD8111_EDAC_DEV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .probe = amd8111_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .remove = amd8111_dev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .id_table = amd8111_edac_dev_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* PCI Device ID table for EDAC PCI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const struct pci_device_id amd8111_edac_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PCI_VEND_DEV(AMD, 8111_PCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .subvendor = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .subdevice = PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .class = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .class_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .driver_data = PCI_BRIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) } /* table is NULL-terminated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) MODULE_DEVICE_TABLE(pci, amd8111_edac_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static struct pci_driver amd8111_edac_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .name = "AMD8111_EDAC_PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .probe = amd8111_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .remove = amd8111_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .id_table = amd8111_edac_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int __init amd8111_edac_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) printk(KERN_INFO "AMD8111 EDAC driver " AMD8111_EDAC_REVISION "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Only POLL mode supported so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) edac_op_state = EDAC_OPSTATE_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) val = pci_register_driver(&amd8111_edac_dev_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) val |= pci_register_driver(&amd8111_edac_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static void __exit amd8111_edac_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pci_unregister_driver(&amd8111_edac_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) pci_unregister_driver(&amd8111_edac_dev_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) module_init(amd8111_edac_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) module_exit(amd8111_edac_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MODULE_DESCRIPTION("AMD8111 HyperTransport I/O Hub EDAC kernel module");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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