^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * AMD 76x Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (C) 2003 Linux Networx (http://lnxi.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Written by Thayne Harbaugh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on work by Dan Hollis <goemon at anime dot net> and others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * http://www.anime.net/~goemon/linux-ecc/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EDAC_MOD_STR "amd76x_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define amd76x_printk(level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) edac_printk(level, "amd76x", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define amd76x_mc_printk(mci, level, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AMD76X_NR_CSROWS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AMD76X_NR_DIMMS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* AMD 76x register addresses - device 0 function 0 - PCI bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 31:16 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 15:14 SERR enabled: x1=ue 1x=ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 13 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 12 diag: disabled, enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 11:10 mode: dis, EC, ECC, ECC+scrub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 9:8 status: x1=ue 1x=ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 7:4 UE cs row
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * 3:0 CE cs row
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 31:26 clock disable 5 - 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 25 SDRAM init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 24 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 23 mode register service
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 22:21 suspend to RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 20 burst refresh enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 19 refresh disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 18 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 17:16 cycles-per-refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 15:8 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 7:0 x4 mode enable 7 - 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 31:23 chip-select base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 22:16 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * 15:7 chip-select mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 6:3 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * 2:1 address mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * 0 chip-select enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct amd76x_error_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 ecc_mode_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) enum amd76x_chips {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) AMD761 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) AMD762
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct amd76x_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const char *ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct amd76x_dev_info amd76x_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [AMD761] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .ctl_name = "AMD761"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [AMD762] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .ctl_name = "AMD762"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static struct edac_pci_ctl_info *amd76x_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * amd76x_get_error_info - fetch error information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @mci: Memory controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @info: Info to fill in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Fetch and store the AMD76x ECC status. Clear pending status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * on the chip so that further errors will be reported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void amd76x_get_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct amd76x_error_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pdev = to_pci_dev(mci->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) &info->ecc_mode_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (info->ecc_mode_status & BIT(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) (u32) BIT(8), (u32) BIT(8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (info->ecc_mode_status & BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) (u32) BIT(9), (u32) BIT(9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * amd76x_process_error_info - Error check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @mci: Memory controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @info: Previously fetched information from chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @handle_errors: 1 if we should do recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Process the chip state and decide if an error has occurred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * A return of 1 indicates an error. Also if handle_errors is true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * then attempt to handle and clean up after the error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int amd76x_process_error_info(struct mem_ctl_info *mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct amd76x_error_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int handle_errors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int error_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) error_found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Check for an uncorrectable error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (info->ecc_mode_status & BIT(8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) error_found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (handle_errors) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) row = (info->ecc_mode_status >> 4) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mci->csrows[row]->first_page, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) row, 0, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mci->ctl_name, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Check for a correctable error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (info->ecc_mode_status & BIT(9)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) error_found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (handle_errors) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) row = info->ecc_mode_status & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) mci->csrows[row]->first_page, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) row, 0, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) mci->ctl_name, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return error_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * amd76x_check - Poll the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @mci: Memory controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Called by the poll handlers this function reads the status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * from the controller and checks for errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void amd76x_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct amd76x_error_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) edac_dbg(3, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) amd76x_get_error_info(mci, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) amd76x_process_error_info(mci, &info, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) enum edac_type edac_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct csrow_info *csrow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 mba, mba_base, mba_mask, dms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for (index = 0; index < mci->nr_csrows; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) csrow = mci->csrows[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dimm = csrow->channels[0]->dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* find the DRAM Chip Select Base address and mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pci_read_config_dword(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!(mba & BIT(0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mba_base = mba & 0xff800000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) csrow->first_page = mba_base >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dimm->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) csrow->last_page = csrow->first_page + dimm->nr_pages - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) csrow->page_mask = mba_mask >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dimm->grain = dimm->nr_pages << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dimm->mtype = MEM_RDDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dimm->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dimm->edac_mode = edac_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * amd76x_probe1 - Perform set up for detected device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @pdev; PCI device detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @dev_idx: Device type index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * We have found an AMD76x and now need to set up the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * controller status reporting. We configure and set up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * memory controller reporting and claim the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const enum edac_type ems_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) EDAC_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) EDAC_EC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) EDAC_SECDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) EDAC_SECDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct edac_mc_layer layers[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 ems;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 ems_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct amd76x_error_info discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ems_mode = (ems >> 10) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) layers[0].size = AMD76X_NR_CSROWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) layers[0].is_virt_csrow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) layers[1].type = EDAC_MC_LAYER_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) layers[1].size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) layers[1].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (mci == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) edac_dbg(0, "mci = %p\n", mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mci->mtype_cap = MEM_FLAG_RDDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mci->edac_cap = ems_mode ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mci->mod_name = EDAC_MOD_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mci->dev_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mci->edac_check = amd76x_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mci->ctl_page_to_phys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) amd76x_get_error_info(mci, &discard); /* clear counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Here we assume that we will never see multiple instances of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * type of memory controller. The ID is therefore hardcoded to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (edac_mc_add_mc(mci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) edac_dbg(3, "failed edac_mc_add_mc()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* allocating generic PCI control info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) amd76x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!amd76x_pci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "%s(): Unable to create PCI control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "%s(): PCI error report via EDAC not setup\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* get this far and it's successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) edac_dbg(3, "success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* returns count (>= 0), or negative on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int amd76x_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* don't need to call pci_enable_device() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return amd76x_probe1(pdev, ent->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * amd76x_remove_one - driver shutdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @pdev: PCI device being handed back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * Called when the driver is unloaded. Find the matching mci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * structure for the device then delete the mci and free the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void amd76x_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) edac_dbg(0, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (amd76x_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) edac_pci_release_generic_ctl(amd76x_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const struct pci_device_id amd76x_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) AMD762},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) AMD761},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) } /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct pci_driver amd76x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .name = EDAC_MOD_STR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .probe = amd76x_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .remove = amd76x_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .id_table = amd76x_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int __init amd76x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Ensure that the OPSTATE is set correctly for POLL or NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) opstate_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return pci_register_driver(&amd76x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static void __exit amd76x_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pci_unregister_driver(&amd76x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) module_init(amd76x_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) module_exit(amd76x_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) module_param(edac_op_state, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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