^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include "amd64_edac.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) static ssize_t amd64_inject_section_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) struct amd64_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) return sprintf(buf, "0x%x\n", pvt->injection.section);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * store error injection section value which refers to one of 4 16-byte sections
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * within a 64-byte cacheline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * range: 0..3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static ssize_t amd64_inject_section_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) const char *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct amd64_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ret = kstrtoul(data, 10, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (value > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) pvt->injection.section = (u32) value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static ssize_t amd64_inject_word_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct amd64_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return sprintf(buf, "0x%x\n", pvt->injection.word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * store error injection word value which refers to one of 9 16-bit word of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 16-byte (128-bit + ECC bits) section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * range: 0..8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static ssize_t amd64_inject_word_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const char *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct amd64_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret = kstrtoul(data, 10, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (value > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) amd64_warn("%s: invalid word 0x%lx\n", __func__, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pvt->injection.word = (u32) value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static ssize_t amd64_inject_ecc_vector_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct amd64_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return sprintf(buf, "0x%x\n", pvt->injection.bit_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * store 16 bit error injection vector which enables injecting errors to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * corresponding bit within the error injection word above. When used during a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * DRAM ECC read, it holds the contents of the of the DRAM ECC bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static ssize_t amd64_inject_ecc_vector_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const char *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct amd64_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = kstrtoul(data, 16, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (value & 0xFFFF0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) amd64_warn("%s: invalid EccVector: 0x%lx\n", __func__, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pvt->injection.bit_map = (u32) value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * fields needed by the injection registers and read the NB Array Data Port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static ssize_t amd64_inject_read_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const char *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct amd64_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 section, word_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = kstrtoul(data, 10, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Form value to choose 16-byte section of cacheline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Issue 'word' and 'bit' along with the READ request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * fields needed by the injection registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static ssize_t amd64_inject_write_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const char *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct amd64_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 section, word_bits, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = kstrtoul(data, 10, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Form value to choose 16-byte section of cacheline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pr_notice_once("Don't forget to decrease MCE polling interval in\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "/sys/bus/machinecheck/devices/machinecheck<CPUNUM>/check_interval\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "so that you can get the error report faster.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) on_each_cpu(disable_caches, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Issue 'word' and 'bit' along with the READ request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* wait until injection happens */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (tmp & F10_NB_ARR_ECC_WR_REQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) on_each_cpu(enable_caches, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * update NUM_INJ_ATTRS in case you add new members
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static DEVICE_ATTR(inject_section, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) amd64_inject_section_show, amd64_inject_section_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static DEVICE_ATTR(inject_word, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) amd64_inject_word_show, amd64_inject_word_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static DEVICE_ATTR(inject_ecc_vector, S_IRUGO | S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) amd64_inject_ecc_vector_show, amd64_inject_ecc_vector_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static DEVICE_ATTR(inject_write, S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) NULL, amd64_inject_write_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static DEVICE_ATTR(inject_read, S_IWUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) NULL, amd64_inject_read_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct attribute *amd64_edac_inj_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) &dev_attr_inject_section.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) &dev_attr_inject_word.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) &dev_attr_inject_ecc_vector.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) &dev_attr_inject_write.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) &dev_attr_inject_read.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static umode_t amd64_edac_inj_is_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct attribute *attr, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct device *dev = kobj_to_dev(kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct amd64_pvt *pvt = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (pvt->fam < 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) const struct attribute_group amd64_edac_inj_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .attrs = amd64_edac_inj_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .is_visible = amd64_edac_inj_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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