Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #include "amd64_edac.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #define EDAC_DCT_ATTR_SHOW(reg)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) static ssize_t amd64_##reg##_show(struct device *dev,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 			       struct device_attribute *mattr,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 			       char *data)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) {									\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	struct mem_ctl_info *mci = to_mci(dev);				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	struct amd64_pvt *pvt = mci->pvt_info;				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 		return sprintf(data, "0x%016llx\n", (u64)pvt->reg);	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) EDAC_DCT_ATTR_SHOW(dhar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) EDAC_DCT_ATTR_SHOW(dbam0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) EDAC_DCT_ATTR_SHOW(top_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) EDAC_DCT_ATTR_SHOW(top_mem2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static ssize_t amd64_hole_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			       struct device_attribute *mattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			       char *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	struct mem_ctl_info *mci = to_mci(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	u64 hole_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	u64 hole_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	u64 hole_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 						 hole_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * update NUM_DBG_ATTRS in case you add new members
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static DEVICE_ATTR(dhar, S_IRUGO, amd64_dhar_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static DEVICE_ATTR(dbam, S_IRUGO, amd64_dbam0_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static DEVICE_ATTR(topmem, S_IRUGO, amd64_top_mem_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static DEVICE_ATTR(topmem2, S_IRUGO, amd64_top_mem2_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static DEVICE_ATTR(dram_hole, S_IRUGO, amd64_hole_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct attribute *amd64_edac_dbg_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	&dev_attr_dhar.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	&dev_attr_dbam.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	&dev_attr_topmem.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	&dev_attr_topmem2.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	&dev_attr_dram_hole.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const struct attribute_group amd64_edac_dbg_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	.attrs = amd64_edac_dbg_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };