^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * AMD64 class Memory Controller kernel module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2009 SoftwareBitMaker.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * GNU General Public License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mmzone.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/cpu_device_id.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/msr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "mce_amd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define amd64_info(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) edac_printk(KERN_INFO, "amd64", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define amd64_warn(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define amd64_err(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define amd64_mc_warn(mci, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define amd64_mc_err(mci, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Throughout the comments in this code, the following terms are used:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * SysAddr, DramAddr, and InputAddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * These terms come directly from the amd64 documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * (AMD publication #26094). They are defined as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * SysAddr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * This is a physical address generated by a CPU core or a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * doing DMA. If generated by a CPU core, a SysAddr is the result of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * a virtual to physical address translation by the CPU core's address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * translation mechanism (MMU).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * DramAddr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * A DramAddr is derived from a SysAddr by subtracting an offset that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * depends on which node the SysAddr maps to and whether the SysAddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * is within a range affected by memory hoisting. The DRAM Base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * determine which node a SysAddr maps to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * is within the range of addresses specified by this register, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * a value x from the DHAR is subtracted from the SysAddr to produce a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * DramAddr. Here, x represents the base address for the node that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * the SysAddr maps to plus an offset due to memory hoisting. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * section 3.4.8 and the comments in amd64_get_dram_hole_info() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * sys_addr_to_dram_addr() below for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * If the SysAddr is not affected by the DHAR then a value y is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * subtracted from the SysAddr to produce a DramAddr. Here, y is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * base address for the node that the SysAddr maps to. See section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * InputAddr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * A DramAddr is translated to an InputAddr before being passed to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * memory controller for the node that the DramAddr is associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * with. The memory controller then maps the InputAddr to a csrow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * If node interleaving is not in use, then the InputAddr has the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * value as the DramAddr. Otherwise, the InputAddr is produced by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * discarding the bits used for node interleaving from the DramAddr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * See section 3.4.4 for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * The memory controller for a given node uses its DRAM CS Base and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * DRAM CS Mask registers to map an InputAddr to a csrow. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * sections 3.5.4 and 3.5.5 for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define EDAC_AMD64_VERSION "3.5.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define EDAC_MOD_STR "amd64_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Extended Model from CPUID, for CPU Revision numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define K8_REV_D 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define K8_REV_E 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define K8_REV_F 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Hardware limit on ChipSelect rows per MC and processors per system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define NUM_CHIPSELECTS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DRAM_RANGES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define NUM_CONTROLLERS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ON true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OFF false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * PCI-defined configuration space registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F6 0x144e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PCI_DEVICE_ID_AMD_19H_DF_F6 0x1656
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Function 1 - Address Map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DRAM_BASE_LO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DRAM_LIMIT_LO 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * F15 M30h D18F1x2[1C:00]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DRAM_CONT_BASE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DRAM_CONT_LIMIT 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * F15 M30h D18F1x2[4C:40]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DRAM_CONT_HIGH_OFF 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DHAR 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* NOTE: Extra mask bit vs K8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DCT_CFG_SEL 0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DRAM_LOCAL_NODE_BASE 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DRAM_LOCAL_NODE_LIM 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DRAM_BASE_HI 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DRAM_LIMIT_HI 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Function 2 - DRAM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DCSB0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DCSB1 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DCSB_CS_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DCSM0 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DCSM1 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DRAM_CONTROL 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DBAM0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DBAM1 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DBAM_MAX_VALUE 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DCLR0 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DCLR1 0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define REVE_WIDTH_128 BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define WIDTH_128 BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DCHR0 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DCHR1 0x194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DDR3_MODE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DCT_SEL_LO 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SWAP_INTLV_REG 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define DCT_SEL_HI 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define F15H_M60H_SCRCTRL 0x1C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define F17H_SCR_BASE_ADDR 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define F17H_SCR_LIMIT_ADDR 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Function 3 - Misc Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define NBCTL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define NBCFG 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define NBCFG_CHIPKILL BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define NBCFG_ECC_ENABLE BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* F3x48: NBSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define F10_NBSL_EXT_ERR_ECC 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define NBSL_PP_OBS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SCRCTRL 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define F10_ONLINE_SPARE 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define F10_NB_ARRAY_ADDR 0xB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define F10_NB_ARRAY_DRAM BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define F10_NB_ARRAY_DATA 0xBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define F10_NB_ARR_ECC_WR_REQ BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SET_NB_DRAM_INJECTION_WRITE(inj) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) (BIT(((inj.word) & 0xF) + 20) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SET_NB_DRAM_INJECTION_READ(inj) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) (BIT(((inj.word) & 0xF) + 20) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) BIT(16) | inj.bit_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define NBCAP 0xE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define NBCAP_CHIPKILL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define NBCAP_SECDED BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define NBCAP_DCT_DUAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define EXT_NB_MCA_CFG 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MSR_MCGCTL_NBE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* F17h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* F0: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DF_DHAR 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* UMC CH register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define UMCCH_BASE_ADDR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define UMCCH_BASE_ADDR_SEC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define UMCCH_ADDR_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define UMCCH_ADDR_MASK_SEC 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define UMCCH_ADDR_CFG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define UMCCH_DIMM_CFG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define UMCCH_UMC_CFG 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define UMCCH_SDP_CTRL 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define UMCCH_ECC_CTRL 0x14C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define UMCCH_ECC_BAD_SYMBOL 0xD90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define UMCCH_UMC_CAP 0xDF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define UMCCH_UMC_CAP_HI 0xDF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* UMC CH bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define UMC_ECC_CHIPKILL_CAP BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define UMC_ECC_ENABLED BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define UMC_SDP_INIT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) enum amd_families {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) K8_CPUS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) F10_CPUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) F15_CPUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) F15_M30H_CPUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) F15_M60H_CPUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) F16_CPUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) F16_M30H_CPUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) F17_CPUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) F17_M10H_CPUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) F17_M30H_CPUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) F17_M60H_CPUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) F17_M70H_CPUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) F19_CPUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) NUM_FAMILIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Error injection control structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct error_injection {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 section;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 bit_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* low and high part of PCI config space regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct reg_pair {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct dram_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct reg_pair base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct reg_pair lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* A DCT chip selects collection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct chip_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 csbases[NUM_CHIPSELECTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 csbases_sec[NUM_CHIPSELECTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 b_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 csmasks[NUM_CHIPSELECTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 csmasks_sec[NUM_CHIPSELECTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u8 m_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct amd64_umc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 dimm_cfg; /* DIMM Configuration reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 umc_cfg; /* Configuration reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 sdp_ctrl; /* SDP Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 ecc_ctrl; /* DRAM ECC Control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 umc_cap_hi; /* Capabilities High reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct amd64_pvt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct low_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* pci_device handles which we utilize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct pci_dev *F0, *F1, *F2, *F3, *F6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u16 mc_node_id; /* MC index of this MC node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 fam; /* CPU family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 model; /* ... model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 stepping; /* ... stepping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int ext_model; /* extended model value of this node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int channel_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Raw registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 dclr0; /* DRAM Configuration Low DCT0 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 dclr1; /* DRAM Configuration Low DCT1 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 dchr0; /* DRAM Configuration High DCT0 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 dchr1; /* DRAM Configuration High DCT1 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 nbcap; /* North Bridge Capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 nbcfg; /* F10 North Bridge Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 dhar; /* DRAM Hoist reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* one for each DCT/UMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct chip_select csels[NUM_CONTROLLERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct dram_range ranges[DRAM_RANGES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u64 top_mem; /* top of memory below 4GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u64 top_mem2; /* top of memory above 4GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 dct_sel_lo; /* DRAM Controller Select Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 dct_sel_hi; /* DRAM Controller Select High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 online_spare; /* On-Line spare Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* x4, x8, or x16 syndromes in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u8 ecc_sym_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* place to store error injection parameters prior to issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct error_injection injection;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* cache the dram_type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) enum mem_type dram_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct amd64_umc *umc; /* UMC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) enum err_codes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DECODE_OK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ERR_NODE = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ERR_CSROW = -2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ERR_CHANNEL = -3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ERR_SYND = -4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ERR_NORM_ADDR = -5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct err_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct mem_ctl_info *src_mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int csrow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u16 syndrome;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static inline u32 get_umc_base(u8 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* chY: 0xY50000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 0x50000 + (channel << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (boot_cpu_data.x86 == 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (boot_cpu_data.x86 == 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static inline u16 extract_syndrome(u64 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (pvt->fam == 0x15 && pvt->model >= 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ((pvt->dct_sel_lo >> 6) & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return ((pvt)->dct_sel_lo >> 6) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * per-node ECC settings descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct ecc_settings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u32 old_nbctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) bool nbctl_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned long nb_mce_enable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned long nb_ecc_prev:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) } flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #ifdef CONFIG_EDAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) extern const struct attribute_group amd64_edac_dbg_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) extern const struct attribute_group amd64_edac_inj_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * Each of the PCI Device IDs types have their own set of hardware accessor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * functions and per device encoding/decoding logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct low_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int (*early_channel_count) (struct amd64_pvt *pvt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct err_info *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned cs_mode, int cs_mask_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct amd64_family_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) const char *ctl_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u16 f0_id, f1_id, f2_id, f6_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Maximum number of memory controllers per die/node. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u8 max_mcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct low_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 *val, const char *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 val, const char *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define amd64_read_pci_cfg(pdev, offset, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define amd64_write_pci_cfg(pdev, offset, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u64 *hole_offset, u64 *hole_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Injection helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static inline void disable_caches(void *dummy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) write_cr0(read_cr0() | X86_CR0_CD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) wbinvd();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static inline void enable_caches(void *dummy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) write_cr0(read_cr0() & ~X86_CR0_CD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (pvt->fam == 0x15 && pvt->model >= 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return (u8) tmp & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static inline u8 dhar_valid(struct amd64_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (pvt->fam == 0x15 && pvt->model >= 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return (tmp >> 1) & BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return (pvt)->dhar & BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (pvt->fam == 0x15 && pvt->model >= 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return (tmp >> 11) & 0x1FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return (pvt)->dct_sel_lo & 0xFFFFF800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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