^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017-2018, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Altera Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _ALTERA_EDAC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _ALTERA_EDAC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* SDRAM Controller CtrlCfg Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CV_CTLCFG_OFST 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* SDRAM Controller CtrlCfg Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CV_CTLCFG_ECC_EN 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CV_CTLCFG_ECC_CORR_EN 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CV_CTLCFG_GEN_SB_ERR 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CV_CTLCFG_GEN_DB_ERR 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CV_CTLCFG_ECC_AUTO_EN (CV_CTLCFG_ECC_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* SDRAM Controller Address Width Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CV_DRAMADDRW_OFST 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* SDRAM Controller Address Widths Field Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRAMADDRW_COLBIT_MASK 0x001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRAMADDRW_COLBIT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRAMADDRW_ROWBIT_MASK 0x03E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRAMADDRW_ROWBIT_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CV_DRAMADDRW_BANKBIT_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CV_DRAMADDRW_CSBIT_MASK 0xE000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CV_DRAMADDRW_CSBIT_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* SDRAM Controller Interface Data Width Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CV_DRAMIFWIDTH_OFST 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* SDRAM Controller Interface Data Width Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CV_DRAMIFWIDTH_16B_ECC 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CV_DRAMIFWIDTH_32B_ECC 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* SDRAM Controller DRAM Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CV_DRAMSTS_OFST 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* SDRAM Controller DRAM Status Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CV_DRAMSTS_SBEERR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CV_DRAMSTS_DBEERR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CV_DRAMSTS_CORR_DROP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* SDRAM Controller DRAM IRQ Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CV_DRAMINTR_OFST 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* SDRAM Controller DRAM IRQ Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CV_DRAMINTR_INTREN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CV_DRAMINTR_SBEMASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CV_DRAMINTR_DBEMASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CV_DRAMINTR_CORRDROPMASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CV_DRAMINTR_INTRCLR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* SDRAM Controller Single Bit Error Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CV_SBECOUNT_OFST 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* SDRAM Controller Double Bit Error Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CV_DBECOUNT_OFST 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* SDRAM Controller ECC Error Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CV_ERRADDR_OFST 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*-----------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* SDRAM Controller EccCtrl Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define A10_ECCCTRL1_OFST 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* SDRAM Controller EccCtrl Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define A10_ECCCTRL1_ECC_EN 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define A10_ECCCTRL1_CNT_RST 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define A10_ECCCTRL1_AWB_CNT_RST 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define A10_ECC_CNT_RESET_MASK (A10_ECCCTRL1_CNT_RST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) A10_ECCCTRL1_AWB_CNT_RST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* SDRAM Controller Address Width Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CV_DRAMADDRW 0xFFC2502C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define A10_DRAMADDRW 0xFFCFA0A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define S10_DRAMADDRW 0xF80110E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* SDRAM Controller Address Widths Field Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DRAMADDRW_COLBIT_MASK 0x001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DRAMADDRW_COLBIT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DRAMADDRW_ROWBIT_MASK 0x03E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DRAMADDRW_ROWBIT_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CV_DRAMADDRW_BANKBIT_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CV_DRAMADDRW_CSBIT_MASK 0xE000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CV_DRAMADDRW_CSBIT_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define A10_DRAMADDRW_BANKBIT_MASK 0x3C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define A10_DRAMADDRW_BANKBIT_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define A10_DRAMADDRW_GRPBIT_MASK 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define A10_DRAMADDRW_GRPBIT_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define A10_DRAMADDRW_CSBIT_MASK 0x70000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define A10_DRAMADDRW_CSBIT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* SDRAM Controller Interface Data Width Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CV_DRAMIFWIDTH 0xFFC25030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define A10_DRAMIFWIDTH 0xFFCFB008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define S10_DRAMIFWIDTH 0xF8011008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* SDRAM Controller Interface Data Width Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CV_DRAMIFWIDTH_16B_ECC 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CV_DRAMIFWIDTH_32B_ECC 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define A10_DRAMIFWIDTH_16B 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define A10_DRAMIFWIDTH_32B 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define A10_DRAMIFWIDTH_64B 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* SDRAM Controller DRAM IRQ Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define A10_ERRINTEN_OFST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* SDRAM Controller DRAM IRQ Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define A10_ERRINTEN_SERRINTEN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define A10_ERRINTEN_DERRINTEN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define A10_ECC_IRQ_EN_MASK (A10_ERRINTEN_SERRINTEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) A10_ERRINTEN_DERRINTEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* SDRAM Interrupt Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define A10_INTMODE_OFST 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define A10_INTMODE_SB_INT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* SDRAM Controller Error Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define A10_INTSTAT_OFST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* SDRAM Controller Error Status Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define A10_INTSTAT_SBEERR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define A10_INTSTAT_DBEERR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* SDRAM Controller ECC Error Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define A10_DERRADDR_OFST 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define A10_SERRADDR_OFST 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* SDRAM Controller ECC Diagnostic Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define A10_DIAGINTTEST_OFST 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define A10_DIAGINT_TSERRA_MASK 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define A10_DIAGINT_TDERRA_MASK 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define A10_SBERR_IRQ 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define A10_DBERR_IRQ 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* SDRAM Single Bit Error Count Compare Set Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define A10_SERRCNTREG_OFST 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define A10_SYMAN_INTMASK_CLR 0xFFD06098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define A10_INTMASK_CLR_OFST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define A10_DDR0_IRQ_MASK BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct altr_sdram_prv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int ecc_ctrl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ecc_ctl_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int ecc_cecnt_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int ecc_uecnt_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int ecc_stat_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int ecc_stat_ce_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int ecc_stat_ue_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int ecc_saddr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ecc_daddr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ecc_irq_en_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ecc_irq_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int ecc_irq_clr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int ecc_irq_clr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ecc_cnt_rst_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int ecc_cnt_rst_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct edac_dev_sysfs_attribute *eccmgr_sysfs_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int ecc_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int ce_set_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int ue_set_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int ce_ue_trgr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Altera SDRAM Memory Controller data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct altr_sdram_mc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct regmap *mc_vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int sb_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int db_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const struct altr_sdram_prv_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /************************** EDAC Device Defines **************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /***** General Device Trigger Defines *****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ALTR_UE_TRIGGER_CHAR 'U' /* Trigger for UE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ALTR_TRIGGER_READ_WRD_CNT 32 /* Line size x 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ALTR_TRIG_OCRAM_BYTE_SIZE 128 /* Line size x 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ALTR_TRIG_L2C_BYTE_SIZE 4096 /* Full Page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /******* Cyclone5 and Arria5 Defines *******/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* OCRAM ECC Management Group Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ALTR_MAN_GRP_OCRAM_ECC_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ALTR_OCR_ECC_REG_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ALTR_OCR_ECC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ALTR_OCR_ECC_INJS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ALTR_OCR_ECC_INJD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ALTR_OCR_ECC_SERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ALTR_OCR_ECC_DERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* L2 ECC Management Group Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ALTR_MAN_GRP_L2_ECC_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ALTR_L2_ECC_REG_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ALTR_L2_ECC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ALTR_L2_ECC_INJS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ALTR_L2_ECC_INJD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Arria10 General ECC Block Module Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ALTR_A10_ECC_CTRL_OFST 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ALTR_A10_ECC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ALTR_A10_ECC_INITA BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ALTR_A10_ECC_INITB BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ALTR_A10_ECC_INITSTAT_OFST 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ALTR_A10_ECC_INITCOMPLETEA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ALTR_A10_ECC_INITCOMPLETEB BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ALTR_A10_ECC_ERRINTEN_OFST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ALTR_A10_ECC_ERRINTENS_OFST 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ALTR_A10_ECC_ERRINTENR_OFST 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ALTR_A10_ECC_SERRINTEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ALTR_A10_ECC_INTMODE_OFST 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ALTR_A10_ECC_INTMODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ALTR_A10_ECC_INTSTAT_OFST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ALTR_A10_ECC_SERRPENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ALTR_A10_ECC_DERRPENA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ALTR_A10_ECC_ERRPENA_MASK (ALTR_A10_ECC_SERRPENA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ALTR_A10_ECC_DERRPENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ALTR_A10_ECC_SERRPENB BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ALTR_A10_ECC_DERRPENB BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define ALTR_A10_ECC_ERRPENB_MASK (ALTR_A10_ECC_SERRPENB | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ALTR_A10_ECC_DERRPENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ALTR_A10_ECC_INTTEST_OFST 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ALTR_A10_ECC_TSERRA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ALTR_A10_ECC_TDERRA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ALTR_A10_ECC_TSERRB BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ALTR_A10_ECC_TDERRB BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* ECC Manager Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define A10_SYSMGR_ECC_INTMASK_SET_OFST 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define A10_SYSMGR_ECC_INTMASK_OCRAM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define A10_SYSMGR_ECC_INTSTAT_SERR_OFST 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define A10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define A10_SYSMGR_ECC_INTSTAT_L2 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define A10_SYSMGR_ECC_INTSTAT_OCRAM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST 0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define A10_SYSGMR_MPU_CLEAR_L2_ECC_SB BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define A10_SYSGMR_MPU_CLEAR_L2_ECC_MB BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Arria 10 L2 ECC Management Group Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define ALTR_A10_L2_ECC_CTL_OFST 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ALTR_A10_L2_ECC_EN_CTL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ALTR_A10_L2_ECC_STATUS 0xFFD060A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define ALTR_A10_L2_ECC_STAT_OFST 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ALTR_A10_L2_ECC_SERR_PEND BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ALTR_A10_L2_ECC_MERR_PEND BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ALTR_A10_L2_ECC_CLR_OFST 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ALTR_A10_L2_ECC_SERR_CLR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define ALTR_A10_L2_ECC_MERR_CLR BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define ALTR_A10_L2_ECC_INJ_OFST ALTR_A10_L2_ECC_CTL_OFST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ALTR_A10_L2_ECC_CE_INJ_MASK 0x00000101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ALTR_A10_L2_ECC_UE_INJ_MASK 0x00010101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Arria 10 OCRAM ECC Management Group Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Arria 10 Ethernet ECC Management Group Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ALTR_A10_COMMON_ECC_EN_CTL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Arria 10 SDMMC ECC Management Group Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ALTR_A10_SDMMC_IRQ_MASK (BIT(16) | BIT(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* A10 ECC Controller memory initialization timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /************* Stratix10 Defines **************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ALTR_S10_ECC_CTRL_SDRAM_OFST 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ALTR_S10_ECC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ALTR_S10_ECC_ERRINTEN_OFST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ALTR_S10_ECC_ERRINTENS_OFST 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ALTR_S10_ECC_ERRINTENR_OFST 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ALTR_S10_ECC_SERRINTEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ALTR_S10_ECC_INTMODE_OFST 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define ALTR_S10_ECC_INTMODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define ALTR_S10_ECC_INTSTAT_OFST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define ALTR_S10_ECC_SERRPENA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define ALTR_S10_ECC_DERRPENA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define ALTR_S10_ECC_ERRPENA_MASK (ALTR_S10_ECC_SERRPENA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ALTR_S10_ECC_DERRPENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ALTR_S10_ECC_INTTEST_OFST 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ALTR_S10_ECC_TSERRA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ALTR_S10_ECC_TDERRA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define ALTR_S10_ECC_TSERRB BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define ALTR_S10_ECC_TDERRB BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define ALTR_S10_DERR_ADDRA_OFST 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Stratix10 ECC Manager Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define S10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define S10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Sticky registers for Uncorrected Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define S10_SYSMGR_UE_VAL_OFST 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define S10_SYSMGR_UE_ADDR_OFST 0x224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define S10_DDR0_IRQ_MASK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define S10_DBE_IRQ_MASK 0x3FFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Define ECC Block Offsets for peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define ECC_BLK_ADDRESS_OFST 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define ECC_BLK_RDATA0_OFST 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define ECC_BLK_RDATA1_OFST 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ECC_BLK_RDATA2_OFST 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ECC_BLK_RDATA3_OFST 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ECC_BLK_WDATA0_OFST 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ECC_BLK_WDATA1_OFST 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ECC_BLK_WDATA2_OFST 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define ECC_BLK_WDATA3_OFST 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define ECC_BLK_RECC0_OFST 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define ECC_BLK_RECC1_OFST 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define ECC_BLK_WECC0_OFST 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define ECC_BLK_WECC1_OFST 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define ECC_BLK_DBYTECTRL_OFST 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define ECC_BLK_ACCCTRL_OFST 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ECC_BLK_STARTACC_OFST 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define ECC_XACT_KICK 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define ECC_WORD_WRITE 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define ECC_WRITE_DOVR 0x101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define ECC_WRITE_EDOVR 0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define ECC_READ_EOVR 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define ECC_READ_EDOVR 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct altr_edac_device_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct edac_device_prv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int (*setup)(struct altr_edac_device_dev *device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int ce_clear_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int ue_clear_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int irq_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) void * (*alloc_mem)(size_t size, void **other);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) void (*free_mem)(void *p, size_t size, void *other);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int ecc_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ecc_en_ofst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int ce_set_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int ue_set_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int set_err_ofst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) irqreturn_t (*ecc_irq_handler)(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int trig_alloc_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const struct file_operations *inject_fops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) bool panic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct altr_edac_device_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct list_head next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int sb_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int db_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) const struct edac_device_prv_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct dentry *debugfs_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) char *edac_dev_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct altr_arria10_edac *edac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct edac_device_ctl_info *edac_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct device ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int edac_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct altr_arria10_edac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct regmap *ecc_mgr_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int sb_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int db_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct list_head a10_ecc_devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct notifier_block panic_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #endif /* #ifndef _ALTERA_EDAC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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