Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/edac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "edac_module.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* Registers Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define AL_MC_ECC_CFG		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define AL_MC_ECC_CLEAR		0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define AL_MC_ECC_ERR_COUNT	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define AL_MC_ECC_CE_ADDR0	0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AL_MC_ECC_CE_ADDR1	0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AL_MC_ECC_UE_ADDR0	0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AL_MC_ECC_UE_ADDR1	0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AL_MC_ECC_CE_SYND0	0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AL_MC_ECC_CE_SYND1	0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AL_MC_ECC_CE_SYND2	0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AL_MC_ECC_UE_SYND0	0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AL_MC_ECC_UE_SYND1	0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AL_MC_ECC_UE_SYND2	0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Registers Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AL_MC_ECC_CFG_SCRUB_DISABLED	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AL_MC_ECC_CLEAR_UE_COUNT	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AL_MC_ECC_CLEAR_CE_COUNT	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AL_MC_ECC_CLEAR_UE_ERR		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AL_MC_ECC_CLEAR_CE_ERR		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AL_MC_ECC_ERR_COUNT_UE		GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AL_MC_ECC_ERR_COUNT_CE		GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AL_MC_ECC_CE_ADDR0_RANK		GENMASK(25, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AL_MC_ECC_CE_ADDR0_ROW		GENMASK(17, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define AL_MC_ECC_CE_ADDR1_BG		GENMASK(25, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AL_MC_ECC_CE_ADDR1_BANK		GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define AL_MC_ECC_CE_ADDR1_COLUMN	GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AL_MC_ECC_UE_ADDR0_RANK		GENMASK(25, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define AL_MC_ECC_UE_ADDR0_ROW		GENMASK(17, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define AL_MC_ECC_UE_ADDR1_BG		GENMASK(25, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define AL_MC_ECC_UE_ADDR1_BANK		GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define AL_MC_ECC_UE_ADDR1_COLUMN	GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define DRV_NAME "al_mc_edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define AL_MC_EDAC_MSG_MAX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) struct al_mc_edac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int irq_ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	int irq_ue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static void prepare_msg(char *message, size_t buffer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			enum hw_event_mc_err_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			u8 rank, u32 row, u8 bg, u8 bank, u16 column,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			u32 syn0, u32 syn1, u32 syn2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	snprintf(message, buffer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		 "%s rank=0x%x row=0x%x bg=0x%x bank=0x%x col=0x%x syn0: 0x%x syn1: 0x%x syn2: 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		 type == HW_EVENT_ERR_UNCORRECTED ? "UE" : "CE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		 rank, row, bg, bank, column, syn0, syn1, syn2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int handle_ce(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 eccerrcnt, ecccaddr0, ecccaddr1, ecccsyn0, ecccsyn1, ecccsyn2, row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct al_mc_edac *al_mc = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	char msg[AL_MC_EDAC_MSG_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u16 ce_count, column;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u8 rank, bg, bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ce_count = FIELD_GET(AL_MC_ECC_ERR_COUNT_CE, eccerrcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (!ce_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ecccaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ecccaddr1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ecccsyn0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	ecccsyn1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	ecccsyn2 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	writel_relaxed(AL_MC_ECC_CLEAR_CE_COUNT | AL_MC_ECC_CLEAR_CE_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		       al_mc->mmio_base + AL_MC_ECC_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	dev_dbg(mci->pdev, "eccuaddr0=0x%08x eccuaddr1=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		ecccaddr0, ecccaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	rank = FIELD_GET(AL_MC_ECC_CE_ADDR0_RANK, ecccaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	row = FIELD_GET(AL_MC_ECC_CE_ADDR0_ROW, ecccaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	bg = FIELD_GET(AL_MC_ECC_CE_ADDR1_BG, ecccaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	bank = FIELD_GET(AL_MC_ECC_CE_ADDR1_BANK, ecccaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	column = FIELD_GET(AL_MC_ECC_CE_ADDR1_COLUMN, ecccaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	prepare_msg(msg, sizeof(msg), HW_EVENT_ERR_CORRECTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		    rank, row, bg, bank, column,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		    ecccsyn0, ecccsyn1, ecccsyn2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	spin_lock_irqsave(&al_mc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			     ce_count, 0, 0, 0, 0, 0, -1, mci->ctl_name, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	spin_unlock_irqrestore(&al_mc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return ce_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int handle_ue(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u32 eccerrcnt, eccuaddr0, eccuaddr1, eccusyn0, eccusyn1, eccusyn2, row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct al_mc_edac *al_mc = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	char msg[AL_MC_EDAC_MSG_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u16 ue_count, column;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u8 rank, bg, bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	ue_count = FIELD_GET(AL_MC_ECC_ERR_COUNT_UE, eccerrcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (!ue_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	eccuaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_ADDR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	eccuaddr1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_ADDR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	eccusyn0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_SYND0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	eccusyn1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_SYND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	eccusyn2 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_SYND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	writel_relaxed(AL_MC_ECC_CLEAR_UE_COUNT | AL_MC_ECC_CLEAR_UE_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		       al_mc->mmio_base + AL_MC_ECC_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	dev_dbg(mci->pdev, "eccuaddr0=0x%08x eccuaddr1=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		eccuaddr0, eccuaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	rank = FIELD_GET(AL_MC_ECC_UE_ADDR0_RANK, eccuaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	row = FIELD_GET(AL_MC_ECC_UE_ADDR0_ROW, eccuaddr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	bg = FIELD_GET(AL_MC_ECC_UE_ADDR1_BG, eccuaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	bank = FIELD_GET(AL_MC_ECC_UE_ADDR1_BANK, eccuaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	column = FIELD_GET(AL_MC_ECC_UE_ADDR1_COLUMN, eccuaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	prepare_msg(msg, sizeof(msg), HW_EVENT_ERR_UNCORRECTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		    rank, row, bg, bank, column,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		    eccusyn0, eccusyn1, eccusyn2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	spin_lock_irqsave(&al_mc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			     ue_count, 0, 0, 0, 0, 0, -1, mci->ctl_name, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	spin_unlock_irqrestore(&al_mc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return ue_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void al_mc_edac_check(struct mem_ctl_info *mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct al_mc_edac *al_mc = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (al_mc->irq_ue <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		handle_ue(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (al_mc->irq_ce <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		handle_ce(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static irqreturn_t al_mc_edac_irq_handler_ue(int irq, void *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct platform_device *pdev = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (handle_ue(mci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static irqreturn_t al_mc_edac_irq_handler_ce(int irq, void *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct platform_device *pdev = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (handle_ce(mci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static enum scrub_type get_scrub_mode(void __iomem *mmio_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 ecccfg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	ecccfg0 = readl(mmio_base + AL_MC_ECC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (FIELD_GET(AL_MC_ECC_CFG_SCRUB_DISABLED, ecccfg0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return SCRUB_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return SCRUB_HW_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void devm_al_mc_edac_free(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	edac_mc_free(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void devm_al_mc_edac_del(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	edac_mc_del_mc(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int al_mc_edac_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct edac_mc_layer layers[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct mem_ctl_info *mci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct al_mc_edac *al_mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct dimm_info *dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	mmio_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (IS_ERR(mmio_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		dev_err(&pdev->dev, "failed to ioremap memory (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			PTR_ERR(mmio_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return PTR_ERR(mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	layers[0].size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	layers[0].is_virt_csrow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			    sizeof(struct al_mc_edac));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (!mci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	ret = devm_add_action(&pdev->dev, devm_al_mc_edac_free, mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		edac_mc_free(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	platform_set_drvdata(pdev, mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	al_mc = mci->pvt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	al_mc->mmio_base = mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	al_mc->irq_ue = of_irq_get_byname(pdev->dev.of_node, "ue");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (al_mc->irq_ue <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		dev_dbg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			"no IRQ defined for UE - falling back to polling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	al_mc->irq_ce = of_irq_get_byname(pdev->dev.of_node, "ce");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (al_mc->irq_ce <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		dev_dbg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			"no IRQ defined for CE - falling back to polling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 * In case both interrupts (ue/ce) are to be found, use interrupt mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	 * In case none of the interrupt are foud, use polling mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	 * In case only one interrupt is found, use interrupt mode for it but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	 * keep polling mode enable for the other.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (al_mc->irq_ue <= 0 || al_mc->irq_ce <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		edac_op_state = EDAC_OPSTATE_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		mci->edac_check = al_mc_edac_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		edac_op_state = EDAC_OPSTATE_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	spin_lock_init(&al_mc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	mci->edac_cap = EDAC_FLAG_SECDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	mci->mod_name = DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	mci->ctl_name = "al_mc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	mci->pdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	mci->scrub_mode = get_scrub_mode(mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	dimm = *mci->dimms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	dimm->grain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	ret = edac_mc_add_mc(mci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			"fail to add memory controller device (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	ret = devm_add_action(&pdev->dev, devm_al_mc_edac_del, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		edac_mc_del_mc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (al_mc->irq_ue > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		ret = devm_request_irq(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 				       al_mc->irq_ue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 				       al_mc_edac_irq_handler_ue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 				       IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 				       pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 				       pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 				"failed to request UE IRQ %d (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 				al_mc->irq_ue, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (al_mc->irq_ce > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		ret = devm_request_irq(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 				       al_mc->irq_ce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 				       al_mc_edac_irq_handler_ce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 				       IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 				       pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 				       pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 				"failed to request CE IRQ %d (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 				al_mc->irq_ce, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct of_device_id al_mc_edac_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{ .compatible = "amazon,al-mc-edac", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_DEVICE_TABLE(of, al_mc_edac_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static struct platform_driver al_mc_edac_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.probe = al_mc_edac_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.of_match_table = al_mc_edac_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) module_platform_driver(al_mc_edac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_AUTHOR("Talel Shenhar");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MODULE_DESCRIPTION("Amazon's Annapurna Lab's Memory Controller EDAC Driver");