Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #	EDAC Kconfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #	Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #	Licensed and distributed under the GPL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) config EDAC_ATOMIC_SCRUB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) config EDAC_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) menuconfig EDAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	tristate "EDAC (Error Detection And Correction) reporting"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	depends on HAS_IOMEM && EDAC_SUPPORT && RAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	  EDAC is a subsystem along with hardware-specific drivers designed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	  report hardware errors. These are low-level errors that are reported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	  in the CPU or supporting chipset or other subsystems:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	  memory errors, cache errors, PCI errors, thermal throttling, etc..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	  If unsure, select 'Y'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	  The mailing list for the EDAC project is linux-edac@vger.kernel.org.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) if EDAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) config EDAC_LEGACY_SYSFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	bool "EDAC legacy sysfs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	  Enable the compatibility sysfs nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	  Use 'Y' if your edac utilities aren't ported to work with the newer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	  structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) config EDAC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	bool "Debugging"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	select DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	  This turns on debugging information for the entire EDAC subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	  You do so by inserting edac_module with "edac_debug_level=x." Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	  levels are 0-4 (from low to high) and by default it is set to 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	  Usually you should select 'N' here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) config EDAC_DECODE_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	tristate "Decode MCEs in human-readable form (only on AMD for now)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	depends on CPU_SUP_AMD && X86_MCE_AMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	  Enable this option if you want to decode Machine Check Exceptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	  occurring on your machine in human-readable form.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	  You should definitely say Y here in case you want to decode MCEs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	  which occur really early upon boot, before the module infrastructure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	  has been initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) config EDAC_GHES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	depends on ACPI_APEI_GHES && (EDAC=y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	  Not all machines support hardware-driven error report. Some of those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	  provide a BIOS-driven error report mechanism via ACPI, using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	  APEI/GHES driver. By enabling this option, the error reports provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	  by GHES are sent to userspace via the EDAC API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	  When this option is enabled, it will disable the hardware-driven
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	  mechanisms, if a GHES BIOS is detected, entering into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	  "Firmware First" mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	  It should be noticed that keeping both GHES and a hardware-driven
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	  error mechanism won't work well, as BIOS will race with OS, while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	  reading the error registers. So, if you want to not use "Firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	  first" GHES error mechanism, you should disable GHES either at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	  compilation time or by passing "ghes.disable=1" Kernel parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	  at boot time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	  In doubt, say 'Y'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) config EDAC_AMD64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	tristate "AMD64 (Opteron, Athlon64)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	depends on AMD_NB && EDAC_DECODE_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	  Support for error detection and correction of DRAM ECC errors on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	  the AMD64 families (>= K8) of memory controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) config EDAC_AMD64_ERROR_INJECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	bool "Sysfs HW Error injection facilities"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	depends on EDAC_AMD64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	  Recent Opterons (Family 10h and later) provide for Memory Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	  Injection into the ECC detection circuits. The amd64_edac module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	  allows the operator/user to inject Uncorrectable and Correctable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	  errors into DRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	  When enabled, in each of the respective memory controller directories
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	  (/sys/devices/system/edac/mc/mcX), there are 3 input files:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	  - inject_word (0..8, 16-bit word of 16-byte section),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	  - inject_ecc_vector (hex ecc vector: select bits of inject word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	  In addition, there are two control files, inject_read and inject_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	  which trigger the DRAM ECC Read and Write respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) config EDAC_AL_MC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	tristate "Amazon's Annapurna Lab Memory Controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	depends on (ARCH_ALPINE || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	  Support for error detection and correction for Amazon's Annapurna
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	  Labs Alpine chips which allow 1 bit correction and 2 bits detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) config EDAC_AMD76X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	tristate "AMD 76x (760, 762, 768)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	depends on PCI && X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	  Support for error detection and correction on the AMD 76x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	  series of chipsets used with the Athlon processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) config EDAC_E7XXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	depends on PCI && X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	  Support for error detection and correction on the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	  E7205, E7500, E7501 and E7505 server chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) config EDAC_E752X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	tristate "Intel e752x (e7520, e7525, e7320) and 3100"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	depends on PCI && X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	  Support for error detection and correction on the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	  E7520, E7525, E7320 server chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) config EDAC_I82443BXGX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	tristate "Intel 82443BX/GX (440BX/GX)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	depends on PCI && X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	depends on BROKEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	  Support for error detection and correction on the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	  82443BX/GX memory controllers (440BX/GX chipsets).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) config EDAC_I82875P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	tristate "Intel 82875p (D82875P, E7210)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	depends on PCI && X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	  Support for error detection and correction on the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	  DP82785P and E7210 server chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) config EDAC_I82975X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	tristate "Intel 82975x (D82975x)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	depends on PCI && X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	  Support for error detection and correction on the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	  DP82975x server chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) config EDAC_I3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	tristate "Intel 3000/3010"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	depends on PCI && X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	  Support for error detection and correction on the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	  3000 and 3010 server chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) config EDAC_I3200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	tristate "Intel 3200"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	depends on PCI && X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	  Support for error detection and correction on the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	  3200 and 3210 server chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) config EDAC_IE31200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	tristate "Intel e312xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	depends on PCI && X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	  Support for error detection and correction on the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	  E3-1200 based DRAM controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) config EDAC_X38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	tristate "Intel X38"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	depends on PCI && X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	  Support for error detection and correction on the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	  X38 server chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) config EDAC_I5400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	tristate "Intel 5400 (Seaburg) chipsets"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	depends on PCI && X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	  Support for error detection and correction the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	  i5400 MCH chipset (Seaburg).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) config EDAC_I7CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	tristate "Intel i7 Core (Nehalem) processors"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	depends on PCI && X86 && X86_MCE_INTEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	  Support for error detection and correction the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	  i7 Core (Nehalem) Integrated Memory Controller that exists on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	  newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	  and Xeon 55xx processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) config EDAC_I82860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	tristate "Intel 82860"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	depends on PCI && X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	  Support for error detection and correction on the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	  82860 chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) config EDAC_R82600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	tristate "Radisys 82600 embedded chipset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	depends on PCI && X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	  Support for error detection and correction on the Radisys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	  82600 embedded chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) config EDAC_I5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	tristate "Intel Greencreek/Blackford chipset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	depends on X86 && PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	  Support for error detection and correction the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	  Greekcreek/Blackford chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) config EDAC_I5100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	tristate "Intel San Clemente MCH"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	depends on X86 && PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	  Support for error detection and correction the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	  San Clemente MCH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) config EDAC_I7300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	tristate "Intel Clarksboro MCH"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	depends on X86 && PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	  Support for error detection and correction the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	  Clarksboro MCH (Intel 7300 chipset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) config EDAC_SBRIDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	  Support for error detection and correction the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	  Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) config EDAC_SKX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	tristate "Intel Skylake server Integrated MC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	select DMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	select ACPI_ADXL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	  Support for error detection and correction the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	  Skylake server Integrated Memory Controllers. If your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	  system has non-volatile DIMMs you should also manually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	  select CONFIG_ACPI_NFIT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) config EDAC_I10NM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	tristate "Intel 10nm server Integrated MC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	select DMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	select ACPI_ADXL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	  Support for error detection and correction the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	  10nm server Integrated Memory Controllers. If your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	  system has non-volatile DIMMs you should also manually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	  select CONFIG_ACPI_NFIT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) config EDAC_PND2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	tristate "Intel Pondicherry2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	depends on PCI && X86_64 && X86_MCE_INTEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	  Support for error detection and correction on the Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	  Pondicherry2 Integrated Memory Controller. This SoC IP is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	  first used on the Apollo Lake platform and Denverton
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	  micro-server but may appear on others in the future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) config EDAC_MPC85XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	bool "Freescale MPC83xx / MPC85xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	depends on FSL_SOC && EDAC=y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	  Support for error detection and correction on the Freescale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	  MPC8349, MPC8560, MPC8540, MPC8548, T4240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) config EDAC_LAYERSCAPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	tristate "Freescale Layerscape DDR"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	depends on ARCH_LAYERSCAPE || SOC_LS1021A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	  Support for error detection and correction on Freescale memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	  controllers on Layerscape SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) config EDAC_MV64X60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	tristate "Marvell MV64x60"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	depends on MV64X60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	  Support for error detection and correction on the Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	  MV64360 and MV64460 chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) config EDAC_PASEMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	tristate "PA Semi PWRficient"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	depends on PPC_PASEMI && PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	  Support for error detection and correction on PA Semi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	  PWRficient.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) config EDAC_CELL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	tristate "Cell Broadband Engine memory controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	depends on PPC_CELL_COMMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	  Cell Broadband Engine internal memory controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	  on platform without a hypervisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) config EDAC_PPC4XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	tristate "PPC4xx IBM DDR2 Memory Controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	depends on 4xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	  This enables support for EDAC on the ECC memory used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	  with the IBM DDR2 memory controller found in various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	  PowerPC 4xx embedded processors such as the 405EX[r],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	  440SP, 440SPe, 460EX, 460GT and 460SX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) config EDAC_AMD8131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	tristate "AMD8131 HyperTransport PCI-X Tunnel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	depends on PCI && PPC_MAPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	  AMD8131 HyperTransport PCI-X Tunnel chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	  Note, add more Kconfig dependency if it's adopted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	  on some machine other than Maple.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) config EDAC_AMD8111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	tristate "AMD8111 HyperTransport I/O Hub"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	depends on PCI && PPC_MAPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	  AMD8111 HyperTransport I/O Hub chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	  Note, add more Kconfig dependency if it's adopted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	  on some machine other than Maple.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) config EDAC_CPC925
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	tristate "IBM CPC925 Memory Controller (PPC970FX)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	depends on PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	  IBM CPC925 Bridge and Memory Controller, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	  a companion chip to the PowerPC 970 family of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	  processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) config EDAC_HIGHBANK_MC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	tristate "Highbank Memory Controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	depends on ARCH_HIGHBANK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	  Calxeda Highbank memory controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) config EDAC_HIGHBANK_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	tristate "Highbank L2 Cache"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	depends on ARCH_HIGHBANK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	  Calxeda Highbank memory controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) config EDAC_OCTEON_PC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	tristate "Cavium Octeon Primary Caches"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	depends on CPU_CAVIUM_OCTEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	  Support for error detection and correction on the primary caches of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	  the cnMIPS cores of Cavium Octeon family SOCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) config EDAC_OCTEON_L2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	tristate "Cavium Octeon Secondary Caches (L2C)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	depends on CAVIUM_OCTEON_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	  Cavium Octeon family of SOCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) config EDAC_OCTEON_LMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	tristate "Cavium Octeon DRAM Memory Controller (LMC)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	depends on CAVIUM_OCTEON_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	  Cavium Octeon family of SOCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) config EDAC_OCTEON_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	tristate "Cavium Octeon PCI Controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	depends on PCI && CAVIUM_OCTEON_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	  Cavium Octeon family of SOCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) config EDAC_THUNDERX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	tristate "Cavium ThunderX EDAC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	depends on ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	depends on PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	  Cavium ThunderX memory controllers (LMC), Cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	  Coherent Processor Interconnect (CCPI) and L2 cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	  blocks (TAD, CBC, MCI).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) config EDAC_ALTERA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	bool "Altera SOCFPGA ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	  Altera SOCs. This is the global enable for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	  various Altera peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) config EDAC_ALTERA_SDRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	bool "Altera SDRAM ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	depends on EDAC_ALTERA=y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	  Altera SDRAM Memory for Altera SoCs. Note that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	  preloader must initialize the SDRAM before loading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	  the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) config EDAC_ALTERA_L2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	bool "Altera L2 Cache ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	depends on EDAC_ALTERA=y && CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	  Altera L2 cache Memory for Altera SoCs. This option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	  requires L2 cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) config EDAC_ALTERA_OCRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	bool "Altera On-Chip RAM ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	  Altera On-Chip RAM Memory for Altera SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) config EDAC_ALTERA_ETHERNET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	bool "Altera Ethernet FIFO ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	depends on EDAC_ALTERA=y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	  Altera Ethernet FIFO Memory for Altera SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) config EDAC_ALTERA_NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	bool "Altera NAND FIFO ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	depends on EDAC_ALTERA=y && MTD_NAND_DENALI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	  Altera NAND FIFO Memory for Altera SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) config EDAC_ALTERA_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	bool "Altera DMA FIFO ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	depends on EDAC_ALTERA=y && PL330_DMA=y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	  Altera DMA FIFO Memory for Altera SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) config EDAC_ALTERA_USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	bool "Altera USB FIFO ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	depends on EDAC_ALTERA=y && USB_DWC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	  Altera USB FIFO Memory for Altera SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) config EDAC_ALTERA_QSPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	bool "Altera QSPI FIFO ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	  Altera QSPI FIFO Memory for Altera SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) config EDAC_ALTERA_SDMMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	bool "Altera SDMMC FIFO ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	depends on EDAC_ALTERA=y && MMC_DW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	  Altera SDMMC FIFO Memory for Altera SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) config EDAC_SIFIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	bool "Sifive platform EDAC driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	depends on EDAC=y && SIFIVE_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	  Support for error detection and correction on the SiFive SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) config EDAC_ARMADA_XP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	bool "Marvell Armada XP DDR and L2 Cache ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	depends on MACH_MVEBU_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	  Support for error correction and detection on the Marvell Aramada XP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	  DDR RAM and L2 cache controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) config EDAC_SYNOPSYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	tristate "Synopsys DDR Memory Controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	depends on ARCH_ZYNQ || ARCH_ZYNQMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	  Support for error detection and correction on the Synopsys DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	  memory controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) config EDAC_XGENE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	tristate "APM X-Gene SoC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	depends on (ARM64 || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	  APM X-Gene family of SOCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) config EDAC_TI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	tristate "Texas Instruments DDR3 ECC Controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	depends on ARCH_KEYSTONE || SOC_DRA7XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	  Support for error detection and correction on the TI SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) config EDAC_QCOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	tristate "QCOM EDAC Controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	depends on ARCH_QCOM && QCOM_LLCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	  Qualcomm Technologies, Inc. SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	  This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	  As of now, it supports error reporting for Last Level Cache Controller (LLCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	  of Tag RAM and Data RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	  For debugging issues having to do with stability and overall system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	  health, you should probably say 'Y' here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) config EDAC_ASPEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	tristate "Aspeed AST 2500 SoC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	depends on MACH_ASPEED_G5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	  Support for error detection and correction on the Aspeed AST 2500 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	  First, ECC must be configured in the bootloader. Then, this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	  will expose error counters via the EDAC kernel framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) config EDAC_BLUEFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	tristate "Mellanox BlueField Memory ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	  Mellanox BlueField SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) config EDAC_DMC520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	tristate "ARM DMC-520 ECC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	depends on ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	  Support for error detection and correction on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	  SoCs with ARM DMC-520 DRAM controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) endif # EDAC