^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xilinx ZynqMP DPDMA Engine driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 - 2020 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Hyun Woo Kwon <hyun.kwon@xilinx.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "../dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "../virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* DPDMA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XILINX_DPDMA_ERR_CTRL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define XILINX_DPDMA_ISR 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define XILINX_DPDMA_IMR 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define XILINX_DPDMA_IEN 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XILINX_DPDMA_IDS 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define XILINX_DPDMA_INTR_DESC_DONE(n) BIT((n) + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define XILINX_DPDMA_INTR_DESC_DONE_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XILINX_DPDMA_INTR_NO_OSTAND(n) BIT((n) + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XILINX_DPDMA_INTR_NO_OSTAND_MASK GENMASK(11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define XILINX_DPDMA_INTR_AXI_ERR(n) BIT((n) + 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define XILINX_DPDMA_INTR_AXI_ERR_MASK GENMASK(17, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define XILINX_DPDMA_INTR_DESC_ERR(n) BIT((n) + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define XILINX_DPDMA_INTR_DESC_ERR_MASK GENMASK(23, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define XILINX_DPDMA_INTR_WR_CMD_FIFO_FULL BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XILINX_DPDMA_INTR_WR_DATA_FIFO_FULL BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define XILINX_DPDMA_INTR_AXI_4K_CROSS BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define XILINX_DPDMA_INTR_VSYNC BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XILINX_DPDMA_INTR_CHAN_ERR_MASK 0x00041000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define XILINX_DPDMA_INTR_CHAN_ERR 0x00fff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define XILINX_DPDMA_INTR_GLOBAL_ERR 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define XILINX_DPDMA_INTR_ERR_ALL 0x07fff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define XILINX_DPDMA_INTR_CHAN_MASK 0x00041041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define XILINX_DPDMA_INTR_GLOBAL_MASK 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define XILINX_DPDMA_INTR_ALL 0x0fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define XILINX_DPDMA_EISR 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define XILINX_DPDMA_EIMR 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define XILINX_DPDMA_EIEN 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define XILINX_DPDMA_EIDS 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define XILINX_DPDMA_EINTR_INV_APB BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define XILINX_DPDMA_EINTR_RD_AXI_ERR(n) BIT((n) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define XILINX_DPDMA_EINTR_RD_AXI_ERR_MASK GENMASK(6, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define XILINX_DPDMA_EINTR_PRE_ERR(n) BIT((n) + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define XILINX_DPDMA_EINTR_PRE_ERR_MASK GENMASK(12, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define XILINX_DPDMA_EINTR_CRC_ERR(n) BIT((n) + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define XILINX_DPDMA_EINTR_CRC_ERR_MASK GENMASK(18, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define XILINX_DPDMA_EINTR_WR_AXI_ERR(n) BIT((n) + 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define XILINX_DPDMA_EINTR_WR_AXI_ERR_MASK GENMASK(24, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define XILINX_DPDMA_EINTR_DESC_DONE_ERR(n) BIT((n) + 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define XILINX_DPDMA_EINTR_DESC_DONE_ERR_MASK GENMASK(30, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define XILINX_DPDMA_EINTR_RD_CMD_FIFO_FULL BIT(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define XILINX_DPDMA_EINTR_CHAN_ERR_MASK 0x02082082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define XILINX_DPDMA_EINTR_CHAN_ERR 0x7ffffffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define XILINX_DPDMA_EINTR_GLOBAL_ERR 0x80000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define XILINX_DPDMA_EINTR_ALL 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define XILINX_DPDMA_CNTL 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define XILINX_DPDMA_GBL 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define XILINX_DPDMA_GBL_TRIG_MASK(n) ((n) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define XILINX_DPDMA_GBL_RETRIG_MASK(n) ((n) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define XILINX_DPDMA_ALC0_CNTL 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define XILINX_DPDMA_ALC0_STATUS 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define XILINX_DPDMA_ALC0_MAX 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define XILINX_DPDMA_ALC0_MIN 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define XILINX_DPDMA_ALC0_ACC 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define XILINX_DPDMA_ALC0_ACC_TRAN 0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define XILINX_DPDMA_ALC1_CNTL 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define XILINX_DPDMA_ALC1_STATUS 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define XILINX_DPDMA_ALC1_MAX 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define XILINX_DPDMA_ALC1_MIN 0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define XILINX_DPDMA_ALC1_ACC 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define XILINX_DPDMA_ALC1_ACC_TRAN 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Channel register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define XILINX_DPDMA_CH_BASE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define XILINX_DPDMA_CH_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define XILINX_DPDMA_CH_DESC_START_ADDRE 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define XILINX_DPDMA_CH_DESC_START_ADDRE_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define XILINX_DPDMA_CH_DESC_START_ADDR 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define XILINX_DPDMA_CH_DESC_NEXT_ADDRE 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define XILINX_DPDMA_CH_DESC_NEXT_ADDR 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define XILINX_DPDMA_CH_PYLD_CUR_ADDRE 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define XILINX_DPDMA_CH_PYLD_CUR_ADDR 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define XILINX_DPDMA_CH_CNTL 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define XILINX_DPDMA_CH_CNTL_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define XILINX_DPDMA_CH_CNTL_PAUSE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK GENMASK(5, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK GENMASK(9, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK GENMASK(13, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define XILINX_DPDMA_CH_STATUS 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK GENMASK(24, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define XILINX_DPDMA_CH_VDO 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define XILINX_DPDMA_CH_PYLD_SZ 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define XILINX_DPDMA_CH_DESC_ID 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define XILINX_DPDMA_CH_DESC_ID_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* DPDMA descriptor fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define XILINX_DPDMA_DESC_CONTROL_PREEMBLE 0xa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define XILINX_DPDMA_DESC_CONTROL_DESC_UPDATE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define XILINX_DPDMA_DESC_CONTROL_FRAG_MODE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define XILINX_DPDMA_DESC_CONTROL_LAST BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define XILINX_DPDMA_DESC_CONTROL_ENABLE_CRC BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define XILINX_DPDMA_DESC_ID_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK GENMASK(17, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK GENMASK(31, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define XILINX_DPDMA_ALIGN_BYTES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define XILINX_DPDMA_LINESIZE_ALIGN_BITS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define XILINX_DPDMA_NUM_CHAN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct xilinx_dpdma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @control: control configuration field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @desc_id: descriptor ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @xfer_size: transfer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @hsize_stride: horizontal size and stride
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @timestamp_lsb: LSB of time stamp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @timestamp_msb: MSB of time stamp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @addr_ext: upper 16 bit of 48 bit address (next_desc and src_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @next_desc: next descriptor 32 bit address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @src_addr: payload source address (1st page, 32 LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @addr_ext_23: payload source address (3nd and 3rd pages, 16 LSBs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @addr_ext_45: payload source address (4th and 5th pages, 16 LSBs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @src_addr2: payload source address (2nd page, 32 LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @src_addr3: payload source address (3rd page, 32 LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @src_addr4: payload source address (4th page, 32 LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @src_addr5: payload source address (5th page, 32 LSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @crc: descriptor CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct xilinx_dpdma_hw_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 desc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 hsize_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 timestamp_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 timestamp_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 addr_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 addr_ext_23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 addr_ext_45;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 src_addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 src_addr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 src_addr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 src_addr5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } __aligned(XILINX_DPDMA_ALIGN_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * struct xilinx_dpdma_sw_desc - DPDMA software descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @hw: DPDMA hardware descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @node: list node for software descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @dma_addr: DMA address of the software descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct xilinx_dpdma_sw_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct xilinx_dpdma_hw_desc hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * struct xilinx_dpdma_tx_desc - DPDMA transaction descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @vdesc: virtual DMA descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @chan: DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @descriptors: list of software descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @error: an error has been detected with this descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct xilinx_dpdma_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct virt_dma_desc vdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct xilinx_dpdma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct list_head descriptors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) bool error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define to_dpdma_tx_desc(_desc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) container_of(_desc, struct xilinx_dpdma_tx_desc, vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * struct xilinx_dpdma_chan - DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @vchan: virtual DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @reg: register base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @id: channel ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @wait_to_stop: queue to wait for outstanding transacitons before stopping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @running: true if the channel is running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @first_frame: flag for the first frame of stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @video_group: flag if multi-channel operation is needed for video channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @lock: lock to access struct xilinx_dpdma_chan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @desc_pool: descriptor allocation pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @err_task: error IRQ bottom half handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @desc: References to descriptors being processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @desc.pending: Descriptor schedule to the hardware, pending execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @desc.active: Descriptor being executed by the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @xdev: DPDMA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct xilinx_dpdma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct virt_dma_chan vchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) wait_queue_head_t wait_to_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) bool running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) bool first_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) bool video_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) spinlock_t lock; /* lock to access struct xilinx_dpdma_chan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct dma_pool *desc_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct tasklet_struct err_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct xilinx_dpdma_tx_desc *pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct xilinx_dpdma_tx_desc *active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct xilinx_dpdma_device *xdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define to_xilinx_chan(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) container_of(_chan, struct xilinx_dpdma_chan, vchan.chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * struct xilinx_dpdma_device - DPDMA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * @common: generic dma device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * @reg: register base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @dev: generic device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @irq: the interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @axi_clk: axi clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @chan: DPDMA channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @ext_addr: flag for 64 bit system (48 bit addressing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct xilinx_dpdma_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct dma_device common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct clk *axi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct xilinx_dpdma_chan *chan[XILINX_DPDMA_NUM_CHAN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) bool ext_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * DebugFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR "65535"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) enum xilinx_dpdma_testcases {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DPDMA_TC_INTR_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DPDMA_TC_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct xilinx_dpdma_debugfs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) enum xilinx_dpdma_testcases testcase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u16 xilinx_dpdma_irq_done_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct xilinx_dpdma_debugfs dpdma_debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct xilinx_dpdma_debugfs_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) enum xilinx_dpdma_testcases tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ssize_t (*read)(char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int (*write)(char *args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (chan->id == dpdma_debugfs.chan_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dpdma_debugfs.xilinx_dpdma_irq_done_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static ssize_t xilinx_dpdma_debugfs_desc_done_irq_read(char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) size_t out_str_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dpdma_debugfs.testcase = DPDMA_TC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) out_str_len = strlen(XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) out_str_len = min_t(size_t, XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) out_str_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) snprintf(buf, out_str_len, "%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dpdma_debugfs.xilinx_dpdma_irq_done_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int xilinx_dpdma_debugfs_desc_done_irq_write(char *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) char *arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) arg = strsep(&args, " ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!arg || strncasecmp(arg, "start", 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) arg = strsep(&args, " ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (!arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = kstrtou32(arg, 0, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (id < ZYNQMP_DPDMA_VIDEO0 || id > ZYNQMP_DPDMA_AUDIO1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dpdma_debugfs.testcase = DPDMA_TC_INTR_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dpdma_debugfs.xilinx_dpdma_irq_done_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dpdma_debugfs.chan_id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct xilinx_dpdma_debugfs_request dpdma_debugfs_reqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .name = "DESCRIPTOR_DONE_INTR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .tc = DPDMA_TC_INTR_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .read = xilinx_dpdma_debugfs_desc_done_irq_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .write = xilinx_dpdma_debugfs_desc_done_irq_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static ssize_t xilinx_dpdma_debugfs_read(struct file *f, char __user *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) size_t size, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) enum xilinx_dpdma_testcases testcase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) char *kern_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (*pos != 0 || size <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) kern_buff = kzalloc(XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (!kern_buff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dpdma_debugfs.testcase = DPDMA_TC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) testcase = READ_ONCE(dpdma_debugfs.testcase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (testcase != DPDMA_TC_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = dpdma_debugfs_reqs[testcase].read(kern_buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) strlcpy(kern_buff, "No testcase executed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) size = min(size, strlen(kern_buff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (copy_to_user(buf, kern_buff, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) kfree(kern_buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) *pos = size + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static ssize_t xilinx_dpdma_debugfs_write(struct file *f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) const char __user *buf, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) char *kern_buff, *kern_buff_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) char *testcase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (*pos != 0 || size <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Supporting single instance of test as of now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (dpdma_debugfs.testcase != DPDMA_TC_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) kern_buff = kzalloc(size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!kern_buff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) kern_buff_start = kern_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = strncpy_from_user(kern_buff, buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Read the testcase name from a user request. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) testcase = strsep(&kern_buff, " ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) for (i = 0; i < ARRAY_SIZE(dpdma_debugfs_reqs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!strcasecmp(testcase, dpdma_debugfs_reqs[i].name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (i == ARRAY_SIZE(dpdma_debugfs_reqs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = dpdma_debugfs_reqs[i].write(kern_buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) kfree(kern_buff_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const struct file_operations fops_xilinx_dpdma_dbgfs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .read = xilinx_dpdma_debugfs_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .write = xilinx_dpdma_debugfs_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void xilinx_dpdma_debugfs_init(struct xilinx_dpdma_device *xdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct dentry *dent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dpdma_debugfs.testcase = DPDMA_TC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dent = debugfs_create_file("testcase", 0444, xdev->common.dbg_dev_root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) NULL, &fops_xilinx_dpdma_dbgfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (IS_ERR(dent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_err(xdev->dev, "Failed to create debugfs testcase file\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static void xilinx_dpdma_debugfs_init(struct xilinx_dpdma_device *xdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #endif /* CONFIG_DEBUG_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * I/O Accessors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static inline u32 dpdma_read(void __iomem *base, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return ioread32(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static inline void dpdma_write(void __iomem *base, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) iowrite32(val, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static inline void dpdma_clr(void __iomem *base, u32 offset, u32 clr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dpdma_write(base, offset, dpdma_read(base, offset) & ~clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static inline void dpdma_set(void __iomem *base, u32 offset, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dpdma_write(base, offset, dpdma_read(base, offset) | set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * Descriptor Operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * xilinx_dpdma_sw_desc_set_dma_addrs - Set DMA addresses in the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * @xdev: DPDMA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * @sw_desc: The software descriptor in which to set DMA addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * @prev: The previous descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * @dma_addr: array of dma addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * @num_src_addr: number of addresses in @dma_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Set all the DMA addresses in the hardware descriptor corresponding to @dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * from @dma_addr. If a previous descriptor is specified in @prev, its next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * descriptor DMA address is set to the DMA address of @sw_desc. @prev may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * identical to @sw_desc for cyclic transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void xilinx_dpdma_sw_desc_set_dma_addrs(struct xilinx_dpdma_device *xdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct xilinx_dpdma_sw_desc *sw_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct xilinx_dpdma_sw_desc *prev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dma_addr_t dma_addr[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned int num_src_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) hw_desc->src_addr = lower_32_bits(dma_addr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (xdev->ext_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) hw_desc->addr_ext |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) upper_32_bits(dma_addr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) for (i = 1; i < num_src_addr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 *addr = &hw_desc->src_addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) addr[i-1] = lower_32_bits(dma_addr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (xdev->ext_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 *addr_ext = &hw_desc->addr_ext_23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 addr_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) addr_msb = upper_32_bits(dma_addr[i]) & GENMASK(15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) addr_msb <<= 16 * ((i - 1) % 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) addr_ext[(i - 1) / 2] |= addr_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!prev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) prev->hw.next_desc = lower_32_bits(sw_desc->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (xdev->ext_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) prev->hw.addr_ext |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) upper_32_bits(sw_desc->dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * xilinx_dpdma_chan_alloc_sw_desc - Allocate a software descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * Allocate a software descriptor from the channel's descriptor pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * Return: a software descriptor or NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static struct xilinx_dpdma_sw_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) xilinx_dpdma_chan_alloc_sw_desc(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct xilinx_dpdma_sw_desc *sw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) sw_desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (!sw_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) sw_desc->dma_addr = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return sw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * xilinx_dpdma_chan_free_sw_desc - Free a software descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * @sw_desc: software descriptor to free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Free a software descriptor from the channel's descriptor pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) xilinx_dpdma_chan_free_sw_desc(struct xilinx_dpdma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct xilinx_dpdma_sw_desc *sw_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dma_pool_free(chan->desc_pool, sw_desc, sw_desc->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * xilinx_dpdma_chan_dump_tx_desc - Dump a tx descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * @tx_desc: tx descriptor to dump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * Dump contents of a tx descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static void xilinx_dpdma_chan_dump_tx_desc(struct xilinx_dpdma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct xilinx_dpdma_tx_desc *tx_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct xilinx_dpdma_sw_desc *sw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct device *dev = chan->xdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_dbg(dev, "------- TX descriptor dump start -------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_dbg(dev, "------- channel ID = %d -------\n", chan->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) list_for_each_entry(sw_desc, &tx_desc->descriptors, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dev_dbg(dev, "------- HW descriptor %d -------\n", i++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dev_dbg(dev, "descriptor DMA addr: %pad\n", &sw_desc->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dev_dbg(dev, "control: 0x%08x\n", hw_desc->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_dbg(dev, "desc_id: 0x%08x\n", hw_desc->desc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_dbg(dev, "xfer_size: 0x%08x\n", hw_desc->xfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_dbg(dev, "hsize_stride: 0x%08x\n", hw_desc->hsize_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_dbg(dev, "timestamp_lsb: 0x%08x\n", hw_desc->timestamp_lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_dbg(dev, "timestamp_msb: 0x%08x\n", hw_desc->timestamp_msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dev_dbg(dev, "addr_ext: 0x%08x\n", hw_desc->addr_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev_dbg(dev, "next_desc: 0x%08x\n", hw_desc->next_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_dbg(dev, "src_addr: 0x%08x\n", hw_desc->src_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev_dbg(dev, "addr_ext_23: 0x%08x\n", hw_desc->addr_ext_23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev_dbg(dev, "addr_ext_45: 0x%08x\n", hw_desc->addr_ext_45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_dbg(dev, "src_addr2: 0x%08x\n", hw_desc->src_addr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dev_dbg(dev, "src_addr3: 0x%08x\n", hw_desc->src_addr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_dbg(dev, "src_addr4: 0x%08x\n", hw_desc->src_addr4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev_dbg(dev, "src_addr5: 0x%08x\n", hw_desc->src_addr5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_dbg(dev, "crc: 0x%08x\n", hw_desc->crc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_dbg(dev, "------- TX descriptor dump end -------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * xilinx_dpdma_chan_alloc_tx_desc - Allocate a transaction descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * Allocate a tx descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * Return: a tx descriptor or NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static struct xilinx_dpdma_tx_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) xilinx_dpdma_chan_alloc_tx_desc(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct xilinx_dpdma_tx_desc *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) tx_desc = kzalloc(sizeof(*tx_desc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (!tx_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) INIT_LIST_HEAD(&tx_desc->descriptors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) tx_desc->chan = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) tx_desc->error = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * xilinx_dpdma_chan_free_tx_desc - Free a virtual DMA descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * @vdesc: virtual DMA descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * Free the virtual DMA descriptor @vdesc including its software descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static void xilinx_dpdma_chan_free_tx_desc(struct virt_dma_desc *vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct xilinx_dpdma_sw_desc *sw_desc, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct xilinx_dpdma_tx_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (!vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) desc = to_dpdma_tx_desc(vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) list_for_each_entry_safe(sw_desc, next, &desc->descriptors, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) list_del(&sw_desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) xilinx_dpdma_chan_free_sw_desc(desc->chan, sw_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * xilinx_dpdma_chan_prep_interleaved_dma - Prepare an interleaved dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * @xt: dma interleaved template
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * Prepare a tx descriptor including internal software/hardware descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * based on @xt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * Return: A DPDMA TX descriptor on success, or NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static struct xilinx_dpdma_tx_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) xilinx_dpdma_chan_prep_interleaved_dma(struct xilinx_dpdma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct dma_interleaved_template *xt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct xilinx_dpdma_tx_desc *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct xilinx_dpdma_sw_desc *sw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct xilinx_dpdma_hw_desc *hw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) size_t hsize = xt->sgl[0].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) size_t stride = hsize + xt->sgl[0].icg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (!IS_ALIGNED(xt->src_start, XILINX_DPDMA_ALIGN_BYTES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dev_err(chan->xdev->dev, "buffer should be aligned at %d B\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) XILINX_DPDMA_ALIGN_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) tx_desc = xilinx_dpdma_chan_alloc_tx_desc(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (!tx_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (!sw_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) xilinx_dpdma_chan_free_tx_desc(&tx_desc->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, sw_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) &xt->src_start, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) hw_desc = &sw_desc->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) hsize = ALIGN(hsize, XILINX_DPDMA_LINESIZE_ALIGN_BITS / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) hw_desc->xfer_size = hsize * xt->numf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) hw_desc->hsize_stride =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK, hsize) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) stride / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_PREEMBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) list_add_tail(&sw_desc->node, &tx_desc->descriptors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * DPDMA Channel Operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * xilinx_dpdma_chan_enable - Enable the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * Enable the channel and its interrupts. Set the QoS values for video class.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void xilinx_dpdma_chan_enable(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) reg = (XILINX_DPDMA_INTR_CHAN_MASK << chan->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) | XILINX_DPDMA_INTR_GLOBAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) reg = (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) | XILINX_DPDMA_INTR_GLOBAL_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) reg = XILINX_DPDMA_CH_CNTL_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * xilinx_dpdma_chan_disable - Disable the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * Disable the channel and its interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static void xilinx_dpdma_chan_disable(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) reg = XILINX_DPDMA_INTR_CHAN_MASK << chan->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) reg = XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * xilinx_dpdma_chan_pause - Pause the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * Pause the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static void xilinx_dpdma_chan_pause(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * xilinx_dpdma_chan_unpause - Unpause the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * Unpause the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static void xilinx_dpdma_chan_unpause(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static u32 xilinx_dpdma_chan_video_group_ready(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct xilinx_dpdma_device *xdev = chan->xdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u32 channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (xdev->chan[i]->video_group && !xdev->chan[i]->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (xdev->chan[i]->video_group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) channels |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * xilinx_dpdma_chan_queue_transfer - Queue the next transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * Queue the next descriptor, if any, to the hardware. If the channel is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * stopped, start it first. Otherwise retrigger it with the next descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct xilinx_dpdma_device *xdev = chan->xdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct xilinx_dpdma_sw_desc *sw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct xilinx_dpdma_tx_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct virt_dma_desc *vdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u32 reg, channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) bool first_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) lockdep_assert_held(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (chan->desc.pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (!chan->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) xilinx_dpdma_chan_unpause(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) xilinx_dpdma_chan_enable(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) chan->first_frame = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) chan->running = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) vdesc = vchan_next_desc(&chan->vchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (!vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) desc = to_dpdma_tx_desc(vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) chan->desc.pending = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) list_del(&desc->vdesc.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * Assign the cookie to descriptors in this transaction. Only 16 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * will be used, but it should be enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) list_for_each_entry(sw_desc, &desc->descriptors, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) sw_desc->hw.desc_id = desc->vdesc.tx.cookie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) & XILINX_DPDMA_CH_DESC_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) sw_desc = list_first_entry(&desc->descriptors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct xilinx_dpdma_sw_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) lower_32_bits(sw_desc->dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (xdev->ext_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) FIELD_PREP(XILINX_DPDMA_CH_DESC_START_ADDRE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) upper_32_bits(sw_desc->dma_addr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) first_frame = chan->first_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) chan->first_frame = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (chan->video_group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) channels = xilinx_dpdma_chan_video_group_ready(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * Trigger the transfer only when all channels in the group are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (!channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) channels = BIT(chan->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (first_frame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) reg = XILINX_DPDMA_GBL_TRIG_MASK(channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) reg = XILINX_DPDMA_GBL_RETRIG_MASK(channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dpdma_write(xdev->reg, XILINX_DPDMA_GBL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * xilinx_dpdma_chan_ostand - Number of outstanding transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * Read and return the number of outstanding transactions from register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * Return: Number of outstanding transactions from the status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static u32 xilinx_dpdma_chan_ostand(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return FIELD_GET(XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dpdma_read(chan->reg, XILINX_DPDMA_CH_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * xilinx_dpdma_chan_no_ostand - Notify no outstanding transaction event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * Notify waiters for no outstanding event, so waiters can stop the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * safely. This function is supposed to be called when 'no outstanding'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * interrupt is generated. The 'no outstanding' interrupt is disabled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * should be re-enabled when this event is handled. If the channel status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * register still shows some number of outstanding transactions, the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * remains enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * Return: 0 on success. On failure, -EWOULDBLOCK if there's still outstanding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * transaction(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int xilinx_dpdma_chan_notify_no_ostand(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) cnt = xilinx_dpdma_chan_ostand(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) dev_dbg(chan->xdev->dev, "%d outstanding transactions\n", cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return -EWOULDBLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* Disable 'no outstanding' interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) dpdma_write(chan->xdev->reg, XILINX_DPDMA_IDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) wake_up(&chan->wait_to_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * xilinx_dpdma_chan_wait_no_ostand - Wait for the no outstanding irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * Wait for the no outstanding transaction interrupt. This functions can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * for 50ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * Return: 0 on success. On failure, -ETIMEOUT for time out, or the error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * from wait_event_interruptible_timeout().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static int xilinx_dpdma_chan_wait_no_ostand(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* Wait for a no outstanding transaction interrupt upto 50msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ret = wait_event_interruptible_timeout(chan->wait_to_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) !xilinx_dpdma_chan_ostand(chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) msecs_to_jiffies(50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (ret > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dev_err(chan->xdev->dev, "not ready to stop: %d trans\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) xilinx_dpdma_chan_ostand(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * xilinx_dpdma_chan_poll_no_ostand - Poll the outstanding transaction status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * Poll the outstanding transaction status, and return when there's no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * outstanding transaction. This functions can be used in the interrupt context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * or where the atomicity is required. Calling thread may wait more than 50ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * Return: 0 on success, or -ETIMEDOUT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static int xilinx_dpdma_chan_poll_no_ostand(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) u32 cnt, loop = 50000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Poll at least for 50ms (20 fps). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) cnt = xilinx_dpdma_chan_ostand(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) } while (loop-- > 0 && cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (loop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dev_err(chan->xdev->dev, "not ready to stop: %d trans\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) xilinx_dpdma_chan_ostand(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * xilinx_dpdma_chan_stop - Stop the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * Stop a previously paused channel by first waiting for completion of all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * outstanding transaction and then disabling the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static int xilinx_dpdma_chan_stop(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = xilinx_dpdma_chan_wait_no_ostand(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) xilinx_dpdma_chan_disable(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) chan->running = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * xilinx_dpdma_chan_done_irq - Handle hardware descriptor completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * Handle completion of the currently active descriptor (@chan->desc.active). As
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * we currently support cyclic transfers only, this just invokes the cyclic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * callback. The descriptor will be completed at the VSYNC interrupt when a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * descriptor replaces it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static void xilinx_dpdma_chan_done_irq(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct xilinx_dpdma_tx_desc *active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) xilinx_dpdma_debugfs_desc_done_irq(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) active = chan->desc.active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) vchan_cyclic_callback(&active->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dev_warn(chan->xdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) "DONE IRQ with no active descriptor!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * xilinx_dpdma_chan_vsync_irq - Handle hardware descriptor scheduling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * At VSYNC the active descriptor may have been replaced by the pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * descriptor. Detect this through the DESC_ID and perform appropriate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * bookkeeping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct xilinx_dpdma_tx_desc *pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct xilinx_dpdma_sw_desc *sw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) u32 desc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) pending = chan->desc.pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (!chan->running || !pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) & XILINX_DPDMA_CH_DESC_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* If the retrigger raced with vsync, retry at the next frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) sw_desc = list_first_entry(&pending->descriptors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) struct xilinx_dpdma_sw_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (sw_desc->hw.desc_id != desc_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * Complete the active descriptor, if any, promote the pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * descriptor to active, and queue the next transfer, if any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (chan->desc.active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) vchan_cookie_complete(&chan->desc.active->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) chan->desc.active = pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) chan->desc.pending = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) xilinx_dpdma_chan_queue_transfer(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * xilinx_dpdma_chan_err - Detect any channel error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * @isr: masked Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * @eisr: Error Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * Return: true if any channel error occurs, or false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) xilinx_dpdma_chan_err(struct xilinx_dpdma_chan *chan, u32 isr, u32 eisr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (chan->running &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ((isr & (XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) (eisr & (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * xilinx_dpdma_chan_handle_err - DPDMA channel error handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * @chan: DPDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * This function is called when any channel error or any global error occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * The function disables the paused channel by errors and determines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * if the current active descriptor can be rescheduled depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * the descriptor status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct xilinx_dpdma_device *xdev = chan->xdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct xilinx_dpdma_tx_desc *active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dev_dbg(xdev->dev, "cur desc addr = 0x%04x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) dev_dbg(xdev->dev, "cur payload addr = 0x%04x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) xilinx_dpdma_chan_disable(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) chan->running = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (!chan->desc.active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) active = chan->desc.active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) chan->desc.active = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) xilinx_dpdma_chan_dump_tx_desc(chan, active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (active->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) dev_dbg(xdev->dev, "repeated error on desc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /* Reschedule if there's no new descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (!chan->desc.pending &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) list_empty(&chan->vchan.desc_issued)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) active->error = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) list_add_tail(&active->vdesc.node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) &chan->vchan.desc_issued);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) xilinx_dpdma_chan_free_tx_desc(&active->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * DMA Engine Operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) xilinx_dpdma_prep_interleaved_dma(struct dma_chan *dchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct dma_interleaved_template *xt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct xilinx_dpdma_tx_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (xt->dir != DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (!xt->numf || !xt->sgl[0].size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (!(flags & DMA_PREP_REPEAT) || !(flags & DMA_PREP_LOAD_EOT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) desc = xilinx_dpdma_chan_prep_interleaved_dma(chan, xt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) vchan_tx_prep(&chan->vchan, &desc->vdesc, flags | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return &desc->vdesc.tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * xilinx_dpdma_alloc_chan_resources - Allocate resources for the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * @dchan: DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * Allocate a descriptor pool for the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * Return: 0 on success, or -ENOMEM if failed to allocate a pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static int xilinx_dpdma_alloc_chan_resources(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) size_t align = __alignof__(struct xilinx_dpdma_sw_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) chan->desc_pool = dma_pool_create(dev_name(chan->xdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) chan->xdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) sizeof(struct xilinx_dpdma_sw_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) align, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (!chan->desc_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dev_err(chan->xdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) "failed to allocate a descriptor pool\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * xilinx_dpdma_free_chan_resources - Free all resources for the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * @dchan: DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * Free resources associated with the virtual DMA channel, and destroy the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * descriptor pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static void xilinx_dpdma_free_chan_resources(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) vchan_free_chan_resources(&chan->vchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) dma_pool_destroy(chan->desc_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) chan->desc_pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static void xilinx_dpdma_issue_pending(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (vchan_issue_pending(&chan->vchan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) xilinx_dpdma_chan_queue_transfer(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static int xilinx_dpdma_config(struct dma_chan *dchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct dma_slave_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * The destination address doesn't need to be specified as the DPDMA is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * hardwired to the destination (the DP controller). The transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * width, burst size and port window size are thus meaningless, they're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * fixed both on the DPDMA side and on the DP controller side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * Abuse the slave_id to indicate that the channel is part of a video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (chan->id <= ZYNQMP_DPDMA_VIDEO2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) chan->video_group = config->slave_id != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static int xilinx_dpdma_pause(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) xilinx_dpdma_chan_pause(to_xilinx_chan(dchan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static int xilinx_dpdma_resume(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) xilinx_dpdma_chan_unpause(to_xilinx_chan(dchan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * xilinx_dpdma_terminate_all - Terminate the channel and descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * @dchan: DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * Pause the channel without waiting for ongoing transfers to complete. Waiting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * for completion is performed by xilinx_dpdma_synchronize() that will disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * the channel to complete the stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * All the descriptors associated with the channel that are guaranteed not to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * be touched by the hardware. The pending and active descriptor are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * touched, and will be freed either upon completion, or by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * xilinx_dpdma_synchronize().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static int xilinx_dpdma_terminate_all(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) struct xilinx_dpdma_device *xdev = chan->xdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) LIST_HEAD(descriptors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* Pause the channel (including the whole video group if applicable). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (chan->video_group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (xdev->chan[i]->video_group &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) xdev->chan[i]->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) xilinx_dpdma_chan_pause(xdev->chan[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) xdev->chan[i]->video_group = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) xilinx_dpdma_chan_pause(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* Gather all the descriptors we can free and free them. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) vchan_get_all_descriptors(&chan->vchan, &descriptors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) vchan_dma_desc_free_list(&chan->vchan, &descriptors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * xilinx_dpdma_synchronize - Synchronize callback execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * @dchan: DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * Synchronizing callback execution ensures that all previously issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * transfers have completed and all associated callbacks have been called and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) * have returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * This function waits for the DMA channel to stop. It assumes it has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * paused by a previous call to dmaengine_terminate_async(), and that no new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * pending descriptors have been issued with dma_async_issue_pending(). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * behaviour is undefined otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static void xilinx_dpdma_synchronize(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) xilinx_dpdma_chan_stop(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (chan->desc.pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) vchan_terminate_vdesc(&chan->desc.pending->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) chan->desc.pending = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (chan->desc.active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) vchan_terminate_vdesc(&chan->desc.active->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) chan->desc.active = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) vchan_synchronize(&chan->vchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * Interrupt and Tasklet Handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * xilinx_dpdma_err - Detect any global error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * @isr: Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * @eisr: Error Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * Return: True if any global error occurs, or false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static bool xilinx_dpdma_err(u32 isr, u32 eisr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (isr & XILINX_DPDMA_INTR_GLOBAL_ERR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) eisr & XILINX_DPDMA_EINTR_GLOBAL_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * xilinx_dpdma_handle_err_irq - Handle DPDMA error interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * @xdev: DPDMA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * @isr: masked Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * @eisr: Error Interrupt Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * Handle if any error occurs based on @isr and @eisr. This function disables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * corresponding error interrupts, and those should be re-enabled once handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static void xilinx_dpdma_handle_err_irq(struct xilinx_dpdma_device *xdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) u32 isr, u32 eisr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) bool err = xilinx_dpdma_err(isr, eisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) dev_dbg_ratelimited(xdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) "error irq: isr = 0x%08x, eisr = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) isr, eisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /* Disable channel error interrupts until errors are handled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) dpdma_write(xdev->reg, XILINX_DPDMA_IDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) isr & ~XILINX_DPDMA_INTR_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) dpdma_write(xdev->reg, XILINX_DPDMA_EIDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) eisr & ~XILINX_DPDMA_EINTR_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (err || xilinx_dpdma_chan_err(xdev->chan[i], isr, eisr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) tasklet_schedule(&xdev->chan[i]->err_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * xilinx_dpdma_enable_irq - Enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) * @xdev: DPDMA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * Enable interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static void xilinx_dpdma_enable_irq(struct xilinx_dpdma_device *xdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) dpdma_write(xdev->reg, XILINX_DPDMA_IEN, XILINX_DPDMA_INTR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) dpdma_write(xdev->reg, XILINX_DPDMA_EIEN, XILINX_DPDMA_EINTR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * xilinx_dpdma_disable_irq - Disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * @xdev: DPDMA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * Disable interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static void xilinx_dpdma_disable_irq(struct xilinx_dpdma_device *xdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) dpdma_write(xdev->reg, XILINX_DPDMA_IDS, XILINX_DPDMA_INTR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, XILINX_DPDMA_EINTR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * xilinx_dpdma_chan_err_task - Per channel tasklet for error handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) * @t: pointer to the tasklet associated with this handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) * Per channel error handling tasklet. This function waits for the outstanding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) * transaction to complete and triggers error handling. After error handling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) * re-enable channel error interrupts, and restart the channel if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static void xilinx_dpdma_chan_err_task(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct xilinx_dpdma_chan *chan = from_tasklet(chan, t, err_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct xilinx_dpdma_device *xdev = chan->xdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* Proceed error handling even when polling fails. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) xilinx_dpdma_chan_poll_no_ostand(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) xilinx_dpdma_chan_handle_err(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) dpdma_write(xdev->reg, XILINX_DPDMA_IEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) dpdma_write(xdev->reg, XILINX_DPDMA_EIEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) xilinx_dpdma_chan_queue_transfer(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static irqreturn_t xilinx_dpdma_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct xilinx_dpdma_device *xdev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) u32 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) status = dpdma_read(xdev->reg, XILINX_DPDMA_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) error = dpdma_read(xdev->reg, XILINX_DPDMA_EISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (!status && !error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) dpdma_write(xdev->reg, XILINX_DPDMA_ISR, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) dpdma_write(xdev->reg, XILINX_DPDMA_EISR, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (status & XILINX_DPDMA_INTR_VSYNC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) * There's a single VSYNC interrupt that needs to be processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * by each running channel to update the active descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) struct xilinx_dpdma_chan *chan = xdev->chan[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) xilinx_dpdma_chan_vsync_irq(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) mask = FIELD_GET(XILINX_DPDMA_INTR_DESC_DONE_MASK, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) xilinx_dpdma_chan_done_irq(xdev->chan[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) mask = FIELD_GET(XILINX_DPDMA_INTR_NO_OSTAND_MASK, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) xilinx_dpdma_chan_notify_no_ostand(xdev->chan[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) mask = status & XILINX_DPDMA_INTR_ERR_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (mask || error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) xilinx_dpdma_handle_err_irq(xdev, mask, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * Initialization & Cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static int xilinx_dpdma_chan_init(struct xilinx_dpdma_device *xdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) unsigned int chan_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct xilinx_dpdma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) chan->id = chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) chan->reg = xdev->reg + XILINX_DPDMA_CH_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) + XILINX_DPDMA_CH_OFFSET * chan->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) chan->running = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) chan->xdev = xdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) spin_lock_init(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) init_waitqueue_head(&chan->wait_to_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) tasklet_setup(&chan->err_task, xilinx_dpdma_chan_err_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) chan->vchan.desc_free = xilinx_dpdma_chan_free_tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) vchan_init(&chan->vchan, &xdev->common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) xdev->chan[chan->id] = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static void xilinx_dpdma_chan_remove(struct xilinx_dpdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) tasklet_kill(&chan->err_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) list_del(&chan->vchan.chan.device_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) struct xilinx_dpdma_device *xdev = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) uint32_t chan_id = dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (chan_id >= ARRAY_SIZE(xdev->chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (!xdev->chan[chan_id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return dma_get_slave_channel(&xdev->chan[chan_id]->vchan.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static void dpdma_hw_init(struct xilinx_dpdma_device *xdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) xilinx_dpdma_disable_irq(xdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /* Stop all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) reg = xdev->reg + XILINX_DPDMA_CH_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) + XILINX_DPDMA_CH_OFFSET * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) dpdma_clr(reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* Clear the interrupt status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) dpdma_write(xdev->reg, XILINX_DPDMA_ISR, XILINX_DPDMA_INTR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) dpdma_write(xdev->reg, XILINX_DPDMA_EISR, XILINX_DPDMA_EINTR_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static int xilinx_dpdma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct xilinx_dpdma_device *xdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) struct dma_device *ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (!xdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) xdev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) xdev->ext_addr = sizeof(dma_addr_t) > 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) INIT_LIST_HEAD(&xdev->common.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) platform_set_drvdata(pdev, xdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) xdev->axi_clk = devm_clk_get(xdev->dev, "axi_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (IS_ERR(xdev->axi_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) return PTR_ERR(xdev->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) xdev->reg = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (IS_ERR(xdev->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return PTR_ERR(xdev->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) dpdma_hw_init(xdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) xdev->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (xdev->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) dev_err(xdev->dev, "failed to get platform irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) return xdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) ret = request_irq(xdev->irq, xilinx_dpdma_irq_handler, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) dev_name(xdev->dev), xdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) dev_err(xdev->dev, "failed to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) ddev = &xdev->common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) ddev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) dma_cap_set(DMA_SLAVE, ddev->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) dma_cap_set(DMA_PRIVATE, ddev->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) dma_cap_set(DMA_INTERLEAVE, ddev->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) dma_cap_set(DMA_REPEAT, ddev->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) dma_cap_set(DMA_LOAD_EOT, ddev->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) ddev->copy_align = fls(XILINX_DPDMA_ALIGN_BYTES - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) ddev->device_alloc_chan_resources = xilinx_dpdma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) ddev->device_free_chan_resources = xilinx_dpdma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) ddev->device_prep_interleaved_dma = xilinx_dpdma_prep_interleaved_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /* TODO: Can we achieve better granularity ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) ddev->device_tx_status = dma_cookie_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) ddev->device_issue_pending = xilinx_dpdma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) ddev->device_config = xilinx_dpdma_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ddev->device_pause = xilinx_dpdma_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) ddev->device_resume = xilinx_dpdma_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) ddev->device_terminate_all = xilinx_dpdma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ddev->device_synchronize = xilinx_dpdma_synchronize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) ddev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) ddev->directions = BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) for (i = 0; i < ARRAY_SIZE(xdev->chan); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) ret = xilinx_dpdma_chan_init(xdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) dev_err(xdev->dev, "failed to initialize channel %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) ret = clk_prepare_enable(xdev->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) dev_err(xdev->dev, "failed to enable the axi clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) ret = dma_async_device_register(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) dev_err(xdev->dev, "failed to register the dma device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) goto error_dma_async;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) ret = of_dma_controller_register(xdev->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) of_dma_xilinx_xlate, ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) dev_err(xdev->dev, "failed to register DMA to DT DMA helper\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) goto error_of_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) xilinx_dpdma_enable_irq(xdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) xilinx_dpdma_debugfs_init(xdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) dev_info(&pdev->dev, "Xilinx DPDMA engine is probed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) error_of_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) dma_async_device_unregister(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) error_dma_async:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) clk_disable_unprepare(xdev->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) xilinx_dpdma_chan_remove(xdev->chan[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) free_irq(xdev->irq, xdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) static int xilinx_dpdma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) struct xilinx_dpdma_device *xdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /* Start by disabling the IRQ to avoid races during cleanup. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) free_irq(xdev->irq, xdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) xilinx_dpdma_disable_irq(xdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) of_dma_controller_free(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) dma_async_device_unregister(&xdev->common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) clk_disable_unprepare(xdev->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) xilinx_dpdma_chan_remove(xdev->chan[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static const struct of_device_id xilinx_dpdma_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) { .compatible = "xlnx,zynqmp-dpdma",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) { /* end of table */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) MODULE_DEVICE_TABLE(of, xilinx_dpdma_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static struct platform_driver xilinx_dpdma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .probe = xilinx_dpdma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .remove = xilinx_dpdma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .name = "xilinx-zynqmp-dpdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .of_match_table = xilinx_dpdma_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) module_platform_driver(xilinx_dpdma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) MODULE_AUTHOR("Xilinx, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) MODULE_DESCRIPTION("Xilinx ZynqMP DPDMA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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