^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP DMAengine support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/omap-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "../virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP_SDMA_REQUESTS 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP_SDMA_CHANNELS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct omap_dma_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int lch_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int rw_priority:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int needs_busy_check:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int may_lose_context:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int needs_lch_clear:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct omap_dma_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 irqenable_l0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 irqenable_l1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 ocp_sysconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 gcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct omap_dmadev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct dma_device ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const struct omap_dma_reg *reg_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct omap_system_dma_plat_info *plat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const struct omap_dma_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct notifier_block nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct omap_dma_context context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int lch_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DECLARE_BITMAP(lch_bitmap, OMAP_SDMA_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct mutex lch_lock; /* for assigning logical channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bool legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bool ll123_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct dma_pool *desc_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned dma_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) spinlock_t irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) uint32_t irq_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct omap_chan **lch_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct omap_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct virt_dma_chan vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __iomem *channel_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const struct omap_dma_reg *reg_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) uint32_t ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned dma_sig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) bool cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) bool paused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) bool running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int dma_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct omap_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned sgidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DESC_NXT_SV_REFRESH (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DESC_NXT_SV_REUSE (0x2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DESC_NXT_DV_REFRESH (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DESC_NXT_DV_REUSE (0x2 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DESC_NTYPE_TYPE2 (0x2 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Type 2 descriptor with Source or Destination address update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct omap_type2_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) uint32_t next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) uint32_t en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) uint32_t addr; /* src or dst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) uint16_t fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) uint16_t cicr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int16_t cdei;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int16_t csei;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int32_t cdfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int32_t csfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct omap_sg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) uint32_t en; /* number of elements (24-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) uint32_t fn; /* number of frames (16-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int32_t fi; /* for double indexing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int16_t ei; /* for double indexing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Linked list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct omap_type2_desc *t2_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dma_addr_t t2_desc_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct omap_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct virt_dma_desc vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bool using_ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum dma_transfer_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dma_addr_t dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) bool polled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int32_t fi; /* for OMAP_DMA_SYNC_PACKET / double indexing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int16_t ei; /* for double indexing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) uint8_t es; /* CSDP_DATA_TYPE_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) uint32_t ccr; /* CCR value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) uint16_t clnk_ctrl; /* CLNK_CTRL value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) uint16_t cicr; /* CICR value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) uint32_t csdp; /* CSDP value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned sglen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct omap_sg sg[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CAPS_0_SUPPORT_LL123 = BIT(20), /* Linked List type1/2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) CAPS_0_SUPPORT_LL4 = BIT(21), /* Linked List type4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) CCR_FS = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CCR_READ_PRIORITY = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) CCR_ENABLE = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CCR_AUTO_INIT = BIT(8), /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CCR_REPEAT = BIT(9), /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CCR_SRC_AMODE_CONSTANT = 0 << 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CCR_SRC_AMODE_POSTINC = 1 << 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CCR_SRC_AMODE_SGLIDX = 2 << 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CCR_SRC_AMODE_DBLIDX = 3 << 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CCR_DST_AMODE_CONSTANT = 0 << 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CCR_DST_AMODE_POSTINC = 1 << 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CCR_DST_AMODE_SGLIDX = 2 << 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) CCR_DST_AMODE_DBLIDX = 3 << 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CCR_CONSTANT_FILL = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CCR_TRANSPARENT_COPY = BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CCR_BS = BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CCR_SUPERVISOR = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CCR_PREFETCH = BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CCR_TRIGGER_SRC = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) CCR_BUFFERING_DISABLE = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CCR_WRITE_PRIORITY = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CCR_SYNC_ELEMENT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CCR_SYNC_FRAME = CCR_FS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CCR_SYNC_BLOCK = CCR_BS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) CCR_SYNC_PACKET = CCR_BS | CCR_FS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) CSDP_DATA_TYPE_8 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) CSDP_DATA_TYPE_16 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) CSDP_DATA_TYPE_32 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CSDP_SRC_PORT_EMIFF = 0 << 2, /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) CSDP_SRC_PORT_EMIFS = 1 << 2, /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) CSDP_SRC_PORT_OCP_T1 = 2 << 2, /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) CSDP_SRC_PORT_TIPB = 3 << 2, /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CSDP_SRC_PORT_OCP_T2 = 4 << 2, /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) CSDP_SRC_PORT_MPUI = 5 << 2, /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CSDP_SRC_PACKED = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CSDP_SRC_BURST_1 = 0 << 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CSDP_SRC_BURST_16 = 1 << 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CSDP_SRC_BURST_32 = 2 << 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CSDP_SRC_BURST_64 = 3 << 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) CSDP_DST_PORT_EMIFF = 0 << 9, /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) CSDP_DST_PORT_EMIFS = 1 << 9, /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) CSDP_DST_PORT_OCP_T1 = 2 << 9, /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CSDP_DST_PORT_TIPB = 3 << 9, /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) CSDP_DST_PORT_OCP_T2 = 4 << 9, /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) CSDP_DST_PORT_MPUI = 5 << 9, /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) CSDP_DST_PACKED = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) CSDP_DST_BURST_1 = 0 << 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CSDP_DST_BURST_16 = 1 << 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) CSDP_DST_BURST_32 = 2 << 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) CSDP_DST_BURST_64 = 3 << 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) CSDP_WRITE_NON_POSTED = 0 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) CSDP_WRITE_POSTED = 1 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CSDP_WRITE_LAST_NON_POSTED = 2 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CICR_TOUT_IE = BIT(0), /* OMAP1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CICR_DROP_IE = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CICR_HALF_IE = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CICR_FRAME_IE = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) CICR_LAST_IE = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CICR_BLOCK_IE = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CICR_PKT_IE = BIT(7), /* OMAP2+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) CLNK_CTRL_ENABLE_LNK = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) CDP_DST_VALID_INC = 0 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) CDP_DST_VALID_RELOAD = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) CDP_DST_VALID_REUSE = 2 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) CDP_SRC_VALID_INC = 0 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) CDP_SRC_VALID_RELOAD = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) CDP_SRC_VALID_REUSE = 2 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) CDP_NTYPE_TYPE1 = 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) CDP_NTYPE_TYPE2 = 2 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) CDP_NTYPE_TYPE3 = 3 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) CDP_TMODE_NORMAL = 0 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) CDP_TMODE_LLIST = 1 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) CDP_FAST = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const unsigned es_bytes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) [CSDP_DATA_TYPE_8] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) [CSDP_DATA_TYPE_16] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) [CSDP_DATA_TYPE_32] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static bool omap_dma_filter_fn(struct dma_chan *chan, void *param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct of_dma_filter_info omap_dma_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .filter_fn = omap_dma_filter_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return container_of(d, struct omap_dmadev, ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return container_of(c, struct omap_chan, vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return container_of(t, struct omap_desc, vd.tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void omap_dma_desc_free(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct omap_desc *d = to_omap_dma_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (d->using_ll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct omap_dmadev *od = to_omap_dma_dev(vd->tx.chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) for (i = 0; i < d->sglen; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (d->sg[i].t2_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dma_pool_free(od->desc_pool, d->sg[i].t2_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) d->sg[i].t2_desc_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) kfree(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void omap_dma_fill_type2_desc(struct omap_desc *d, int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) enum dma_transfer_direction dir, bool last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct omap_sg *sg = &d->sg[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct omap_type2_desc *t2_desc = sg->t2_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) d->sg[idx - 1].t2_desc->next_desc = sg->t2_desc_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) t2_desc->next_desc = 0xfffffffc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) t2_desc->en = sg->en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) t2_desc->addr = sg->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) t2_desc->fn = sg->fn & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) t2_desc->cicr = d->cicr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) t2_desc->cicr &= ~CICR_BLOCK_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) t2_desc->cdei = sg->ei;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) t2_desc->csei = d->ei;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) t2_desc->cdfi = sg->fi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) t2_desc->csfi = d->fi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) t2_desc->en |= DESC_NXT_DV_REFRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) t2_desc->en |= DESC_NXT_SV_REUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) t2_desc->cdei = d->ei;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) t2_desc->csei = sg->ei;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) t2_desc->cdfi = d->fi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) t2_desc->csfi = sg->fi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) t2_desc->en |= DESC_NXT_SV_REFRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) t2_desc->en |= DESC_NXT_DV_REUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) t2_desc->en |= DESC_NTYPE_TYPE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case OMAP_DMA_REG_16BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) writew_relaxed(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case OMAP_DMA_REG_2X16BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writew_relaxed(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) writew_relaxed(val >> 16, addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case OMAP_DMA_REG_32BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) writel_relaxed(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static unsigned omap_dma_read(unsigned type, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case OMAP_DMA_REG_16BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) val = readw_relaxed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case OMAP_DMA_REG_2X16BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) val = readw_relaxed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) val |= readw_relaxed(addr + 2) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case OMAP_DMA_REG_32BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) val = readl_relaxed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) const struct omap_dma_reg *r = od->reg_map + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) WARN_ON(r->stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) omap_dma_write(val, r->type, od->base + r->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) const struct omap_dma_reg *r = od->reg_map + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) WARN_ON(r->stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return omap_dma_read(r->type, od->base + r->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) const struct omap_dma_reg *r = c->reg_map + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) omap_dma_write(val, r->type, c->channel_base + r->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) const struct omap_dma_reg *r = c->reg_map + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return omap_dma_read(r->type, c->channel_base + r->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void omap_dma_clear_csr(struct omap_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (dma_omap1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) omap_dma_chan_read(c, CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) omap_dma_chan_write(c, CSR, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static unsigned omap_dma_get_csr(struct omap_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned val = omap_dma_chan_read(c, CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!dma_omap1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) omap_dma_chan_write(c, CSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void omap_dma_clear_lch(struct omap_dmadev *od, int lch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct omap_chan *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) c = od->lch_map[lch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) for (i = CSDP; i <= od->cfg->lch_end; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) omap_dma_chan_write(c, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned lch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) c->channel_base = od->base + od->plat->channel_stride * lch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) od->lch_map[lch] = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) uint16_t cicr = d->cicr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (__dma_omap15xx(od->plat->dma_attr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) omap_dma_chan_write(c, CPC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) omap_dma_chan_write(c, CDAC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) omap_dma_clear_csr(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (d->using_ll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) uint32_t cdp = CDP_TMODE_LLIST | CDP_NTYPE_TYPE2 | CDP_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (d->dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cdp |= (CDP_DST_VALID_RELOAD | CDP_SRC_VALID_REUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) cdp |= (CDP_DST_VALID_REUSE | CDP_SRC_VALID_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) omap_dma_chan_write(c, CDP, cdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) omap_dma_chan_write(c, CNDP, d->sg[0].t2_desc_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) omap_dma_chan_write(c, CCDN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) omap_dma_chan_write(c, CCFN, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) omap_dma_chan_write(c, CCEN, 0xffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) cicr &= ~CICR_BLOCK_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } else if (od->ll123_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) omap_dma_chan_write(c, CDP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) omap_dma_chan_write(c, CICR, cicr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Enable channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) c->running = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static void omap_dma_drain_chan(struct omap_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Wait for sDMA FIFO to drain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) for (i = 0; ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) val = omap_dma_chan_read(c, CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (i > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_err(c->vc.chan.device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "DMA drain did not complete on lch %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) c->dma_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int omap_dma_stop(struct omap_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* disable irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) omap_dma_chan_write(c, CICR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) omap_dma_clear_csr(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) val = omap_dma_chan_read(c, CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) uint32_t sysconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) omap_dma_glbl_write(od, OCP_SYSCONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) val = omap_dma_chan_read(c, CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) val &= ~CCR_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) omap_dma_chan_write(c, CCR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!(c->ccr & CCR_BUFFERING_DISABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) omap_dma_drain_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (!(val & CCR_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) val &= ~CCR_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) omap_dma_chan_write(c, CCR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!(c->ccr & CCR_BUFFERING_DISABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) omap_dma_drain_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) val = omap_dma_chan_read(c, CLNK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (dma_omap1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) val |= 1 << 14; /* set the STOP_LNK bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) val &= ~CLNK_CTRL_ENABLE_LNK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) omap_dma_chan_write(c, CLNK_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) c->running = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct omap_sg *sg = d->sg + c->sgidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned cxsa, cxei, cxfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) cxsa = CDSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) cxei = CDEI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) cxfi = CDFI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) cxsa = CSSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) cxei = CSEI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) cxfi = CSFI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) omap_dma_chan_write(c, cxsa, sg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) omap_dma_chan_write(c, cxei, sg->ei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) omap_dma_chan_write(c, cxfi, sg->fi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) omap_dma_chan_write(c, CEN, sg->en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) omap_dma_chan_write(c, CFN, sg->fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) omap_dma_start(c, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) c->sgidx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static void omap_dma_start_desc(struct omap_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct omap_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned cxsa, cxei, cxfi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (!vd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) c->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) list_del(&vd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) c->desc = d = to_omap_dma_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) c->sgidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * This provides the necessary barrier to ensure data held in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * DMA coherent memory is visible to the DMA engine prior to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * the transfer starting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) omap_dma_chan_write(c, CCR, d->ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (dma_omap1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) omap_dma_chan_write(c, CCR2, d->ccr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) cxsa = CSSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) cxei = CSEI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) cxfi = CSFI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cxsa = CDSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) cxei = CDEI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) cxfi = CDFI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) omap_dma_chan_write(c, cxsa, d->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) omap_dma_chan_write(c, cxei, d->ei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) omap_dma_chan_write(c, cxfi, d->fi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) omap_dma_chan_write(c, CSDP, d->csdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) omap_dma_start_sg(c, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static void omap_dma_callback(int ch, u16 status, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct omap_chan *c = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct omap_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) spin_lock_irqsave(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) d = c->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (c->cyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) vchan_cyclic_callback(&d->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) } else if (d->using_ll || c->sgidx == d->sglen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) omap_dma_start_desc(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) vchan_cookie_complete(&d->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) omap_dma_start_sg(c, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) spin_unlock_irqrestore(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static irqreturn_t omap_dma_irq(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct omap_dmadev *od = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned status, channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) spin_lock(&od->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) status = omap_dma_glbl_read(od, IRQSTATUS_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) status &= od->irq_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) spin_unlock(&od->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) while ((channel = ffs(status)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) unsigned mask, csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct omap_chan *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) channel -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) mask = BIT(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) status &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) c = od->lch_map[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (c == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* This should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev_err(od->ddev.dev, "invalid channel %u\n", channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) csr = omap_dma_get_csr(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) omap_dma_glbl_write(od, IRQSTATUS_L1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) omap_dma_callback(channel, csr, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) spin_unlock(&od->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int omap_dma_get_lch(struct omap_dmadev *od, int *lch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mutex_lock(&od->lch_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) channel = find_first_zero_bit(od->lch_bitmap, od->lch_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (channel >= od->lch_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) goto out_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) set_bit(channel, od->lch_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mutex_unlock(&od->lch_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) omap_dma_clear_lch(od, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) *lch = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) out_busy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) mutex_unlock(&od->lch_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) *lch = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static void omap_dma_put_lch(struct omap_dmadev *od, int lch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) omap_dma_clear_lch(od, lch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) mutex_lock(&od->lch_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) clear_bit(lch, od->lch_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) mutex_unlock(&od->lch_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct omap_dmadev *od = to_omap_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct device *dev = od->ddev.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (od->legacy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ret = omap_request_dma(c->dma_sig, "DMA engine",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) omap_dma_callback, c, &c->dma_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret = omap_dma_get_lch(od, &c->dma_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_dbg(dev, "allocating channel %u for %u\n", c->dma_ch, c->dma_sig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) omap_dma_assign(od, c, c->dma_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!od->legacy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) unsigned val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) spin_lock_irq(&od->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) val = BIT(c->dma_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) omap_dma_glbl_write(od, IRQSTATUS_L1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) od->irq_enable_mask |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) val = omap_dma_glbl_read(od, IRQENABLE_L0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) val &= ~BIT(c->dma_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) omap_dma_glbl_write(od, IRQENABLE_L0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) spin_unlock_irq(&od->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (dma_omap1()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (__dma_omap16xx(od->plat->dma_attr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) c->ccr = CCR_OMAP31_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* Duplicate what plat-omap/dma.c does */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) c->ccr |= c->dma_ch + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) c->ccr = c->dma_sig & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) c->ccr = c->dma_sig & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) c->ccr |= (c->dma_sig & ~0x1f) << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) c->ccr |= CCR_BUFFERING_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static void omap_dma_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct omap_dmadev *od = to_omap_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (!od->legacy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) spin_lock_irq(&od->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) od->irq_enable_mask &= ~BIT(c->dma_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) spin_unlock_irq(&od->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) c->channel_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) od->lch_map[c->dma_ch] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) vchan_free_chan_resources(&c->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (od->legacy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) omap_free_dma(c->dma_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) omap_dma_put_lch(od, c->dma_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_dbg(od->ddev.dev, "freeing channel %u used for %u\n", c->dma_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) c->dma_sig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) c->dma_sig = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static size_t omap_dma_sg_size(struct omap_sg *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return sg->en * sg->fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static size_t omap_dma_desc_size(struct omap_desc *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) for (size = i = 0; i < d->sglen; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) size += omap_dma_sg_size(&d->sg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return size * es_bytes[d->es];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) size_t size, es_size = es_bytes[d->es];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) for (size = i = 0; i < d->sglen; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) size += this_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) else if (addr >= d->sg[i].addr &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) addr < d->sg[i].addr + this_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) size += d->sg[i].addr + this_size - addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * OMAP 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * read before the DMA controller finished disabling the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) val = omap_dma_chan_read(c, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (val == 0 && od->plat->errata & DMA_ERRATA_3_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) val = omap_dma_chan_read(c, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dma_addr_t addr, cdac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (__dma_omap15xx(od->plat->dma_attr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) addr = omap_dma_chan_read(c, CPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) addr = omap_dma_chan_read_3_3(c, CSAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) cdac = omap_dma_chan_read_3_3(c, CDAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * CDAC == 0 indicates that the DMA transfer on the channel has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * not been started (no data has been transferred so far).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * Return the programmed source start address in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (cdac == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) addr = omap_dma_chan_read(c, CSSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (dma_omap1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (__dma_omap15xx(od->plat->dma_attr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) addr = omap_dma_chan_read(c, CPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) addr = omap_dma_chan_read_3_3(c, CDAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * CDAC == 0 indicates that the DMA transfer on the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * has not been started (no data has been transferred so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * far). Return the programmed destination start address in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (addr == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) addr = omap_dma_chan_read(c, CDSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (dma_omap1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dma_cookie_t cookie, struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) enum dma_status ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct omap_desc *d = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ret = dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (ret == DMA_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) spin_lock_irqsave(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (c->desc && c->desc->vd.tx.cookie == cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) d = c->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (!txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dma_addr_t pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (d->dir == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) pos = omap_dma_get_src_pos(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) else if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) pos = omap_dma_get_dst_pos(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) txstate->residue = omap_dma_desc_size_pos(d, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct virt_dma_desc *vd = vchan_find_desc(&c->vc, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) txstate->residue = omap_dma_desc_size(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) to_omap_dma_desc(&vd->tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) txstate->residue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (ret == DMA_IN_PROGRESS && c->paused) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ret = DMA_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) } else if (d && d->polled && c->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) uint32_t ccr = omap_dma_chan_read(c, CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * The channel is no longer active, set the return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * accordingly and mark it as completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (!(ccr & CCR_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) omap_dma_start_desc(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) vchan_cookie_complete(&d->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) spin_unlock_irqrestore(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static void omap_dma_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) spin_lock_irqsave(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (vchan_issue_pending(&c->vc) && !c->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) omap_dma_start_desc(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) spin_unlock_irqrestore(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct omap_dmadev *od = to_omap_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) enum dma_slave_buswidth dev_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct scatterlist *sgent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct omap_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dma_addr_t dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) unsigned i, es, en, frame_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) bool ll_failed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u32 burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) u32 port_window, port_window_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (dir == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dev_addr = c->cfg.src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) dev_width = c->cfg.src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) burst = c->cfg.src_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) port_window = c->cfg.src_port_window_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) } else if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dev_addr = c->cfg.dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dev_width = c->cfg.dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) burst = c->cfg.dst_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) port_window = c->cfg.dst_port_window_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /* Bus width translates to the element size (ES) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) switch (dev_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) es = CSDP_DATA_TYPE_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) es = CSDP_DATA_TYPE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) es = CSDP_DATA_TYPE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) default: /* not reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* Now allocate and setup the descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) d = kzalloc(struct_size(d, sg, sglen), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) d->dir = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) d->dev_addr = dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) d->es = es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* When the port_window is used, one frame must cover the window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (port_window) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) burst = port_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) port_window_bytes = port_window * es_bytes[es];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) d->ei = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * One frame covers the port_window and by configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * the source frame index to be -1 * (port_window - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * we instruct the sDMA that after a frame is processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * it should move back to the start of the window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) d->fi = -(port_window_bytes - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) d->ccr = c->ccr | CCR_SYNC_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (dir == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) d->csdp = CSDP_DST_BURST_64 | CSDP_DST_PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) d->ccr |= CCR_DST_AMODE_POSTINC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (port_window) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) d->ccr |= CCR_SRC_AMODE_DBLIDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (port_window_bytes >= 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) d->csdp |= CSDP_SRC_BURST_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) else if (port_window_bytes >= 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) d->csdp |= CSDP_SRC_BURST_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) else if (port_window_bytes >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) d->csdp |= CSDP_SRC_BURST_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) d->ccr |= CCR_SRC_AMODE_CONSTANT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) d->csdp = CSDP_SRC_BURST_64 | CSDP_SRC_PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) d->ccr |= CCR_SRC_AMODE_POSTINC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (port_window) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) d->ccr |= CCR_DST_AMODE_DBLIDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (port_window_bytes >= 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) d->csdp |= CSDP_DST_BURST_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) else if (port_window_bytes >= 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) d->csdp |= CSDP_DST_BURST_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) else if (port_window_bytes >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) d->csdp |= CSDP_DST_BURST_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) d->ccr |= CCR_DST_AMODE_CONSTANT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) d->cicr = CICR_DROP_IE | CICR_BLOCK_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) d->csdp |= es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (dma_omap1()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) d->cicr |= CICR_TOUT_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) d->ccr |= CCR_TRIGGER_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (port_window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) d->csdp |= CSDP_WRITE_LAST_NON_POSTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) d->clnk_ctrl = c->dma_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * Build our scatterlist entries: each contains the address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * the number of elements (EN) in each frame, and the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * frames (FN). Number of bytes for this entry = ES * EN * FN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * Burst size translates to number of elements with frame sync.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * Note: DMA engine defines burst to be the number of dev-width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) en = burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) frame_bytes = es_bytes[es] * en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (sglen >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) d->using_ll = od->ll123_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) for_each_sg(sgl, sgent, sglen, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct omap_sg *osg = &d->sg[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) osg->addr = sg_dma_address(sgent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) osg->en = en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) osg->fn = sg_dma_len(sgent) / frame_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (d->using_ll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) osg->t2_desc = dma_pool_alloc(od->desc_pool, GFP_ATOMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) &osg->t2_desc_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (!osg->t2_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) dev_err(chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) "t2_desc[%d] allocation failed\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ll_failed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) d->using_ll = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) omap_dma_fill_type2_desc(d, i, dir, (i == sglen - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) d->sglen = sglen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* Release the dma_pool entries if one allocation failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (ll_failed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) for (i = 0; i < d->sglen; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct omap_sg *osg = &d->sg[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (osg->t2_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) dma_pool_free(od->desc_pool, osg->t2_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) osg->t2_desc_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) osg->t2_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) size_t period_len, enum dma_transfer_direction dir, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct omap_dmadev *od = to_omap_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) enum dma_slave_buswidth dev_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct omap_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) dma_addr_t dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) unsigned es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) u32 burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (dir == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) dev_addr = c->cfg.src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) dev_width = c->cfg.src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) burst = c->cfg.src_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) } else if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev_addr = c->cfg.dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dev_width = c->cfg.dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) burst = c->cfg.dst_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* Bus width translates to the element size (ES) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) switch (dev_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) es = CSDP_DATA_TYPE_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) es = CSDP_DATA_TYPE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) es = CSDP_DATA_TYPE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) default: /* not reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* Now allocate and setup the descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) d->dir = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) d->dev_addr = dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) d->fi = burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) d->es = es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) d->sg[0].addr = buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) d->sg[0].en = period_len / es_bytes[es];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) d->sg[0].fn = buf_len / period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) d->sglen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) d->ccr = c->ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) d->cicr = CICR_DROP_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (flags & DMA_PREP_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) d->cicr |= CICR_FRAME_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) d->csdp = es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (dma_omap1()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) d->cicr |= CICR_TOUT_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) d->ccr |= CCR_SYNC_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) d->ccr |= CCR_SYNC_ELEMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (dir == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) d->ccr |= CCR_TRIGGER_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) d->csdp |= CSDP_DST_PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) d->csdp |= CSDP_SRC_PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (__dma_omap15xx(od->plat->dma_attr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) d->ccr |= CCR_AUTO_INIT | CCR_REPEAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) c->cyclic = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return vchan_tx_prep(&c->vc, &d->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static struct dma_async_tx_descriptor *omap_dma_prep_dma_memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) size_t len, unsigned long tx_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct omap_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) uint8_t data_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) data_type = __ffs((src | dest | len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (data_type > CSDP_DATA_TYPE_32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) data_type = CSDP_DATA_TYPE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) d->dir = DMA_MEM_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) d->dev_addr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) d->fi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) d->es = data_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) d->sg[0].en = len / BIT(data_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) d->sg[0].fn = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) d->sg[0].addr = dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) d->sglen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) d->ccr = c->ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_POSTINC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (tx_flags & DMA_PREP_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) d->cicr |= CICR_FRAME_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) d->polled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) d->csdp = data_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (dma_omap1()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) d->cicr |= CICR_TOUT_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_EMIFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) d->csdp |= CSDP_DST_PACKED | CSDP_SRC_PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static struct dma_async_tx_descriptor *omap_dma_prep_dma_interleaved(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct dma_chan *chan, struct dma_interleaved_template *xt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct omap_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct omap_sg *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) uint8_t data_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) size_t src_icg, dst_icg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* Slave mode is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (is_slave_direction(xt->dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (xt->frame_size != 1 || xt->numf == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) data_type = __ffs((xt->src_start | xt->dst_start | xt->sgl[0].size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (data_type > CSDP_DATA_TYPE_32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) data_type = CSDP_DATA_TYPE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) sg = &d->sg[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) d->dir = DMA_MEM_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) d->dev_addr = xt->src_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) d->es = data_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) sg->en = xt->sgl[0].size / BIT(data_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) sg->fn = xt->numf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) sg->addr = xt->dst_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) d->sglen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) d->ccr = c->ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) src_icg = dmaengine_get_src_icg(xt, &xt->sgl[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dst_icg = dmaengine_get_dst_icg(xt, &xt->sgl[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (src_icg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) d->ccr |= CCR_SRC_AMODE_DBLIDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) d->ei = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) d->fi = src_icg + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) } else if (xt->src_inc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) d->ccr |= CCR_SRC_AMODE_POSTINC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) d->fi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) dev_err(chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) "%s: SRC constant addressing is not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) kfree(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (dst_icg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) d->ccr |= CCR_DST_AMODE_DBLIDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) sg->ei = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) sg->fi = dst_icg + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) } else if (xt->dst_inc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) d->ccr |= CCR_DST_AMODE_POSTINC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) sg->fi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) dev_err(chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) "%s: DST constant addressing is not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) kfree(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) d->cicr = CICR_DROP_IE | CICR_FRAME_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) d->csdp = data_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (dma_omap1()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) d->cicr |= CICR_TOUT_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_EMIFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) d->csdp |= CSDP_DST_PACKED | CSDP_SRC_PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return vchan_tx_prep(&c->vc, &d->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static int omap_dma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (cfg->src_maxburst > chan->device->max_burst ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) cfg->dst_maxburst > chan->device->max_burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) memcpy(&c->cfg, cfg, sizeof(c->cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) static int omap_dma_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) spin_lock_irqsave(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * Stop DMA activity: we assume the callback will not be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * after omap_dma_stop() returns (even if it does, it will see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * c->desc is NULL and exit.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (c->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) vchan_terminate_vdesc(&c->desc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) c->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /* Avoid stopping the dma twice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (!c->paused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) omap_dma_stop(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) c->cyclic = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) c->paused = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) vchan_get_all_descriptors(&c->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) spin_unlock_irqrestore(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) vchan_dma_desc_free_list(&c->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static void omap_dma_synchronize(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) vchan_synchronize(&c->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static int omap_dma_pause(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) struct omap_dmadev *od = to_omap_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) bool can_pause = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) spin_lock_irqsave(&od->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (!c->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (c->cyclic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) can_pause = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * We do not allow DMA_MEM_TO_DEV transfers to be paused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * From the AM572x TRM, 16.1.4.18 Disabling a Channel During Transfer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * "When a channel is disabled during a transfer, the channel undergoes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * an abort, unless it is hardware-source-synchronized …".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * A source-synchronised channel is one where the fetching of data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * under control of the device. In other words, a device-to-memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * transfer. So, a destination-synchronised channel (which would be a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) * memory-to-device transfer) undergoes an abort if the the CCR_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * bit is cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) * From 16.1.4.20.4.6.2 Abort: "If an abort trigger occurs, the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * aborts immediately after completion of current read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * transactions and then the FIFO is cleaned up." The term "cleaned up"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) * is not defined. TI recommends to check that RD_ACTIVE and WR_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * are both clear _before_ disabling the channel, otherwise data loss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * will occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * The problem is that if the channel is active, then device activity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) * can result in DMA activity starting between reading those as both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * clear and the write to DMA_CCR to clear the enable bit hitting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * hardware. If the DMA hardware can't drain the data in its FIFO to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * destination, then data loss "might" occur (say if we write to an UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * and the UART is not accepting any further data).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) else if (c->desc->dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) can_pause = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (can_pause && !c->paused) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) ret = omap_dma_stop(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) c->paused = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) spin_unlock_irqrestore(&od->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static int omap_dma_resume(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) struct omap_dmadev *od = to_omap_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) spin_lock_irqsave(&od->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (c->paused && c->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) /* Restore channel link register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) omap_dma_chan_write(c, CLNK_CTRL, c->desc->clnk_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) omap_dma_start(c, c->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) c->paused = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) spin_unlock_irqrestore(&od->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static int omap_dma_chan_init(struct omap_dmadev *od)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct omap_chan *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) c = kzalloc(sizeof(*c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (!c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) c->reg_map = od->reg_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) c->vc.desc_free = omap_dma_desc_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) vchan_init(&c->vc, &od->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static void omap_dma_free(struct omap_dmadev *od)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) while (!list_empty(&od->ddev.channels)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct omap_chan *c = list_first_entry(&od->ddev.channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct omap_chan, vc.chan.device_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) list_del(&c->vc.chan.device_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) tasklet_kill(&c->vc.task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) kfree(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* Currently used by omap2 & 3 to block deeper SoC idle states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static bool omap_dma_busy(struct omap_dmadev *od)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) struct omap_chan *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) int lch = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) lch = find_next_bit(od->lch_bitmap, od->lch_count, lch + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (lch >= od->lch_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) c = od->lch_map[lch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (!c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (omap_dma_chan_read(c, CCR) & CCR_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) /* Currently only used for omap2. For omap1, also a check for lcd_dma is needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static int omap_dma_busy_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) unsigned long cmd, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) struct omap_dmadev *od;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) od = container_of(nb, struct omap_dmadev, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) case CPU_CLUSTER_PM_ENTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (omap_dma_busy(od))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) case CPU_CLUSTER_PM_ENTER_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) case CPU_CLUSTER_PM_EXIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * We are using IRQENABLE_L1, and legacy DMA code was using IRQENABLE_L0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * As the DSP may be using IRQENABLE_L2 and L3, let's not touch those for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * now. Context save seems to be only currently needed on omap3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static void omap_dma_context_save(struct omap_dmadev *od)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) od->context.irqenable_l0 = omap_dma_glbl_read(od, IRQENABLE_L0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) od->context.irqenable_l1 = omap_dma_glbl_read(od, IRQENABLE_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) od->context.ocp_sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) od->context.gcr = omap_dma_glbl_read(od, GCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static void omap_dma_context_restore(struct omap_dmadev *od)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) omap_dma_glbl_write(od, GCR, od->context.gcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) omap_dma_glbl_write(od, OCP_SYSCONFIG, od->context.ocp_sysconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) omap_dma_glbl_write(od, IRQENABLE_L0, od->context.irqenable_l0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) omap_dma_glbl_write(od, IRQENABLE_L1, od->context.irqenable_l1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) /* Clear IRQSTATUS_L0 as legacy DMA code is no longer doing it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (od->plat->errata & DMA_ROMCODE_BUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) omap_dma_glbl_write(od, IRQSTATUS_L0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* Clear dma channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) for (i = 0; i < od->lch_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) omap_dma_clear_lch(od, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* Currently only used for omap3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) static int omap_dma_context_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) unsigned long cmd, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct omap_dmadev *od;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) od = container_of(nb, struct omap_dmadev, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) case CPU_CLUSTER_PM_ENTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (omap_dma_busy(od))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) omap_dma_context_save(od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) case CPU_CLUSTER_PM_ENTER_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) case CPU_CLUSTER_PM_EXIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) omap_dma_context_restore(od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static void omap_dma_init_gcr(struct omap_dmadev *od, int arb_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) int max_fifo_depth, int tparams)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) /* Set only for omap2430 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (!od->cfg->rw_priority)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (max_fifo_depth == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) max_fifo_depth = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (arb_rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) arb_rate = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) val = 0xff & max_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) val |= (0x3 & tparams) << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) val |= (arb_rate & 0xff) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) omap_dma_glbl_write(od, GCR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #define OMAP_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * No flags currently set for default configuration as omap1 is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * using platform data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) static const struct omap_dma_config default_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static int omap_dma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) const struct omap_dma_config *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) struct omap_dmadev *od;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) int rc, i, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (!od)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) od->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (IS_ERR(od->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) return PTR_ERR(od->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) conf = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (conf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) od->cfg = conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) od->plat = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (!od->plat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) dev_err(&pdev->dev, "omap_system_dma_plat_info is missing");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) od->cfg = &default_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) od->plat = omap_get_plat_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (!od->plat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) od->reg_map = od->plat->reg_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) dma_cap_set(DMA_INTERLEAVE, od->ddev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) od->ddev.device_free_chan_resources = omap_dma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) od->ddev.device_tx_status = omap_dma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) od->ddev.device_issue_pending = omap_dma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) od->ddev.device_prep_dma_memcpy = omap_dma_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) od->ddev.device_prep_interleaved_dma = omap_dma_prep_dma_interleaved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) od->ddev.device_config = omap_dma_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) od->ddev.device_pause = omap_dma_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) od->ddev.device_resume = omap_dma_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) od->ddev.device_terminate_all = omap_dma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) od->ddev.device_synchronize = omap_dma_synchronize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) od->ddev.src_addr_widths = OMAP_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) od->ddev.dst_addr_widths = OMAP_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (__dma_omap15xx(od->plat->dma_attr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) od->ddev.residue_granularity =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) od->ddev.max_burst = SZ_16M - 1; /* CCEN: 24bit unsigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) od->ddev.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) INIT_LIST_HEAD(&od->ddev.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) mutex_init(&od->lch_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) spin_lock_init(&od->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) spin_lock_init(&od->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /* Number of DMA requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) od->dma_requests = OMAP_SDMA_REQUESTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) "dma-requests",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) &od->dma_requests)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) "Missing dma-requests property, using %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) OMAP_SDMA_REQUESTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) /* Number of available logical channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (!pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) od->lch_count = od->plat->dma_attr->lch_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (unlikely(!od->lch_count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) od->lch_count = OMAP_SDMA_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) } else if (of_property_read_u32(pdev->dev.of_node, "dma-channels",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) &od->lch_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) "Missing dma-channels property, using %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) OMAP_SDMA_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) od->lch_count = OMAP_SDMA_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* Mask of allowed logical channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if (pdev->dev.of_node && !of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) "dma-channel-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /* Tag channels not in mask as reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) val = ~val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) bitmap_from_arr32(od->lch_bitmap, &val, od->lch_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) if (od->plat->dma_attr->dev_caps & HS_CHANNELS_RESERVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) bitmap_set(od->lch_bitmap, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) od->lch_map = devm_kcalloc(&pdev->dev, od->lch_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) sizeof(*od->lch_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (!od->lch_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) for (i = 0; i < od->dma_requests; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) rc = omap_dma_chan_init(od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) omap_dma_free(od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) dev_info(&pdev->dev, "failed to get L1 IRQ: %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) od->legacy = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) od->irq_enable_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) omap_dma_glbl_write(od, IRQENABLE_L1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) rc = devm_request_irq(&pdev->dev, irq, omap_dma_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) IRQF_SHARED, "omap-dma-engine", od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) omap_dma_free(od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if (omap_dma_glbl_read(od, CAPS_0) & CAPS_0_SUPPORT_LL123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) od->ll123_supported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) od->ddev.filter.map = od->plat->slave_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) od->ddev.filter.mapcnt = od->plat->slavecnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) od->ddev.filter.fn = omap_dma_filter_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (od->ll123_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) od->desc_pool = dma_pool_create(dev_name(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) sizeof(struct omap_type2_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) if (!od->desc_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) "unable to allocate descriptor pool\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) od->ll123_supported = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) rc = dma_async_device_register(&od->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) omap_dma_free(od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) platform_set_drvdata(pdev, od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) omap_dma_info.dma_cap = od->ddev.cap_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) /* Device-tree DMA controller registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) rc = of_dma_controller_register(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) of_dma_simple_xlate, &omap_dma_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) pr_warn("OMAP-DMA: failed to register DMA controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) dma_async_device_unregister(&od->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) omap_dma_free(od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) omap_dma_init_gcr(od, DMA_DEFAULT_ARB_RATE, DMA_DEFAULT_FIFO_DEPTH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (od->cfg->needs_busy_check) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) od->nb.notifier_call = omap_dma_busy_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) cpu_pm_register_notifier(&od->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) } else if (od->cfg->may_lose_context) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) od->nb.notifier_call = omap_dma_context_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) cpu_pm_register_notifier(&od->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) dev_info(&pdev->dev, "OMAP DMA engine driver%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) od->ll123_supported ? " (LinkedList1/2/3 supported)" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) static int omap_dma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct omap_dmadev *od = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (od->cfg->may_lose_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) cpu_pm_unregister_notifier(&od->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) of_dma_controller_free(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) devm_free_irq(&pdev->dev, irq, od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) dma_async_device_unregister(&od->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (!od->legacy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) omap_dma_glbl_write(od, IRQENABLE_L0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) if (od->ll123_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) dma_pool_destroy(od->desc_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) omap_dma_free(od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) static const struct omap_dma_config omap2420_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .lch_end = CCFN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .rw_priority = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .needs_lch_clear = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .needs_busy_check = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) static const struct omap_dma_config omap2430_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .lch_end = CCFN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .rw_priority = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .needs_lch_clear = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) static const struct omap_dma_config omap3430_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .lch_end = CCFN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .rw_priority = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .needs_lch_clear = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .may_lose_context = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) static const struct omap_dma_config omap3630_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .lch_end = CCDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .rw_priority = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .needs_lch_clear = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .may_lose_context = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static const struct omap_dma_config omap4_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .lch_end = CCDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .rw_priority = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .needs_lch_clear = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) static const struct of_device_id omap_dma_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) { .compatible = "ti,omap2420-sdma", .data = &omap2420_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) { .compatible = "ti,omap2430-sdma", .data = &omap2430_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) { .compatible = "ti,omap3430-sdma", .data = &omap3430_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) { .compatible = "ti,omap3630-sdma", .data = &omap3630_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) { .compatible = "ti,omap4430-sdma", .data = &omap4_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) MODULE_DEVICE_TABLE(of, omap_dma_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) static struct platform_driver omap_dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .probe = omap_dma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .remove = omap_dma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .name = "omap-dma-engine",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .of_match_table = omap_dma_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) static bool omap_dma_filter_fn(struct dma_chan *chan, void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) if (chan->device->dev->driver == &omap_dma_driver.driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) struct omap_dmadev *od = to_omap_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) struct omap_chan *c = to_omap_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) unsigned req = *(unsigned *)param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (req <= od->dma_requests) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) c->dma_sig = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) static int omap_dma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return platform_driver_register(&omap_dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) subsys_initcall(omap_dma_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static void __exit omap_dma_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) platform_driver_unregister(&omap_dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) module_exit(omap_dma_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) MODULE_AUTHOR("Russell King");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags