^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef K3_UDMA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define K3_UDMA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/soc/ti/ti_sci_protocol.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Global registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define UDMA_REV_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define UDMA_PERF_CTL_REG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define UDMA_EMU_CTL_REG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define UDMA_PSIL_TO_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define UDMA_UTC_CTL_REG 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define UDMA_CAP_REG(i) (0x20 + ((i) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* TCHANRT/RCHANRT registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define UDMA_CHAN_RT_CTL_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define UDMA_CHAN_RT_SWTRIG_REG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define UDMA_CHAN_RT_STDATA_REG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define UDMA_CHAN_RT_PEER_REG(i) (0x200 + ((i) * 0x4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UDMA_CHAN_RT_PEER_STATIC_TR_XY_REG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) UDMA_CHAN_RT_PEER_REG(0) /* PSI-L: 0x400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UDMA_CHAN_RT_PEER_STATIC_TR_Z_REG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) UDMA_CHAN_RT_PEER_REG(1) /* PSI-L: 0x401 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UDMA_CHAN_RT_PEER_BCNT_REG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) UDMA_CHAN_RT_PEER_REG(4) /* PSI-L: 0x404 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UDMA_CHAN_RT_PEER_RT_EN_REG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) UDMA_CHAN_RT_PEER_REG(8) /* PSI-L: 0x408 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UDMA_CHAN_RT_PCNT_REG 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UDMA_CHAN_RT_BCNT_REG 0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define UDMA_CHAN_RT_SBCNT_REG 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* UDMA_CAP Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UDMA_CAP2_TCHAN_CNT(val) ((val) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define UDMA_CAP2_ECHAN_CNT(val) (((val) >> 9) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UDMA_CAP2_RCHAN_CNT(val) (((val) >> 18) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UDMA_CAP3_RFLOW_CNT(val) ((val) & 0x3fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UDMA_CAP3_HCHAN_CNT(val) (((val) >> 14) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define UDMA_CAP3_UCHAN_CNT(val) (((val) >> 23) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* UDMA_CHAN_RT_CTL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UDMA_CHAN_RT_CTL_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UDMA_CHAN_RT_CTL_TDOWN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define UDMA_CHAN_RT_CTL_PAUSE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define UDMA_CHAN_RT_CTL_FTDOWN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define UDMA_CHAN_RT_CTL_ERROR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* UDMA_CHAN_RT_PEER_RT_EN_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UDMA_PEER_RT_EN_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UDMA_PEER_RT_EN_TEARDOWN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UDMA_PEER_RT_EN_PAUSE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UDMA_PEER_RT_EN_FLUSH BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UDMA_PEER_RT_EN_IDLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PDMA_STATIC_TR_X_MASK GENMASK(26, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PDMA_STATIC_TR_X_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PDMA_STATIC_TR_Y_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PDMA_STATIC_TR_Y_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PDMA_STATIC_TR_Y(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (((x) << PDMA_STATIC_TR_Y_SHIFT) & PDMA_STATIC_TR_Y_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PDMA_STATIC_TR_X(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (((x) << PDMA_STATIC_TR_X_SHIFT) & PDMA_STATIC_TR_X_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PDMA_STATIC_TR_XY_ACC32 BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PDMA_STATIC_TR_XY_BURST BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PDMA_STATIC_TR_Z(x, mask) ((x) & (mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct udma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct udma_tchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct udma_rchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct udma_rflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) enum udma_rm_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) RM_RANGE_TCHAN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) RM_RANGE_RCHAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) RM_RANGE_RFLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) RM_RANGE_LAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct udma_tisci_rm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const struct ti_sci_handle *tisci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 tisci_dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* tisci information for PSI-L thread pairing/unpairing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const struct ti_sci_rm_psil_ops *tisci_psil_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 tisci_navss_dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Direct access to UDMA low lever resources for the glue layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 dst_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct udma_dev *of_xudma_dev_get(struct device_node *np, const char *property);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void xudma_dev_put(struct udma_dev *ud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 xudma_dev_get_psil_base(struct udma_dev *ud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct udma_tisci_rm *xudma_dev_get_tisci_rm(struct udma_dev *ud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int xudma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int xudma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct udma_tchan *xudma_tchan_get(struct udma_dev *ud, int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct udma_rchan *xudma_rchan_get(struct udma_dev *ud, int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct udma_rflow *xudma_rflow_get(struct udma_dev *ud, int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void xudma_tchan_put(struct udma_dev *ud, struct udma_tchan *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void xudma_rchan_put(struct udma_dev *ud, struct udma_rchan *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void xudma_rflow_put(struct udma_dev *ud, struct udma_rflow *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int xudma_tchan_get_id(struct udma_tchan *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int xudma_rchan_get_id(struct udma_rchan *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int xudma_rflow_get_id(struct udma_rflow *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 xudma_tchanrt_read(struct udma_tchan *tchan, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void xudma_tchanrt_write(struct udma_tchan *tchan, int reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 xudma_rchanrt_read(struct udma_rchan *rchan, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void xudma_rchanrt_write(struct udma_rchan *rchan, int reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool xudma_rflow_is_gp(struct udma_dev *ud, int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif /* K3_UDMA_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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