^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) return navss_psil_pair(ud, src_thread, dst_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) EXPORT_SYMBOL(xudma_navss_psil_pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, u32 dst_thread)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) return navss_psil_unpair(ud, src_thread, dst_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) EXPORT_SYMBOL(xudma_navss_psil_unpair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct udma_dev *of_xudma_dev_get(struct device_node *np, const char *property)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct device_node *udma_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct udma_dev *ud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) if (property) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) udma_node = of_parse_phandle(np, property, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (!udma_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pr_err("UDMA node is not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) pdev = of_find_device_by_node(udma_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (!pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) pr_debug("UDMA device not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (np != udma_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) of_node_put(udma_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ud = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (!ud) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) pr_debug("UDMA has not been probed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) put_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return ud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) EXPORT_SYMBOL(of_xudma_dev_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 xudma_dev_get_psil_base(struct udma_dev *ud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return ud->psil_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) EXPORT_SYMBOL(xudma_dev_get_psil_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct udma_tisci_rm *xudma_dev_get_tisci_rm(struct udma_dev *ud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return &ud->tisci_rm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) EXPORT_SYMBOL(xudma_dev_get_tisci_rm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int xudma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return __udma_alloc_gp_rflow_range(ud, from, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) EXPORT_SYMBOL(xudma_alloc_gp_rflow_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int xudma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return __udma_free_gp_rflow_range(ud, from, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) EXPORT_SYMBOL(xudma_free_gp_rflow_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bool xudma_rflow_is_gp(struct udma_dev *ud, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return !test_bit(id, ud->rflow_gp_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) EXPORT_SYMBOL(xudma_rflow_is_gp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define XUDMA_GET_PUT_RESOURCE(res) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct udma_##res *xudma_##res##_get(struct udma_dev *ud, int id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return __udma_reserve_##res(ud, UDMA_TP_NORMAL, id); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) EXPORT_SYMBOL(xudma_##res##_get); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void xudma_##res##_put(struct udma_dev *ud, struct udma_##res *p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clear_bit(p->id, ud->res##_map); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) EXPORT_SYMBOL(xudma_##res##_put)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) XUDMA_GET_PUT_RESOURCE(tchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) XUDMA_GET_PUT_RESOURCE(rchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct udma_rflow *xudma_rflow_get(struct udma_dev *ud, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return __udma_get_rflow(ud, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) EXPORT_SYMBOL(xudma_rflow_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void xudma_rflow_put(struct udma_dev *ud, struct udma_rflow *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __udma_put_rflow(ud, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) EXPORT_SYMBOL(xudma_rflow_put);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define XUDMA_GET_RESOURCE_ID(res) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int xudma_##res##_get_id(struct udma_##res *p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return p->id; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) EXPORT_SYMBOL(xudma_##res##_get_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) XUDMA_GET_RESOURCE_ID(tchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) XUDMA_GET_RESOURCE_ID(rchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) XUDMA_GET_RESOURCE_ID(rflow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Exported register access functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define XUDMA_RT_IO_FUNCTIONS(res) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 xudma_##res##rt_read(struct udma_##res *p, int reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return udma_read(p->reg_rt, reg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) EXPORT_SYMBOL(xudma_##res##rt_read); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void xudma_##res##rt_write(struct udma_##res *p, int reg, u32 val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) udma_write(p->reg_rt, reg, val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) EXPORT_SYMBOL(xudma_##res##rt_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) XUDMA_RT_IO_FUNCTIONS(tchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) XUDMA_RT_IO_FUNCTIONS(rchan);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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