Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include "k3-psil-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define PSIL_PDMA_XY_TR(x)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 		.thread_id = x,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 		.ep_config = {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 			.ep_type = PSIL_EP_PDMA_XY,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 		},					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PSIL_PDMA_XY_PKT(x)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 		.thread_id = x,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		.ep_config = {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 			.ep_type = PSIL_EP_PDMA_XY,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 			.pkt_mode = 1,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		},					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PSIL_PDMA_MCASP(x)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		.thread_id = x,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		.ep_config = {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 			.ep_type = PSIL_EP_PDMA_XY,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 			.pdma_acc32 = 1,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			.pdma_burst = 1,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		},					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PSIL_ETHERNET(x)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.thread_id = x,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.ep_config = {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			.ep_type = PSIL_EP_NATIVE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			.pkt_mode = 1,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			.needs_epib = 1,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			.psd_size = 16,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		},					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PSIL_SA2UL(x, tx)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.thread_id = x,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.ep_config = {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			.ep_type = PSIL_EP_NATIVE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			.pkt_mode = 1,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			.needs_epib = 1,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			.psd_size = 64,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 			.notdpkt = tx,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		},					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static struct psil_ep j721e_src_ep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* SA2UL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	PSIL_SA2UL(0x4000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	PSIL_SA2UL(0x4001, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	PSIL_SA2UL(0x4002, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	PSIL_SA2UL(0x4003, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* PRU_ICSSG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	PSIL_ETHERNET(0x4100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	PSIL_ETHERNET(0x4101),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	PSIL_ETHERNET(0x4102),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	PSIL_ETHERNET(0x4103),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* PRU_ICSSG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	PSIL_ETHERNET(0x4200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	PSIL_ETHERNET(0x4201),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	PSIL_ETHERNET(0x4202),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	PSIL_ETHERNET(0x4203),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* PDMA6 (PSIL_PDMA_MCASP_G0) - McASP0-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	PSIL_PDMA_MCASP(0x4400),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	PSIL_PDMA_MCASP(0x4401),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	PSIL_PDMA_MCASP(0x4402),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* PDMA7 (PSIL_PDMA_MCASP_G1) - McASP3-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	PSIL_PDMA_MCASP(0x4500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	PSIL_PDMA_MCASP(0x4501),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	PSIL_PDMA_MCASP(0x4502),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	PSIL_PDMA_MCASP(0x4503),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	PSIL_PDMA_MCASP(0x4504),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	PSIL_PDMA_MCASP(0x4505),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	PSIL_PDMA_MCASP(0x4506),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	PSIL_PDMA_MCASP(0x4507),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	PSIL_PDMA_MCASP(0x4508),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* PDMA8 (PDMA_MISC_G0) - SPI0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	PSIL_PDMA_XY_PKT(0x4600),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	PSIL_PDMA_XY_PKT(0x4601),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	PSIL_PDMA_XY_PKT(0x4602),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	PSIL_PDMA_XY_PKT(0x4603),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	PSIL_PDMA_XY_PKT(0x4604),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	PSIL_PDMA_XY_PKT(0x4605),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	PSIL_PDMA_XY_PKT(0x4606),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	PSIL_PDMA_XY_PKT(0x4607),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/* PDMA9 (PDMA_MISC_G1) - SPI2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	PSIL_PDMA_XY_PKT(0x460c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	PSIL_PDMA_XY_PKT(0x460d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	PSIL_PDMA_XY_PKT(0x460e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	PSIL_PDMA_XY_PKT(0x460f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	PSIL_PDMA_XY_PKT(0x4610),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	PSIL_PDMA_XY_PKT(0x4611),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	PSIL_PDMA_XY_PKT(0x4612),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	PSIL_PDMA_XY_PKT(0x4613),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/* PDMA10 (PDMA_MISC_G2) - SPI4-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	PSIL_PDMA_XY_PKT(0x4618),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	PSIL_PDMA_XY_PKT(0x4619),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	PSIL_PDMA_XY_PKT(0x461a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	PSIL_PDMA_XY_PKT(0x461b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	PSIL_PDMA_XY_PKT(0x461c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	PSIL_PDMA_XY_PKT(0x461d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	PSIL_PDMA_XY_PKT(0x461e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	PSIL_PDMA_XY_PKT(0x461f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/* PDMA11 (PDMA_MISC_G3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	PSIL_PDMA_XY_PKT(0x4624),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	PSIL_PDMA_XY_PKT(0x4625),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	PSIL_PDMA_XY_PKT(0x4626),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	PSIL_PDMA_XY_PKT(0x4627),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	PSIL_PDMA_XY_PKT(0x4628),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	PSIL_PDMA_XY_PKT(0x4629),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	PSIL_PDMA_XY_PKT(0x4630),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	PSIL_PDMA_XY_PKT(0x463a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* PDMA13 (PDMA_USART_G0) - UART0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	PSIL_PDMA_XY_PKT(0x4700),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	PSIL_PDMA_XY_PKT(0x4701),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* PDMA14 (PDMA_USART_G1) - UART2-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	PSIL_PDMA_XY_PKT(0x4702),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	PSIL_PDMA_XY_PKT(0x4703),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* PDMA15 (PDMA_USART_G2) - UART4-9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	PSIL_PDMA_XY_PKT(0x4704),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	PSIL_PDMA_XY_PKT(0x4705),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	PSIL_PDMA_XY_PKT(0x4706),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	PSIL_PDMA_XY_PKT(0x4707),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	PSIL_PDMA_XY_PKT(0x4708),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	PSIL_PDMA_XY_PKT(0x4709),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* CPSW9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	PSIL_ETHERNET(0x4a00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* CPSW0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	PSIL_ETHERNET(0x7000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	PSIL_PDMA_XY_PKT(0x7100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	PSIL_PDMA_XY_PKT(0x7101),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	PSIL_PDMA_XY_PKT(0x7102),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	PSIL_PDMA_XY_PKT(0x7103),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	PSIL_PDMA_XY_PKT(0x7200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	PSIL_PDMA_XY_PKT(0x7201),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	PSIL_PDMA_XY_PKT(0x7202),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	PSIL_PDMA_XY_PKT(0x7203),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	PSIL_PDMA_XY_PKT(0x7204),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	PSIL_PDMA_XY_PKT(0x7205),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	PSIL_PDMA_XY_PKT(0x7206),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	PSIL_PDMA_XY_PKT(0x7207),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	/* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	PSIL_PDMA_XY_PKT(0x7300),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* MCU_PDMA_ADC - ADC0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	PSIL_PDMA_XY_TR(0x7400),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	PSIL_PDMA_XY_TR(0x7401),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	PSIL_PDMA_XY_TR(0x7402),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	PSIL_PDMA_XY_TR(0x7403),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* SA2UL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	PSIL_SA2UL(0x7500, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	PSIL_SA2UL(0x7501, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	PSIL_SA2UL(0x7502, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	PSIL_SA2UL(0x7503, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct psil_ep j721e_dst_ep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* SA2UL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	PSIL_SA2UL(0xc000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	PSIL_SA2UL(0xc001, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* PRU_ICSSG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	PSIL_ETHERNET(0xc100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	PSIL_ETHERNET(0xc101),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	PSIL_ETHERNET(0xc102),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	PSIL_ETHERNET(0xc103),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	PSIL_ETHERNET(0xc104),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	PSIL_ETHERNET(0xc105),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	PSIL_ETHERNET(0xc106),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	PSIL_ETHERNET(0xc107),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	/* PRU_ICSSG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	PSIL_ETHERNET(0xc200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	PSIL_ETHERNET(0xc201),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	PSIL_ETHERNET(0xc202),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	PSIL_ETHERNET(0xc203),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	PSIL_ETHERNET(0xc204),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	PSIL_ETHERNET(0xc205),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	PSIL_ETHERNET(0xc206),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	PSIL_ETHERNET(0xc207),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/* CPSW9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	PSIL_ETHERNET(0xca00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	PSIL_ETHERNET(0xca01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	PSIL_ETHERNET(0xca02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	PSIL_ETHERNET(0xca03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	PSIL_ETHERNET(0xca04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	PSIL_ETHERNET(0xca05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	PSIL_ETHERNET(0xca06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	PSIL_ETHERNET(0xca07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* CPSW0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	PSIL_ETHERNET(0xf000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	PSIL_ETHERNET(0xf001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	PSIL_ETHERNET(0xf002),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	PSIL_ETHERNET(0xf003),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	PSIL_ETHERNET(0xf004),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	PSIL_ETHERNET(0xf005),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	PSIL_ETHERNET(0xf006),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	PSIL_ETHERNET(0xf007),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/* SA2UL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	PSIL_SA2UL(0xf500, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	PSIL_SA2UL(0xf501, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct psil_ep_map j721e_ep_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.name = "j721e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.src = j721e_src_ep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.src_count = ARRAY_SIZE(j721e_src_ep_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.dst = j721e_dst_ep_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.dst_count = ARRAY_SIZE(j721e_dst_ep_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };