^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TI_XBAR_DRA7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TI_XBAR_AM335X 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static const u32 ti_xbar_type[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) [TI_XBAR_DRA7] = TI_XBAR_DRA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) [TI_XBAR_AM335X] = TI_XBAR_AM335X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct of_device_id ti_dma_xbar_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .compatible = "ti,dra7-dma-crossbar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .data = &ti_xbar_type[TI_XBAR_DRA7],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .compatible = "ti,am335x-edma-crossbar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .data = &ti_xbar_type[TI_XBAR_AM335X],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Crossbar on AM335x/AM437x family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TI_AM335X_XBAR_LINES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct ti_am335x_xbar_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct dma_router dmarouter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 xbar_events; /* maximum number of events to select in xbar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 dma_requests; /* number of DMA requests on eDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct ti_am335x_xbar_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u16 dma_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 mux_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline void ti_am335x_xbar_write(void __iomem *iomem, int event, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * TPCC_EVT_MUX_60_63 register layout is different than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * rest, in the sense, that event 63 is mapped to lowest byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * and event 60 is mapped to highest, handle it separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (event >= 60 && event <= 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writeb_relaxed(val, iomem + (63 - event % 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) writeb_relaxed(val, iomem + event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void ti_am335x_xbar_free(struct device *dev, void *route_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct ti_am335x_xbar_data *xbar = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct ti_am335x_xbar_map *map = route_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) dev_dbg(dev, "Unmapping XBAR event %u on channel %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) map->mux_val, map->dma_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ti_am335x_xbar_write(xbar->iomem, map->dma_line, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) kfree(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static void *ti_am335x_xbar_route_allocate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct ti_am335x_xbar_data *xbar = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct ti_am335x_xbar_map *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (dma_spec->args_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (dma_spec->args[2] >= xbar->xbar_events) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev_err(&pdev->dev, "Invalid XBAR event number: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dma_spec->args[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (dma_spec->args[0] >= xbar->dma_requests) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev_err(&pdev->dev, "Invalid DMA request line number: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dma_spec->args[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* The of_node_put() will be done in the core for the node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!dma_spec->np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dev_err(&pdev->dev, "Can't get DMA master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) map = kzalloc(sizeof(*map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (!map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) of_node_put(dma_spec->np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) map->dma_line = (u16)dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) map->mux_val = (u8)dma_spec->args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dma_spec->args[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dma_spec->args_count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_dbg(&pdev->dev, "Mapping XBAR event%u to DMA%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) map->mux_val, map->dma_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ti_am335x_xbar_write(xbar->iomem, map->dma_line, map->mux_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct of_device_id ti_am335x_master_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { .compatible = "ti,edma3-tpcc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int ti_am335x_xbar_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct device_node *dma_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct ti_am335x_xbar_data *xbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void __iomem *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) xbar = devm_kzalloc(&pdev->dev, sizeof(*xbar), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!xbar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dma_node = of_parse_phandle(node, "dma-masters", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!dma_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_err(&pdev->dev, "Can't get DMA master node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) match = of_match_node(ti_am335x_master_match, dma_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dev_err(&pdev->dev, "DMA master is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) of_node_put(dma_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (of_property_read_u32(dma_node, "dma-requests",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) &xbar->dma_requests)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "Missing XBAR output information, using %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) TI_AM335X_XBAR_LINES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) xbar->dma_requests = TI_AM335X_XBAR_LINES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) of_node_put(dma_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (of_property_read_u32(node, "dma-requests", &xbar->xbar_events)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "Missing XBAR input information, using %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) TI_AM335X_XBAR_LINES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) xbar->xbar_events = TI_AM335X_XBAR_LINES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) iomem = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (IS_ERR(iomem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return PTR_ERR(iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) xbar->iomem = iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) xbar->dmarouter.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) xbar->dmarouter.route_free = ti_am335x_xbar_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) platform_set_drvdata(pdev, xbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Reset the crossbar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for (i = 0; i < xbar->dma_requests; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ti_am335x_xbar_write(xbar->iomem, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = of_dma_router_register(node, ti_am335x_xbar_route_allocate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) &xbar->dmarouter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Crossbar on DRA7xx family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TI_DRA7_XBAR_OUTPUTS 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TI_DRA7_XBAR_INPUTS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct ti_dra7_xbar_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void __iomem *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct dma_router dmarouter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned long *dma_inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u16 safe_val; /* Value to rest the crossbar lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 xbar_requests; /* number of DMA requests connected to XBAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 dma_requests; /* number of DMA requests forwarded to DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 dma_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct ti_dra7_xbar_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u16 xbar_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int xbar_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static inline void ti_dra7_xbar_write(void __iomem *iomem, int xbar, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writew_relaxed(val, iomem + (xbar * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void ti_dra7_xbar_free(struct device *dev, void *route_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct ti_dra7_xbar_data *xbar = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct ti_dra7_xbar_map *map = route_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_dbg(dev, "Unmapping XBAR%u (was routed to %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) map->xbar_in, map->xbar_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ti_dra7_xbar_write(xbar->iomem, map->xbar_out, xbar->safe_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mutex_lock(&xbar->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) clear_bit(map->xbar_out, xbar->dma_inuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mutex_unlock(&xbar->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) kfree(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void *ti_dra7_xbar_route_allocate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct ti_dra7_xbar_data *xbar = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct ti_dra7_xbar_map *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (dma_spec->args[0] >= xbar->xbar_requests) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_err(&pdev->dev, "Invalid XBAR request number: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dma_spec->args[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* The of_node_put() will be done in the core for the node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (!dma_spec->np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_err(&pdev->dev, "Can't get DMA master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) map = kzalloc(sizeof(*map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (!map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) of_node_put(dma_spec->np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mutex_lock(&xbar->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) map->xbar_out = find_first_zero_bit(xbar->dma_inuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) xbar->dma_requests);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (map->xbar_out == xbar->dma_requests) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mutex_unlock(&xbar->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_err(&pdev->dev, "Run out of free DMA requests\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) kfree(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) set_bit(map->xbar_out, xbar->dma_inuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mutex_unlock(&xbar->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) map->xbar_in = (u16)dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dma_spec->args[0] = map->xbar_out + xbar->dma_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_dbg(&pdev->dev, "Mapping XBAR%u to DMA%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) map->xbar_in, map->xbar_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ti_dra7_xbar_write(xbar->iomem, map->xbar_out, map->xbar_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TI_XBAR_EDMA_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define TI_XBAR_SDMA_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const u32 ti_dma_offset[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [TI_XBAR_EDMA_OFFSET] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [TI_XBAR_SDMA_OFFSET] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct of_device_id ti_dra7_master_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .compatible = "ti,omap4430-sdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .data = &ti_dma_offset[TI_XBAR_SDMA_OFFSET],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .compatible = "ti,edma3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .data = &ti_dma_offset[TI_XBAR_EDMA_OFFSET],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .compatible = "ti,edma3-tpcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .data = &ti_dma_offset[TI_XBAR_EDMA_OFFSET],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static inline void ti_dra7_xbar_reserve(int offset, int len, unsigned long *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) for (; len > 0; len--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) set_bit(offset + (len - 1), p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int ti_dra7_xbar_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct device_node *dma_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct ti_dra7_xbar_data *xbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 safe_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void __iomem *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) xbar = devm_kzalloc(&pdev->dev, sizeof(*xbar), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!xbar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dma_node = of_parse_phandle(node, "dma-masters", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!dma_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_err(&pdev->dev, "Can't get DMA master node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) match = of_match_node(ti_dra7_master_match, dma_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dev_err(&pdev->dev, "DMA master is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) of_node_put(dma_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (of_property_read_u32(dma_node, "dma-requests",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) &xbar->dma_requests)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "Missing XBAR output information, using %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) TI_DRA7_XBAR_OUTPUTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) xbar->dma_requests = TI_DRA7_XBAR_OUTPUTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) of_node_put(dma_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) xbar->dma_inuse = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) BITS_TO_LONGS(xbar->dma_requests),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) sizeof(unsigned long), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!xbar->dma_inuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (of_property_read_u32(node, "dma-requests", &xbar->xbar_requests)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "Missing XBAR input information, using %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) TI_DRA7_XBAR_INPUTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) xbar->xbar_requests = TI_DRA7_XBAR_INPUTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (!of_property_read_u32(node, "ti,dma-safe-map", &safe_val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) xbar->safe_val = (u16)safe_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) prop = of_find_property(node, "ti,reserved-dma-request-ranges", &sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) const char pname[] = "ti,reserved-dma-request-ranges";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 (*rsv_events)[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) size_t nelm = sz / sizeof(*rsv_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (!nelm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) rsv_events = kcalloc(nelm, sizeof(*rsv_events), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!rsv_events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = of_property_read_u32_array(node, pname, (u32 *)rsv_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) nelm * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) kfree(rsv_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) for (i = 0; i < nelm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ti_dra7_xbar_reserve(rsv_events[i][0], rsv_events[i][1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) xbar->dma_inuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) kfree(rsv_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) iomem = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (IS_ERR(iomem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return PTR_ERR(iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) xbar->iomem = iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) xbar->dmarouter.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) xbar->dmarouter.route_free = ti_dra7_xbar_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) xbar->dma_offset = *(u32 *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mutex_init(&xbar->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) platform_set_drvdata(pdev, xbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Reset the crossbar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) for (i = 0; i < xbar->dma_requests; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!test_bit(i, xbar->dma_inuse))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ti_dra7_xbar_write(xbar->iomem, i, xbar->safe_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = of_dma_router_register(node, ti_dra7_xbar_route_allocate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) &xbar->dmarouter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Restore the defaults for the crossbar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) for (i = 0; i < xbar->dma_requests; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!test_bit(i, xbar->dma_inuse))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ti_dra7_xbar_write(xbar->iomem, i, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int ti_dma_xbar_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) match = of_match_node(ti_dma_xbar_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (unlikely(!match))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) switch (*(u32 *)match->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case TI_XBAR_DRA7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = ti_dra7_xbar_probe(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case TI_XBAR_AM335X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = ti_am335x_xbar_probe(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_err(&pdev->dev, "Unsupported crossbar\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static struct platform_driver ti_dma_xbar_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .name = "ti-dma-crossbar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .of_match_table = of_match_ptr(ti_dma_xbar_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .probe = ti_dma_xbar_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int omap_dmaxbar_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return platform_driver_register(&ti_dma_xbar_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) arch_initcall(omap_dmaxbar_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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