^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ADMA driver for Nvidia's Tegra210 ADMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ADMA_CH_CMD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ADMA_CH_STATUS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ADMA_CH_STATUS_XFER_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ADMA_CH_STATUS_XFER_PAUSED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADMA_CH_INT_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADMA_CH_INT_STATUS_XFER_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADMA_CH_INT_CLEAR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADMA_CH_CTRL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADMA_CH_CTRL_DIR(val) (((val) & 0xf) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADMA_CH_CTRL_DIR_AHUB2MEM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADMA_CH_CTRL_DIR_MEM2AHUB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADMA_CH_CTRL_MODE_CONTINUOUS (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADMA_CH_CTRL_FLOWCTRL_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADMA_CH_CTRL_XFER_PAUSE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADMA_CH_CONFIG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADMA_CH_CONFIG_SRC_BUF(val) (((val) & 0x7) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADMA_CH_CONFIG_TRG_BUF(val) (((val) & 0x7) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADMA_CH_CONFIG_BURST_SIZE_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ADMA_CH_CONFIG_MAX_BURST_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADMA_CH_CONFIG_MAX_BUFS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) (reqs << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADMA_CH_FIFO_CTRL 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0x1f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADMA_CH_LOWER_SRC_ADDR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADMA_CH_LOWER_TRG_ADDR 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADMA_CH_TC 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADMA_CH_TC_COUNT_MASK 0x3ffffffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADMA_CH_XFER_STATUS 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADMA_CH_XFER_STATUS_COUNT_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ADMA_GLOBAL_CMD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ADMA_GLOBAL_SOFT_RESET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA_ADMA_BURST_COMPLETE_TIME 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA210_FIFO_CTRL_DEFAULT (TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA186_FIFO_CTRL_DEFAULT (TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct tegra_adma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * struct tegra_adma_chip_data - Tegra chip specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @global_reg_offset: Register offset of DMA global register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @global_int_clear: Register offset of DMA global interrupt clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @ch_req_rx_shift: Register offset for AHUB receive channel select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @ch_base_offset: Register offset of DMA channel registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @has_outstanding_reqs: If DMA channel can have outstanding requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @ch_fifo_ctrl: Default value for channel FIFO CTRL register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @ch_req_mask: Mask for Tx or Rx channel select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @ch_req_max: Maximum number of Tx or Rx channels available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @ch_reg_size: Size of DMA channel register space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @nr_channels: Number of DMA channels available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct tegra_adma_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int (*adma_get_burst_config)(unsigned int burst_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int global_reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int global_int_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int ch_req_tx_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int ch_req_rx_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int ch_base_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int ch_fifo_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int ch_req_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int ch_req_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int ch_reg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bool has_outstanding_reqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * struct tegra_adma_chan_regs - Tegra ADMA channel registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct tegra_adma_chan_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int trg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int fifo_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct tegra_adma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct virt_dma_desc vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct tegra_adma_chan_regs ch_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) size_t buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) size_t period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) size_t num_periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * struct tegra_adma_chan - Tegra ADMA channel information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct tegra_adma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct virt_dma_chan vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct tegra_adma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct tegra_adma *tdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __iomem *chan_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Slave channel configuration info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct dma_slave_config sconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) enum dma_transfer_direction sreq_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int sreq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool sreq_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct tegra_adma_chan_regs ch_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Transfer count and position info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int tx_buf_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int tx_buf_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * struct tegra_adma - Tegra ADMA controller information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct tegra_adma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct dma_device dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void __iomem *base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct clk *ahub_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned long rx_requests_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long tx_requests_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Used to store global command register state when suspending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int global_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) const struct tegra_adma_chip_data *cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Last member of the structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct tegra_adma_chan channels[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writel(val, tdc->chan_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline u32 tdma_ch_read(struct tegra_adma_chan *tdc, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return readl(tdc->chan_addr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return container_of(dc, struct tegra_adma_chan, vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static inline struct tegra_adma_desc *to_tegra_adma_desc(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct dma_async_tx_descriptor *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return container_of(td, struct tegra_adma_desc, vd.tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static inline struct device *tdc2dev(struct tegra_adma_chan *tdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return tdc->tdma->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void tegra_adma_desc_free(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) kfree(container_of(vd, struct tegra_adma_desc, vd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int tegra_adma_slave_config(struct dma_chan *dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct dma_slave_config *sconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int tegra_adma_init(struct tegra_adma *tdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Clear any interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tdma_write(tdma, tdma->cdata->global_int_clear, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Assert soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Wait for reset to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = readx_poll_timeout(readl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) tdma->base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tdma->cdata->global_reg_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ADMA_GLOBAL_SOFT_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) status, status == 0, 20, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Enable global ADMA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) tdma_write(tdma, ADMA_GLOBAL_CMD, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) enum dma_transfer_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct tegra_adma *tdma = tdc->tdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned int sreq_index = tdc->sreq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (tdc->sreq_reserved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return tdc->sreq_dir == direction ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (sreq_index > tdma->cdata->ch_req_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(tdma->dev, "invalid DMA request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev_err(tdma->dev, "DMA request reserved\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_err(tdma->dev, "DMA request reserved\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dma_chan_name(&tdc->vc.chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) tdc->sreq_dir = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) tdc->sreq_reserved = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void tegra_adma_request_free(struct tegra_adma_chan *tdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct tegra_adma *tdma = tdc->tdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!tdc->sreq_reserved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) switch (tdc->sreq_dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dma_chan_name(&tdc->vc.chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) tdc->sreq_reserved = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static u32 tegra_adma_irq_status(struct tegra_adma_chan *tdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 status = tdma_ch_read(tdc, ADMA_CH_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return status & ADMA_CH_INT_STATUS_XFER_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static u32 tegra_adma_irq_clear(struct tegra_adma_chan *tdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 status = tegra_adma_irq_status(tdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) tdma_ch_write(tdc, ADMA_CH_INT_CLEAR, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static void tegra_adma_stop(struct tegra_adma_chan *tdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Disable ADMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) tdma_ch_write(tdc, ADMA_CH_CMD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Clear interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) tegra_adma_irq_clear(tdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) status, !(status & ADMA_CH_STATUS_XFER_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 20, 10000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(tdc2dev(tdc), "unable to stop DMA channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) kfree(tdc->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) tdc->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void tegra_adma_start(struct tegra_adma_chan *tdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct tegra_adma_chan_regs *ch_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct tegra_adma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) list_del(&vd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) desc = to_tegra_adma_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ch_regs = &desc->ch_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) tdc->tx_buf_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tdc->tx_buf_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Start ADMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) tdma_ch_write(tdc, ADMA_CH_CMD, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) tdc->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static unsigned int tegra_adma_get_residue(struct tegra_adma_chan *tdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct tegra_adma_desc *desc = tdc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned int max = ADMA_CH_XFER_STATUS_COUNT_MASK + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int periods_remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * Handle wrap around of buffer count register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (pos < tdc->tx_buf_pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) tdc->tx_buf_count += pos - tdc->tx_buf_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) periods_remaining = tdc->tx_buf_count % desc->num_periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) tdc->tx_buf_pos = pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return desc->buf_len - (periods_remaining * desc->period_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static irqreturn_t tegra_adma_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct tegra_adma_chan *tdc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) spin_lock_irqsave(&tdc->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) status = tegra_adma_irq_clear(tdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (status == 0 || !tdc->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) spin_unlock_irqrestore(&tdc->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) vchan_cyclic_callback(&tdc->desc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) spin_unlock_irqrestore(&tdc->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void tegra_adma_issue_pending(struct dma_chan *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) spin_lock_irqsave(&tdc->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (vchan_issue_pending(&tdc->vc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!tdc->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) tegra_adma_start(tdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) spin_unlock_irqrestore(&tdc->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static bool tegra_adma_is_paused(struct tegra_adma_chan *tdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 csts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) csts = tdma_ch_read(tdc, ADMA_CH_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) csts &= ADMA_CH_STATUS_XFER_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return csts ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int tegra_adma_pause(struct dma_chan *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct tegra_adma_desc *desc = tdc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int dcnt = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) while (dcnt-- && !tegra_adma_is_paused(tdc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) udelay(TEGRA_ADMA_BURST_COMPLETE_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (dcnt < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_err(tdc2dev(tdc), "unable to pause DMA channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int tegra_adma_resume(struct dma_chan *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct tegra_adma_desc *desc = tdc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int tegra_adma_terminate_all(struct dma_chan *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) spin_lock_irqsave(&tdc->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (tdc->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) tegra_adma_stop(tdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) tegra_adma_request_free(tdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) vchan_get_all_descriptors(&tdc->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) spin_unlock_irqrestore(&tdc->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) vchan_dma_desc_free_list(&tdc->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static enum dma_status tegra_adma_tx_status(struct dma_chan *dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct tegra_adma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct virt_dma_desc *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) enum dma_status ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) unsigned int residual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret = dma_cookie_status(dc, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (ret == DMA_COMPLETE || !txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) spin_lock_irqsave(&tdc->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) vd = vchan_find_desc(&tdc->vc, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (vd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) desc = to_tegra_adma_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) residual = desc->ch_regs.tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) residual = tegra_adma_get_residue(tdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) residual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) spin_unlock_irqrestore(&tdc->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dma_set_residue(txstate, residual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static unsigned int tegra210_adma_get_burst_config(unsigned int burst_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return fls(burst_size) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static unsigned int tegra186_adma_get_burst_config(unsigned int burst_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct tegra_adma_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dma_addr_t buf_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) enum dma_transfer_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned int burst_size, adma_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) adma_dir = ADMA_CH_CTRL_DIR_MEM2AHUB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) burst_size = tdc->sconfig.dst_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) cdata->ch_req_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) cdata->ch_req_tx_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ch_regs->src_addr = buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) adma_dir = ADMA_CH_CTRL_DIR_AHUB2MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) burst_size = tdc->sconfig.src_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) cdata->ch_req_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) cdata->ch_req_rx_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ch_regs->trg_addr = buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ADMA_CH_CTRL_MODE_CONTINUOUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ADMA_CH_CTRL_FLOWCTRL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ch_regs->config |= cdata->adma_get_burst_config(burst_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (cdata->has_outstanding_reqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ch_regs->config |= TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ch_regs->fifo_ctrl = cdata->ch_fifo_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return tegra_adma_request_alloc(tdc, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static struct dma_async_tx_descriptor *tegra_adma_prep_dma_cyclic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) size_t period_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct tegra_adma_desc *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (!buf_len || !period_len || period_len > ADMA_CH_TC_COUNT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_err(tdc2dev(tdc), "invalid buffer/period len\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (buf_len % period_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!IS_ALIGNED(buf_addr, 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dev_err(tdc2dev(tdc), "invalid buffer alignment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) desc->buf_len = buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) desc->period_len = period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) desc->num_periods = buf_len / period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (tegra_adma_set_xfer_params(tdc, desc, buf_addr, direction)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return vchan_tx_prep(&tdc->vc, &desc->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int tegra_adma_alloc_chan_resources(struct dma_chan *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_err(tdc2dev(tdc), "failed to get interrupt for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dma_chan_name(dc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = pm_runtime_get_sync(tdc2dev(tdc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) pm_runtime_put_noidle(tdc2dev(tdc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) free_irq(tdc->irq, tdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dma_cookie_init(&tdc->vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static void tegra_adma_free_chan_resources(struct dma_chan *dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) tegra_adma_terminate_all(dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) vchan_free_chan_resources(&tdc->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) tasklet_kill(&tdc->vc.task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) free_irq(tdc->irq, tdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) pm_runtime_put(tdc2dev(tdc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) tdc->sreq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) tdc->sreq_dir = DMA_TRANS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct tegra_adma *tdma = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct tegra_adma_chan *tdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) unsigned int sreq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (dma_spec->args_count != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) sreq_index = dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (sreq_index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_err(tdma->dev, "DMA request must not be 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) chan = dma_get_any_slave_channel(&tdma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) tdc = to_tegra_adma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) tdc->sreq_index = sreq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct tegra_adma *tdma = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct tegra_adma_chan_regs *ch_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct tegra_adma_chan *tdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!tdma->global_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) for (i = 0; i < tdma->nr_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) tdc = &tdma->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ch_reg = &tdc->ch_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* skip if channel is not active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!ch_reg->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) clk_disable_unprepare(tdma->ahub_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static int __maybe_unused tegra_adma_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct tegra_adma *tdma = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct tegra_adma_chan_regs *ch_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct tegra_adma_chan *tdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ret = clk_prepare_enable(tdma->ahub_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev_err(dev, "ahub clk_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!tdma->global_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) for (i = 0; i < tdma->nr_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) tdc = &tdma->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ch_reg = &tdc->ch_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* skip if channel was not active earlier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (!ch_reg->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const struct tegra_adma_chip_data tegra210_chip_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .adma_get_burst_config = tegra210_adma_get_burst_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .global_reg_offset = 0xc00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .global_int_clear = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .ch_req_tx_shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .ch_req_rx_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .ch_base_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .has_outstanding_reqs = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .ch_fifo_ctrl = TEGRA210_FIFO_CTRL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .ch_req_mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .ch_req_max = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .ch_reg_size = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .nr_channels = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static const struct tegra_adma_chip_data tegra186_chip_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .adma_get_burst_config = tegra186_adma_get_burst_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .global_reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .global_int_clear = 0x402c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .ch_req_tx_shift = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .ch_req_rx_shift = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .ch_base_offset = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .has_outstanding_reqs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .ch_fifo_ctrl = TEGRA186_FIFO_CTRL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .ch_req_mask = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .ch_req_max = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .ch_reg_size = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .nr_channels = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const struct of_device_id tegra_adma_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) MODULE_DEVICE_TABLE(of, tegra_adma_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int tegra_adma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) const struct tegra_adma_chip_data *cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct tegra_adma *tdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) cdata = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (!cdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_err(&pdev->dev, "device match data not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) tdma = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct_size(tdma, channels, cdata->nr_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (!tdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) tdma->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) tdma->cdata = cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) tdma->nr_channels = cdata->nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) platform_set_drvdata(pdev, tdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (IS_ERR(tdma->base_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return PTR_ERR(tdma->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (IS_ERR(tdma->ahub_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_err(&pdev->dev, "Error: Missing ahub controller clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return PTR_ERR(tdma->ahub_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) INIT_LIST_HEAD(&tdma->dma_dev.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) for (i = 0; i < tdma->nr_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct tegra_adma_chan *tdc = &tdma->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) + (cdata->ch_reg_size * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) tdc->irq = of_irq_get(pdev->dev.of_node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (tdc->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ret = tdc->irq ?: -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) goto irq_dispose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) vchan_init(&tdc->vc, &tdma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) tdc->vc.desc_free = tegra_adma_desc_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) tdc->tdma = tdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ret = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) goto rpm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret = tegra_adma_init(tdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) goto rpm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) tdma->dma_dev.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) tdma->dma_dev.device_alloc_chan_resources =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) tegra_adma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) tdma->dma_dev.device_free_chan_resources =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) tegra_adma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) tdma->dma_dev.device_config = tegra_adma_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) tdma->dma_dev.device_tx_status = tegra_adma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) tdma->dma_dev.device_pause = tegra_adma_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) tdma->dma_dev.device_resume = tegra_adma_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ret = dma_async_device_register(&tdma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) goto rpm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ret = of_dma_controller_register(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) tegra_dma_of_xlate, tdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) goto dma_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) tdma->nr_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dma_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dma_async_device_unregister(&tdma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) rpm_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) rpm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) irq_dispose:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) irq_dispose_mapping(tdma->channels[i].irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static int tegra_adma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct tegra_adma *tdma = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) of_dma_controller_free(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) dma_async_device_unregister(&tdma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) for (i = 0; i < tdma->nr_channels; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) irq_dispose_mapping(tdma->channels[i].irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static const struct dev_pm_ops tegra_adma_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) SET_RUNTIME_PM_OPS(tegra_adma_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) tegra_adma_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static struct platform_driver tegra_admac_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .name = "tegra-adma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .pm = &tegra_adma_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .of_match_table = tegra_adma_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .probe = tegra_adma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .remove = tegra_adma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) module_platform_driver(tegra_admac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) MODULE_ALIAS("platform:tegra210-adma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) MODULE_DESCRIPTION("NVIDIA Tegra ADMA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) MODULE_AUTHOR("Dara Ramesh <dramesh@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) MODULE_AUTHOR("Jon Hunter <jonathanh@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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