^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Sugar <shuge@allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Common registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DMA_IRQ_EN(x) ((x) * 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DMA_IRQ_HALF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DMA_IRQ_PKG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DMA_IRQ_QUEUE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DMA_IRQ_CHAN_NR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DMA_IRQ_CHAN_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DMA_IRQ_STAT(x) ((x) * 0x04 + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DMA_STAT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DMA_MAX_CHANNELS (DMA_IRQ_CHAN_NR * 0x10 / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * sun8i specific registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUN8I_DMA_GATE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SUN8I_DMA_GATE_ENABLE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SUNXI_H3_SECURE_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SUNXI_H3_DMA_GATE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SUNXI_H3_DMA_GATE_ENABLE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Channels specific registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DMA_CHAN_ENABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DMA_CHAN_ENABLE_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DMA_CHAN_ENABLE_STOP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DMA_CHAN_PAUSE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DMA_CHAN_PAUSE_PAUSE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DMA_CHAN_PAUSE_RESUME 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DMA_CHAN_LLI_ADDR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DMA_CHAN_CUR_CFG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DMA_CHAN_MAX_DRQ_A31 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DMA_CHAN_MAX_DRQ_H6 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DMA_CHAN_CFG_SRC_DRQ_H6(x) ((x) & DMA_CHAN_MAX_DRQ_H6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DMA_CHAN_CFG_SRC_MODE_A31(x) (((x) & 0x1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DMA_CHAN_CFG_SRC_MODE_H6(x) (((x) & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DMA_CHAN_CFG_DST_DRQ_H6(x) (DMA_CHAN_CFG_SRC_DRQ_H6(x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DMA_CHAN_CFG_DST_MODE_A31(x) (DMA_CHAN_CFG_SRC_MODE_A31(x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DMA_CHAN_CFG_DST_MODE_H6(x) (DMA_CHAN_CFG_SRC_MODE_H6(x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DMA_CHAN_CUR_SRC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DMA_CHAN_CUR_DST 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DMA_CHAN_CUR_CNT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DMA_CHAN_CUR_PARA 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Various hardware related defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LLI_LAST_ITEM 0xfffff800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define NORMAL_WAIT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DRQ_SDRAM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LINEAR_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IO_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* forward declaration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct sun6i_dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Hardware channels / ports representation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * The hardware is used in several SoCs, with differing numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * of channels and endpoints. This structure ties those numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * to a certain compatible string.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct sun6i_dma_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 nr_max_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 nr_max_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 nr_max_vchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * In the datasheets/user manuals of newer Allwinner SoCs, a special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * bit (bit 2 at register 0x20) is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * It's named "DMA MCLK interface circuit auto gating bit" in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * documents, and the footnote of this register says that this bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * should be set up when initializing the DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Allwinner A23/A33 user manuals do not have this bit documented,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * however these SoCs really have and need this bit, as seen in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * BSP kernel source code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void (*clock_autogate_enable)(struct sun6i_dma_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 src_burst_lengths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 dst_burst_lengths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 src_addr_widths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 dst_addr_widths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bool has_mbus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Hardware representation of the LLI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * The hardware will be fed the physical address of this structure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * and read its content in order to start the transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct sun6i_dma_lli {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 para;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 p_lli_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * This field is not used by the DMA controller, but will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * used by the CPU to go through the list (mostly for dumping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * or freeing it).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct sun6i_dma_lli *v_lli_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct sun6i_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct virt_dma_desc vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dma_addr_t p_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct sun6i_dma_lli *v_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct sun6i_pchan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct sun6i_vchan *vchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct sun6i_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct sun6i_desc *done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct sun6i_vchan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct virt_dma_chan vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct sun6i_pchan *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) bool cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct sun6i_dma_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct dma_device slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct clk *clk_mbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct tasklet_struct task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) atomic_t tasklet_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct list_head pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct dma_pool *pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct sun6i_pchan *pchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct sun6i_vchan *vchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) const struct sun6i_dma_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 num_pchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 num_vchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 max_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct device *chan2dev(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return &chan->dev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return container_of(d, struct sun6i_dma_dev, slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static inline struct sun6i_vchan *to_sun6i_vchan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return container_of(chan, struct sun6i_vchan, vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static inline struct sun6i_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) to_sun6i_desc(struct dma_async_tx_descriptor *tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return container_of(tx, struct sun6i_desc, vd.tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_dbg(sdev->slave.dev, "Common register:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "\tmask0(%04x): 0x%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "\tmask1(%04x): 0x%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "\tpend0(%04x): 0x%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "\tpend1(%04x): 0x%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "\tstats(%04x): 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) DMA_STAT, readl(sdev->base + DMA_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct sun6i_pchan *pchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) phys_addr_t reg = virt_to_phys(pchan->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_dbg(sdev->slave.dev, "Chan %d reg: %pa\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "\t___en(%04x): \t0x%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "\tpause(%04x): \t0x%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "\tstart(%04x): \t0x%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "\t__cfg(%04x): \t0x%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "\t__src(%04x): \t0x%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "\t__dst(%04x): \t0x%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "\tcount(%04x): \t0x%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "\t_para(%04x): \t0x%08x\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pchan->idx, ®,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DMA_CHAN_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) readl(pchan->base + DMA_CHAN_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DMA_CHAN_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) readl(pchan->base + DMA_CHAN_PAUSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DMA_CHAN_LLI_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) readl(pchan->base + DMA_CHAN_LLI_ADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) DMA_CHAN_CUR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) readl(pchan->base + DMA_CHAN_CUR_CFG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) DMA_CHAN_CUR_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) readl(pchan->base + DMA_CHAN_CUR_SRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DMA_CHAN_CUR_DST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) readl(pchan->base + DMA_CHAN_CUR_DST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DMA_CHAN_CUR_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) readl(pchan->base + DMA_CHAN_CUR_CNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DMA_CHAN_CUR_PARA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) readl(pchan->base + DMA_CHAN_CUR_PARA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static inline s8 convert_burst(u32 maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) switch (maxburst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ilog2(addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static void sun6i_enable_clock_autogate_a23(struct sun6i_dma_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) writel(SUN8I_DMA_GATE_ENABLE, sdev->base + SUN8I_DMA_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void sun6i_enable_clock_autogate_h3(struct sun6i_dma_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) writel(SUNXI_H3_DMA_GATE_ENABLE, sdev->base + SUNXI_H3_DMA_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void sun6i_set_burst_length_a31(u32 *p_cfg, s8 src_burst, s8 dst_burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) *p_cfg |= DMA_CHAN_CFG_SRC_BURST_A31(src_burst) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) DMA_CHAN_CFG_DST_BURST_A31(dst_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void sun6i_set_burst_length_h3(u32 *p_cfg, s8 src_burst, s8 dst_burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *p_cfg |= DMA_CHAN_CFG_SRC_BURST_H3(src_burst) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) DMA_CHAN_CFG_DST_BURST_H3(dst_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_A31(src_drq) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) DMA_CHAN_CFG_DST_DRQ_A31(dst_drq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void sun6i_set_drq_h6(u32 *p_cfg, s8 src_drq, s8 dst_drq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_H6(src_drq) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) DMA_CHAN_CFG_DST_DRQ_H6(dst_drq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) DMA_CHAN_CFG_DST_MODE_A31(dst_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *p_cfg |= DMA_CHAN_CFG_SRC_MODE_H6(src_mode) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) DMA_CHAN_CFG_DST_MODE_H6(dst_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct sun6i_desc *txd = pchan->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct sun6i_dma_lli *lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) size_t bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dma_addr_t pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pos = readl(pchan->base + DMA_CHAN_LLI_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) bytes = readl(pchan->base + DMA_CHAN_CUR_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (pos == LLI_LAST_ITEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) for (lli = txd->v_lli; lli; lli = lli->v_lli_next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (lli->p_lli_next == pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (lli = lli->v_lli_next; lli; lli = lli->v_lli_next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) bytes += lli->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct sun6i_dma_lli *next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dma_addr_t next_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct sun6i_desc *txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if ((!prev && !txd) || !next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!prev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) txd->p_lli = next_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) txd->v_lli = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) prev->p_lli_next = next_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) prev->v_lli_next = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) next->p_lli_next = LLI_LAST_ITEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) next->v_lli_next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct sun6i_dma_lli *lli)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) phys_addr_t p_lli = virt_to_phys(lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_dbg(chan2dev(&vchan->vc.chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) "\n\tdesc: p - %pa v - 0x%p\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) &p_lli, lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) lli->cfg, lli->src, lli->dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) lli->len, lli->para, lli->p_lli_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void sun6i_dma_free_desc(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct sun6i_desc *txd = to_sun6i_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct sun6i_dma_lli *v_lli, *v_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dma_addr_t p_lli, p_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (unlikely(!txd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) p_lli = txd->p_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) v_lli = txd->v_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) while (v_lli) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) v_next = v_lli->v_lli_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) p_next = v_lli->p_lli_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dma_pool_free(sdev->pool, v_lli, p_lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) v_lli = v_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) p_lli = p_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) kfree(txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int sun6i_dma_start_desc(struct sun6i_vchan *vchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct virt_dma_desc *desc = vchan_next_desc(&vchan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct sun6i_pchan *pchan = vchan->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 irq_val, irq_reg, irq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!pchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pchan->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pchan->done = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) list_del(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pchan->desc = to_sun6i_desc(&desc->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) pchan->done = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) sun6i_dma_dump_lli(vchan, pchan->desc->v_lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) irq_reg = pchan->idx / DMA_IRQ_CHAN_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) irq_offset = pchan->idx % DMA_IRQ_CHAN_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) irq_val &= ~((DMA_IRQ_HALF | DMA_IRQ_PKG | DMA_IRQ_QUEUE) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) (irq_offset * DMA_IRQ_CHAN_WIDTH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) irq_val |= vchan->irq_type << (irq_offset * DMA_IRQ_CHAN_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) sun6i_dma_dump_com_regs(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) sun6i_dma_dump_chan_regs(sdev, pchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void sun6i_dma_tasklet(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct sun6i_dma_dev *sdev = from_tasklet(sdev, t, task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct sun6i_vchan *vchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct sun6i_pchan *pchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned int pchan_alloc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) unsigned int pchan_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) spin_lock_irq(&vchan->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pchan = vchan->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (pchan && pchan->done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (sun6i_dma_start_desc(vchan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * No current txd associated with this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_dbg(sdev->slave.dev, "pchan %u: free\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pchan->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Mark this channel free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) vchan->phy = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pchan->vchan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) spin_unlock_irq(&vchan->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) spin_lock_irq(&sdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) for (pchan_idx = 0; pchan_idx < sdev->num_pchans; pchan_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pchan = &sdev->pchans[pchan_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (pchan->vchan || list_empty(&sdev->pending))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) vchan = list_first_entry(&sdev->pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct sun6i_vchan, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Remove from pending channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) list_del_init(&vchan->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pchan_alloc |= BIT(pchan_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Mark this channel allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pchan->vchan = vchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) vchan->phy = pchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dev_dbg(sdev->slave.dev, "pchan %u: alloc vchan %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) pchan->idx, &vchan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) spin_unlock_irq(&sdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) for (pchan_idx = 0; pchan_idx < sdev->num_pchans; pchan_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!(pchan_alloc & BIT(pchan_idx)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pchan = sdev->pchans + pchan_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) vchan = pchan->vchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (vchan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) spin_lock_irq(&vchan->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) sun6i_dma_start_desc(vchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) spin_unlock_irq(&vchan->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct sun6i_dma_dev *sdev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct sun6i_vchan *vchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct sun6i_pchan *pchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int i, j, ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) for (i = 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) status = readl(sdev->base + DMA_IRQ_STAT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) i ? "high" : "low", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) writel(status, sdev->base + DMA_IRQ_STAT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pchan = sdev->pchans + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) vchan = pchan->vchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (vchan && (status & vchan->irq_type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (vchan->cyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) vchan_cyclic_callback(&pchan->desc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) spin_lock(&vchan->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) vchan_cookie_complete(&pchan->desc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pchan->done = pchan->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) spin_unlock(&vchan->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) status = status >> DMA_IRQ_CHAN_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (!atomic_read(&sdev->tasklet_shutdown))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) tasklet_schedule(&sdev->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int set_config(struct sun6i_dma_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct dma_slave_config *sconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u32 *p_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) enum dma_slave_buswidth src_addr_width, dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u32 src_maxburst, dst_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) s8 src_width, dst_width, src_burst, dst_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) src_addr_width = sconfig->src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dst_addr_width = sconfig->dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) src_maxburst = sconfig->src_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dst_maxburst = sconfig->dst_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) src_maxburst = src_maxburst ? src_maxburst : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dst_maxburst = dst_maxburst ? dst_maxburst : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!(BIT(src_addr_width) & sdev->slave.src_addr_widths))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (!(BIT(dst_addr_width) & sdev->slave.dst_addr_widths))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (!(BIT(src_maxburst) & sdev->cfg->src_burst_lengths))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (!(BIT(dst_maxburst) & sdev->cfg->dst_burst_lengths))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) src_width = convert_buswidth(src_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dst_width = convert_buswidth(dst_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dst_burst = convert_burst(dst_maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) src_burst = convert_burst(src_maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) *p_cfg = DMA_CHAN_CFG_SRC_WIDTH(src_width) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) DMA_CHAN_CFG_DST_WIDTH(dst_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) sdev->cfg->set_burst_length(p_cfg, src_burst, dst_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct sun6i_dma_lli *v_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct sun6i_desc *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dma_addr_t p_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) s8 burst, width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dev_dbg(chan2dev(chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (!v_lli) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) goto err_txd_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) v_lli->src = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) v_lli->dst = dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) v_lli->len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) v_lli->para = NORMAL_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) burst = convert_burst(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) v_lli->cfg = DMA_CHAN_CFG_SRC_WIDTH(width) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) DMA_CHAN_CFG_DST_WIDTH(width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, LINEAR_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) sun6i_dma_dump_lli(vchan, v_lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) err_txd_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) kfree(txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct dma_chan *chan, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned int sg_len, enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct dma_slave_config *sconfig = &vchan->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct sun6i_dma_lli *v_lli, *prev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct sun6i_desc *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dma_addr_t p_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 lli_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (!sgl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ret = set_config(sdev, sconfig, dir, &lli_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_err(chan2dev(chan), "Invalid DMA configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) for_each_sg(sgl, sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (!v_lli)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) goto err_lli_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) v_lli->len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) v_lli->para = NORMAL_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) v_lli->src = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) v_lli->dst = sconfig->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) v_lli->cfg = lli_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dev_dbg(chan2dev(chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) __func__, vchan->vc.chan.chan_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) &sconfig->dst_addr, &sg_dma_address(sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) sg_dma_len(sg), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) v_lli->src = sconfig->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) v_lli->dst = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) v_lli->cfg = lli_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev_dbg(chan2dev(chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) __func__, vchan->vc.chan.chan_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) &sg_dma_address(sg), &sconfig->src_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) sg_dma_len(sg), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) sun6i_dma_dump_lli(vchan, prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) err_lli_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dma_pool_free(sdev->pool, prev, virt_to_phys(prev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) kfree(txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dma_addr_t buf_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) size_t buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) size_t period_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct dma_slave_config *sconfig = &vchan->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct sun6i_dma_lli *v_lli, *prev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct sun6i_desc *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dma_addr_t p_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u32 lli_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) unsigned int i, periods = buf_len / period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret = set_config(sdev, sconfig, dir, &lli_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dev_err(chan2dev(chan), "Invalid DMA configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) for (i = 0; i < periods; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!v_lli) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) goto err_lli_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) v_lli->len = period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) v_lli->para = NORMAL_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) v_lli->src = buf_addr + period_len * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) v_lli->dst = sconfig->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) v_lli->cfg = lli_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) v_lli->src = sconfig->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) v_lli->dst = buf_addr + period_len * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) v_lli->cfg = lli_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) prev->p_lli_next = txd->p_lli; /* cyclic list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) vchan->cyclic = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) err_lli_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dma_pool_free(sdev->pool, prev, virt_to_phys(prev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) kfree(txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int sun6i_dma_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct dma_slave_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) memcpy(&vchan->cfg, config, sizeof(*config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int sun6i_dma_pause(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct sun6i_pchan *pchan = vchan->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (pchan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) writel(DMA_CHAN_PAUSE_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) pchan->base + DMA_CHAN_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) spin_lock(&sdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) list_del_init(&vchan->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) spin_unlock(&sdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int sun6i_dma_resume(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct sun6i_pchan *pchan = vchan->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) spin_lock_irqsave(&vchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (pchan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) writel(DMA_CHAN_PAUSE_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) pchan->base + DMA_CHAN_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) } else if (!list_empty(&vchan->vc.desc_issued)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) spin_lock(&sdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) list_add_tail(&vchan->node, &sdev->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) spin_unlock(&sdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) spin_unlock_irqrestore(&vchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int sun6i_dma_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct sun6i_pchan *pchan = vchan->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) spin_lock(&sdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) list_del_init(&vchan->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) spin_unlock(&sdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) spin_lock_irqsave(&vchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (vchan->cyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) vchan->cyclic = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (pchan && pchan->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct virt_dma_desc *vd = &pchan->desc->vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct virt_dma_chan *vc = &vchan->vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) list_add_tail(&vd->node, &vc->desc_completed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) vchan_get_all_descriptors(&vchan->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (pchan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) vchan->phy = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) pchan->vchan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) pchan->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) pchan->done = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) spin_unlock_irqrestore(&vchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) vchan_dma_desc_free_list(&vchan->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct dma_tx_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct sun6i_pchan *pchan = vchan->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct sun6i_dma_lli *lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct virt_dma_desc *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct sun6i_desc *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) enum dma_status ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) size_t bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ret = dma_cookie_status(chan, cookie, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (ret == DMA_COMPLETE || !state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) spin_lock_irqsave(&vchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) vd = vchan_find_desc(&vchan->vc, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) txd = to_sun6i_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (vd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) for (lli = txd->v_lli; lli != NULL; lli = lli->v_lli_next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) bytes += lli->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) } else if (!pchan || !pchan->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) bytes = sun6i_get_chan_size(pchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) spin_unlock_irqrestore(&vchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) dma_set_residue(state, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static void sun6i_dma_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) spin_lock_irqsave(&vchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (vchan_issue_pending(&vchan->vc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) spin_lock(&sdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (!vchan->phy && list_empty(&vchan->node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) list_add_tail(&vchan->node, &sdev->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) tasklet_schedule(&sdev->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) dev_dbg(chan2dev(chan), "vchan %p: issued\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) &vchan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) spin_unlock(&sdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) &vchan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) spin_unlock_irqrestore(&vchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static void sun6i_dma_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) spin_lock_irqsave(&sdev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) list_del_init(&vchan->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) spin_unlock_irqrestore(&sdev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) vchan_free_chan_resources(&vchan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct sun6i_dma_dev *sdev = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct sun6i_vchan *vchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u8 port = dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (port > sdev->max_request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) chan = dma_get_any_slave_channel(&sdev->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) vchan = to_sun6i_vchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) vchan->port = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* Disable all interrupts from DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) writel(0, sdev->base + DMA_IRQ_EN(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) writel(0, sdev->base + DMA_IRQ_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* Prevent spurious interrupts from scheduling the tasklet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) atomic_inc(&sdev->tasklet_shutdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* Make sure we won't have any further interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) devm_free_irq(sdev->slave.dev, sdev->irq, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* Actually prevent the tasklet from being scheduled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) tasklet_kill(&sdev->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) for (i = 0; i < sdev->num_vchans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct sun6i_vchan *vchan = &sdev->vchans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) list_del(&vchan->vc.chan.device_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) tasklet_kill(&vchan->vc.task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * For A31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * There's 16 physical channels that can work in parallel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * However we have 30 different endpoints for our requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * Since the channels are able to handle only an unidirectional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * transfer, we need to allocate more virtual channels so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * everyone can grab one channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * Some devices can't work in both direction (mostly because it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * wouldn't make sense), so we have a bit fewer virtual channels than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * 2 channels per endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static struct sun6i_dma_config sun6i_a31_dma_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .nr_max_channels = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .nr_max_requests = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .nr_max_vchans = 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .set_burst_length = sun6i_set_burst_length_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .set_drq = sun6i_set_drq_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .set_mode = sun6i_set_mode_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .src_burst_lengths = BIT(1) | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .dst_burst_lengths = BIT(1) | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * The A23 only has 8 physical channels, a maximum DRQ port id of 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * and a total of 37 usable source and destination endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static struct sun6i_dma_config sun8i_a23_dma_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .nr_max_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .nr_max_requests = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .nr_max_vchans = 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .set_burst_length = sun6i_set_burst_length_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .set_drq = sun6i_set_drq_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .set_mode = sun6i_set_mode_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .src_burst_lengths = BIT(1) | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .dst_burst_lengths = BIT(1) | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static struct sun6i_dma_config sun8i_a83t_dma_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .nr_max_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .nr_max_requests = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .nr_max_vchans = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .set_burst_length = sun6i_set_burst_length_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .set_drq = sun6i_set_drq_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .set_mode = sun6i_set_mode_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .src_burst_lengths = BIT(1) | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .dst_burst_lengths = BIT(1) | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * The H3 has 12 physical channels, a maximum DRQ port id of 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * and a total of 34 usable source and destination endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * It also supports additional burst lengths and bus widths,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * and the burst length fields have different offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static struct sun6i_dma_config sun8i_h3_dma_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .nr_max_channels = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .nr_max_requests = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .nr_max_vchans = 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .set_burst_length = sun6i_set_burst_length_h3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .set_drq = sun6i_set_drq_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .set_mode = sun6i_set_mode_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * The A64 binding uses the number of dma channels from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * device tree node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static struct sun6i_dma_config sun50i_a64_dma_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .set_burst_length = sun6i_set_burst_length_h3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .set_drq = sun6i_set_drq_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .set_mode = sun6i_set_mode_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * The H6 binding uses the number of dma channels from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * device tree node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static struct sun6i_dma_config sun50i_h6_dma_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .set_burst_length = sun6i_set_burst_length_h3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .set_drq = sun6i_set_drq_h6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .set_mode = sun6i_set_mode_h6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .has_mbus_clk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * The V3s have only 8 physical channels, a maximum DRQ port id of 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * and a total of 24 usable source and destination endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static struct sun6i_dma_config sun8i_v3s_dma_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .nr_max_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .nr_max_requests = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .nr_max_vchans = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .set_burst_length = sun6i_set_burst_length_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .set_drq = sun6i_set_drq_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .set_mode = sun6i_set_mode_a31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .src_burst_lengths = BIT(1) | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .dst_burst_lengths = BIT(1) | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static const struct of_device_id sun6i_dma_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) MODULE_DEVICE_TABLE(of, sun6i_dma_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static int sun6i_dma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct sun6i_dma_dev *sdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (!sdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) sdc->cfg = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (!sdc->cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) sdc->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (IS_ERR(sdc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return PTR_ERR(sdc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) sdc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (sdc->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return sdc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) sdc->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (IS_ERR(sdc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_err(&pdev->dev, "No clock specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return PTR_ERR(sdc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (sdc->cfg->has_mbus_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) sdc->clk_mbus = devm_clk_get(&pdev->dev, "mbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (IS_ERR(sdc->clk_mbus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) dev_err(&pdev->dev, "No mbus clock specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return PTR_ERR(sdc->clk_mbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) sdc->rstc = devm_reset_control_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (IS_ERR(sdc->rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dev_err(&pdev->dev, "No reset controller specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return PTR_ERR(sdc->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) sdc->pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) sizeof(struct sun6i_dma_lli), 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (!sdc->pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) platform_set_drvdata(pdev, sdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) INIT_LIST_HEAD(&sdc->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) spin_lock_init(&sdc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) dma_cap_set(DMA_CYCLIC, sdc->slave.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) INIT_LIST_HEAD(&sdc->slave.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) sdc->slave.device_free_chan_resources = sun6i_dma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) sdc->slave.device_tx_status = sun6i_dma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) sdc->slave.device_issue_pending = sun6i_dma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) sdc->slave.device_prep_slave_sg = sun6i_dma_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) sdc->slave.device_prep_dma_memcpy = sun6i_dma_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) sdc->slave.device_prep_dma_cyclic = sun6i_dma_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) sdc->slave.copy_align = DMAENGINE_ALIGN_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) sdc->slave.device_config = sun6i_dma_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) sdc->slave.device_pause = sun6i_dma_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) sdc->slave.device_resume = sun6i_dma_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) sdc->slave.device_terminate_all = sun6i_dma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) sdc->slave.src_addr_widths = sdc->cfg->src_addr_widths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) sdc->slave.dst_addr_widths = sdc->cfg->dst_addr_widths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) sdc->slave.directions = BIT(DMA_DEV_TO_MEM) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) sdc->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) sdc->slave.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) sdc->num_pchans = sdc->cfg->nr_max_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) sdc->num_vchans = sdc->cfg->nr_max_vchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) sdc->max_request = sdc->cfg->nr_max_requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ret = of_property_read_u32(np, "dma-channels", &sdc->num_pchans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (ret && !sdc->num_pchans) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) dev_err(&pdev->dev, "Can't get dma-channels.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) ret = of_property_read_u32(np, "dma-requests", &sdc->max_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (ret && !sdc->max_request) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) dev_info(&pdev->dev, "Missing dma-requests, using %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) DMA_CHAN_MAX_DRQ_A31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) sdc->max_request = DMA_CHAN_MAX_DRQ_A31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * If the number of vchans is not specified, derive it from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * highest port number, at most one channel per port and direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (!sdc->num_vchans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) sdc->num_vchans = 2 * (sdc->max_request + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) sdc->pchans = devm_kcalloc(&pdev->dev, sdc->num_pchans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) sizeof(struct sun6i_pchan), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (!sdc->pchans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) sdc->vchans = devm_kcalloc(&pdev->dev, sdc->num_vchans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) sizeof(struct sun6i_vchan), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (!sdc->vchans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) tasklet_setup(&sdc->task, sun6i_dma_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) for (i = 0; i < sdc->num_pchans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) struct sun6i_pchan *pchan = &sdc->pchans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) pchan->idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) pchan->base = sdc->base + 0x100 + i * 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) for (i = 0; i < sdc->num_vchans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) struct sun6i_vchan *vchan = &sdc->vchans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) INIT_LIST_HEAD(&vchan->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) vchan->vc.desc_free = sun6i_dma_free_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) vchan_init(&vchan->vc, &sdc->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ret = reset_control_deassert(sdc->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) dev_err(&pdev->dev, "Couldn't deassert the device from reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) goto err_chan_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ret = clk_prepare_enable(sdc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) dev_err(&pdev->dev, "Couldn't enable the clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) goto err_reset_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (sdc->cfg->has_mbus_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ret = clk_prepare_enable(sdc->clk_mbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dev_err(&pdev->dev, "Couldn't enable mbus clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) dev_name(&pdev->dev), sdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) dev_err(&pdev->dev, "Cannot request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) goto err_mbus_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ret = dma_async_device_register(&sdc->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) dev_warn(&pdev->dev, "Failed to register DMA engine device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) goto err_irq_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) ret = of_dma_controller_register(pdev->dev.of_node, sun6i_dma_of_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) sdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) dev_err(&pdev->dev, "of_dma_controller_register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) goto err_dma_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (sdc->cfg->clock_autogate_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) sdc->cfg->clock_autogate_enable(sdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) err_dma_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dma_async_device_unregister(&sdc->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) err_irq_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) sun6i_kill_tasklet(sdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) err_mbus_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) clk_disable_unprepare(sdc->clk_mbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) clk_disable_unprepare(sdc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) err_reset_assert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) reset_control_assert(sdc->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) err_chan_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) sun6i_dma_free(sdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static int sun6i_dma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) struct sun6i_dma_dev *sdc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) of_dma_controller_free(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) dma_async_device_unregister(&sdc->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) sun6i_kill_tasklet(sdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) clk_disable_unprepare(sdc->clk_mbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) clk_disable_unprepare(sdc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) reset_control_assert(sdc->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) sun6i_dma_free(sdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static struct platform_driver sun6i_dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .probe = sun6i_dma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .remove = sun6i_dma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .name = "sun6i-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .of_match_table = sun6i_dma_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) module_platform_driver(sun6i_dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) MODULE_DESCRIPTION("Allwinner A31 DMA Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) MODULE_AUTHOR("Sugar <shuge@allwinnertech.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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