^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for STM32 DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Inspired by dma-jz4740.c and tegra20-apb-dma.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) M'boumba Cedric Madianga 2015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define STM32_DMA_LISR 0x0000 /* DMA Low Int Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define STM32_DMA_MASKI (STM32_DMA_TCI \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) | STM32_DMA_TEI \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) | STM32_DMA_DMEI \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) | STM32_DMA_FEI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* DMA Stream x Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STM32_DMA_SCR_REQ(n) ((n & 0x7) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STM32_DMA_SCR_MBURST_MASK GENMASK(24, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STM32_DMA_SCR_MBURST(n) ((n & 0x3) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STM32_DMA_SCR_PBURST_MASK GENMASK(22, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STM32_DMA_SCR_PBURST(n) ((n & 0x3) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STM32_DMA_SCR_PL_MASK GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define STM32_DMA_SCR_PL(n) ((n & 0x3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STM32_DMA_SCR_MSIZE_MASK GENMASK(14, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define STM32_DMA_SCR_MSIZE(n) ((n & 0x3) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define STM32_DMA_SCR_PSIZE_MASK GENMASK(12, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STM32_DMA_SCR_PSIZE(n) ((n & 0x3) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STM32_DMA_SCR_PSIZE_GET(n) ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define STM32_DMA_SCR_DIR_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STM32_DMA_SCR_DIR(n) ((n & 0x3) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STM32_DMA_SCR_CT BIT(19) /* Target in double buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STM32_DMA_SCR_PINCOS BIT(15) /* Peripheral inc offset size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define STM32_DMA_SCR_MINC BIT(10) /* Memory increment mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define STM32_DMA_SCR_CFG_MASK (STM32_DMA_SCR_PINC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) | STM32_DMA_SCR_MINC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) | STM32_DMA_SCR_PINCOS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) | STM32_DMA_SCR_PL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STM32_DMA_SCR_IRQ_MASK (STM32_DMA_SCR_TCIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) | STM32_DMA_SCR_TEIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) | STM32_DMA_SCR_DMEIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* DMA Stream x number of data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define STM32_DMA_SNDTR(x) (0x0014 + 0x18 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* DMA stream peripheral address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define STM32_DMA_SPAR(x) (0x0018 + 0x18 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* DMA stream x memory 0 address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define STM32_DMA_SM0AR(x) (0x001c + 0x18 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* DMA stream x memory 1 address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STM32_DMA_SM1AR(x) (0x0020 + 0x18 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* DMA stream x FIFO control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define STM32_DMA_SFCR(x) (0x0024 + 0x18 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define STM32_DMA_SFCR_FTH_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define STM32_DMA_SFCR_FTH(n) (n & STM32_DMA_SFCR_FTH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define STM32_DMA_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define STM32_DMA_SFCR_DMDIS BIT(2) /* Direct mode disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define STM32_DMA_SFCR_MASK (STM32_DMA_SFCR_FEIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) | STM32_DMA_SFCR_DMDIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* DMA direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define STM32_DMA_DEV_TO_MEM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define STM32_DMA_MEM_TO_DEV 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define STM32_DMA_MEM_TO_MEM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* DMA priority level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define STM32_DMA_PRIORITY_LOW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define STM32_DMA_PRIORITY_MEDIUM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define STM32_DMA_PRIORITY_HIGH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define STM32_DMA_PRIORITY_VERY_HIGH 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* DMA FIFO threshold selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define STM32_DMA_FIFO_THRESHOLD_HALFFULL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define STM32_DMA_FIFO_THRESHOLD_FULL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define STM32_DMA_FIFO_THRESHOLD_NONE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define STM32_DMA_MAX_DATA_ITEMS 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * gather at boundary. Thus it's safer to round down this value on FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * size (16 Bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define STM32_DMA_MAX_CHANNELS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define STM32_DMA_MAX_REQUEST_ID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define STM32_DMA_MAX_DATA_PARAM 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define STM32_DMA_FIFO_SIZE 16 /* FIFO is 16 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define STM32_DMA_MIN_BURST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define STM32_DMA_MAX_BURST 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* DMA Features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define STM32_DMA_DIRECT_MODE_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define STM32_DMA_DIRECT_MODE_GET(n) (((n) & STM32_DMA_DIRECT_MODE_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum stm32_dma_width {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) STM32_DMA_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) STM32_DMA_HALF_WORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) STM32_DMA_WORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) enum stm32_dma_burst_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) STM32_DMA_BURST_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) STM32_DMA_BURST_INCR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) STM32_DMA_BURST_INCR8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) STM32_DMA_BURST_INCR16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * struct stm32_dma_cfg - STM32 DMA custom configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @channel_id: channel ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @request_line: DMA request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @stream_config: 32bit mask specifying the DMA channel configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @features: 32bit mask specifying the DMA Feature list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct stm32_dma_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 channel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 request_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 stream_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct stm32_dma_chan_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 dma_lisr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 dma_hisr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 dma_lifcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 dma_hifcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 dma_scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 dma_sndtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 dma_spar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 dma_sm0ar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 dma_sm1ar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 dma_sfcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct stm32_dma_sg_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct stm32_dma_chan_reg chan_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct stm32_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct virt_dma_desc vdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) bool cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 num_sgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct stm32_dma_sg_req sg_req[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct stm32_dma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct virt_dma_chan vchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bool config_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) bool busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct stm32_dma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 next_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct dma_slave_config dma_sconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct stm32_dma_chan_reg chan_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 mem_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 mem_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct stm32_dma_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct dma_device ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) bool mem2mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return container_of(chan->vchan.chan.device, struct stm32_dma_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return container_of(c, struct stm32_dma_chan, vchan.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return container_of(vdesc, struct stm32_dma_desc, vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct device *chan2dev(struct stm32_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return &chan->vchan.chan.dev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return readl_relaxed(dmadev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) writel_relaxed(val, dmadev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int stm32_dma_get_width(struct stm32_dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) enum dma_slave_buswidth width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return STM32_DMA_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return STM32_DMA_HALF_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return STM32_DMA_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_err(chan2dev(chan), "Dma bus width not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) enum dma_slave_buswidth max_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) max_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) max_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) while ((buf_len < max_width || buf_len % max_width) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) max_width > DMA_SLAVE_BUSWIDTH_1_BYTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) max_width = max_width >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return max_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) enum dma_slave_buswidth width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (burst != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * If number of beats fit in several whole bursts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * this configuration is allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) remaining = ((STM32_DMA_FIFO_SIZE / width) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) (threshold + 1) / 4) % burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (remaining == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* If FIFO direct mode, burst is not possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * Buffer or period length has to be aligned on FIFO depth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Otherwise bytes may be stuck within FIFO at buffer or period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return ((buf_len % ((threshold + 1) * 4)) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) enum dma_slave_buswidth width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 best_burst = max_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) while ((buf_len < best_burst * width && best_burst > 1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) width)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (best_burst > STM32_DMA_MIN_BURST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) best_burst = best_burst >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) best_burst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return best_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) switch (maxburst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return STM32_DMA_BURST_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return STM32_DMA_BURST_INCR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return STM32_DMA_BURST_INCR8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return STM32_DMA_BURST_INCR16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_err(chan2dev(chan), "Dma burst size not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 src_burst, u32 dst_burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!src_burst && !dst_burst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Using direct mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Using FIFO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int stm32_dma_slave_config(struct dma_chan *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct dma_slave_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) memcpy(&chan->dma_sconfig, config, sizeof(*config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) chan->config_init = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 flags, dma_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * Read "flags" from DMA_xISR register corresponding to the selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * DMA channel at the correct bit offset inside that register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (chan->id & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return flags & STM32_DMA_MASKI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 dma_ifcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Write "flags" to the DMA_xIFCR register corresponding to the selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * DMA channel at the correct bit offset inside that register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) flags &= STM32_DMA_MASKI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (chan->id & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int stm32_dma_disable_chan(struct stm32_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 dma_scr, id, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) id = chan->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) reg = STM32_DMA_SCR(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dma_scr = stm32_dma_read(dmadev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (dma_scr & STM32_DMA_SCR_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dma_scr &= ~STM32_DMA_SCR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) stm32_dma_write(dmadev, reg, dma_scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return readl_relaxed_poll_timeout_atomic(dmadev->base + reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dma_scr, !(dma_scr & STM32_DMA_SCR_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 10, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static void stm32_dma_stop(struct stm32_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 dma_scr, dma_sfcr, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dma_scr &= ~STM32_DMA_SCR_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dma_sfcr &= ~STM32_DMA_SFCR_FEIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Disable DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = stm32_dma_disable_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Clear interrupt status if it is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) status = stm32_dma_irq_status(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) stm32_dma_irq_clear(chan, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) chan->busy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int stm32_dma_terminate_all(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (chan->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) vchan_terminate_vdesc(&chan->desc->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (chan->busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) stm32_dma_stop(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) chan->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) vchan_get_all_descriptors(&chan->vchan, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) vchan_dma_desc_free_list(&chan->vchan, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static void stm32_dma_synchronize(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) vchan_synchronize(&chan->vchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_dbg(chan2dev(chan), "SCR: 0x%08x\n", scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev_dbg(chan2dev(chan), "NDTR: 0x%08x\n", ndtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev_dbg(chan2dev(chan), "SPAR: 0x%08x\n", spar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct virt_dma_desc *vdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct stm32_dma_sg_req *sg_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct stm32_dma_chan_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = stm32_dma_disable_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!chan->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) vdesc = vchan_next_desc(&chan->vchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (!vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) list_del(&vdesc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) chan->desc = to_stm32_dma_desc(vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) chan->next_sg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (chan->next_sg == chan->desc->num_sgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) chan->next_sg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) sg_req = &chan->desc->sg_req[chan->next_sg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) reg = &sg_req->chan_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) reg->dma_scr &= ~STM32_DMA_SCR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) chan->next_sg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Clear interrupt status if it is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) status = stm32_dma_irq_status(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) stm32_dma_irq_clear(chan, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (chan->desc->cyclic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) stm32_dma_configure_next_sg(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) stm32_dma_dump_reg(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Start DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) reg->dma_scr |= STM32_DMA_SCR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) chan->busy = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct stm32_dma_sg_req *sg_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u32 dma_scr, dma_sm0ar, dma_sm1ar, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) id = chan->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (dma_scr & STM32_DMA_SCR_DBM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (chan->next_sg == chan->desc->num_sgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) chan->next_sg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) sg_req = &chan->desc->sg_req[chan->next_sg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (dma_scr & STM32_DMA_SCR_CT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (chan->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (chan->desc->cyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) vchan_cyclic_callback(&chan->desc->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) chan->next_sg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) stm32_dma_configure_next_sg(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) chan->busy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (chan->next_sg == chan->desc->num_sgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) vchan_cookie_complete(&chan->desc->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) chan->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) stm32_dma_start_transfer(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct stm32_dma_chan *chan = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u32 status, scr, sfcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) spin_lock(&chan->vchan.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) status = stm32_dma_irq_status(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (status & STM32_DMA_TCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) stm32_dma_irq_clear(chan, STM32_DMA_TCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (scr & STM32_DMA_SCR_TCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) stm32_dma_handle_chan_done(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) status &= ~STM32_DMA_TCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (status & STM32_DMA_HTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) stm32_dma_irq_clear(chan, STM32_DMA_HTI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) status &= ~STM32_DMA_HTI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (status & STM32_DMA_FEI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) stm32_dma_irq_clear(chan, STM32_DMA_FEI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) status &= ~STM32_DMA_FEI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (sfcr & STM32_DMA_SFCR_FEIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!(scr & STM32_DMA_SCR_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dev_err(chan2dev(chan), "FIFO Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_dbg(chan2dev(chan), "FIFO over/underrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (status & STM32_DMA_DMEI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) stm32_dma_irq_clear(chan, STM32_DMA_DMEI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) status &= ~STM32_DMA_DMEI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (sfcr & STM32_DMA_SCR_DMEIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_dbg(chan2dev(chan), "Direct mode overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) stm32_dma_irq_clear(chan, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (!(scr & STM32_DMA_SCR_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_err(chan2dev(chan), "chan disabled by HW\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) spin_unlock(&chan->vchan.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static void stm32_dma_issue_pending(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) stm32_dma_start_transfer(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) enum dma_slave_buswidth *buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u32 buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) enum dma_slave_buswidth src_addr_width, dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int src_bus_width, dst_bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int src_burst_size, dst_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u32 dma_scr, fifoth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) src_addr_width = chan->dma_sconfig.src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dst_addr_width = chan->dma_sconfig.dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) src_maxburst = chan->dma_sconfig.src_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dst_maxburst = chan->dma_sconfig.dst_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) fifoth = chan->threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* Set device data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (dst_bus_width < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return dst_bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Set device burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dst_best_burst = stm32_dma_get_best_burst(buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dst_maxburst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) fifoth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dst_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (dst_burst_size < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return dst_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Set memory data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) src_addr_width = stm32_dma_get_max_width(buf_len, fifoth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) chan->mem_width = src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) src_bus_width = stm32_dma_get_width(chan, src_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (src_bus_width < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return src_bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Set memory burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) src_maxburst = STM32_DMA_MAX_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) src_best_burst = stm32_dma_get_best_burst(buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) src_maxburst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) fifoth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) src_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (src_burst_size < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return src_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) STM32_DMA_SCR_PSIZE(dst_bus_width) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) STM32_DMA_SCR_MSIZE(src_bus_width) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) STM32_DMA_SCR_PBURST(dst_burst_size) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) STM32_DMA_SCR_MBURST(src_burst_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Set FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Set peripheral address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) *buswidth = dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* Set device data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) src_bus_width = stm32_dma_get_width(chan, src_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (src_bus_width < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return src_bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Set device burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) src_best_burst = stm32_dma_get_best_burst(buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) src_maxburst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) fifoth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) src_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) chan->mem_burst = src_best_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (src_burst_size < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return src_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* Set memory data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dst_addr_width = stm32_dma_get_max_width(buf_len, fifoth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) chan->mem_width = dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (dst_bus_width < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return dst_bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* Set memory burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dst_maxburst = STM32_DMA_MAX_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dst_best_burst = stm32_dma_get_best_burst(buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dst_maxburst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) fifoth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dst_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) chan->mem_burst = dst_best_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (dst_burst_size < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return dst_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) STM32_DMA_SCR_PSIZE(src_bus_width) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) STM32_DMA_SCR_MSIZE(dst_bus_width) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) STM32_DMA_SCR_PBURST(src_burst_size) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) STM32_DMA_SCR_MBURST(dst_burst_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* Set FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* Set peripheral address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) *buswidth = chan->dma_sconfig.src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dev_err(chan2dev(chan), "Dma direction is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* Set DMA control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) chan->chan_reg.dma_scr |= dma_scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) memset(regs, 0, sizeof(struct stm32_dma_chan_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct dma_chan *c, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u32 sg_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct stm32_dma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) enum dma_slave_buswidth buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u32 nb_data_items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (!chan->config_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dev_err(chan2dev(chan), "dma channel is not configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (sg_len < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) desc = kzalloc(struct_size(desc, sg_req, sg_len), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* Set peripheral flow controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (chan->dma_sconfig.device_fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) for_each_sg(sgl, sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ret = stm32_dma_set_xfer_param(chan, direction, &buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) desc->sg_req[i].len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) nb_data_items = desc->sg_req[i].len / buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev_err(chan2dev(chan), "nb items not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) desc->num_sgs = sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) desc->cyclic = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) size_t period_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct stm32_dma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) enum dma_slave_buswidth buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) u32 num_periods, nb_data_items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (!buf_len || !period_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dev_err(chan2dev(chan), "Invalid buffer/period len\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (!chan->config_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dev_err(chan2dev(chan), "dma channel is not configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (buf_len % period_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * We allow to take more number of requests till DMA is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * not started. The driver will loop over all requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * Once DMA is started then new requests can be queued only after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * terminating the DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (chan->busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) dev_err(chan2dev(chan), "Request not allowed when dma busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) nb_data_items = period_len / buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_err(chan2dev(chan), "number of items not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* Enable Circular mode or double buffer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (buf_len == period_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* Clear periph ctrl if client set it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) num_periods = buf_len / period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) desc = kzalloc(struct_size(desc, sg_req, num_periods), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) for (i = 0; i < num_periods; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) desc->sg_req[i].len = period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) buf_addr += period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) desc->num_sgs = num_periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) desc->cyclic = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct dma_chan *c, dma_addr_t dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) dma_addr_t src, size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) enum dma_slave_buswidth max_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct stm32_dma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) size_t xfer_count, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) u32 num_sgs, best_burst, dma_burst, threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) desc = kzalloc(struct_size(desc, sg_req, num_sgs), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) threshold = chan->threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) xfer_count = min_t(size_t, len - offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* Compute best burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) threshold, max_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) dma_burst = stm32_dma_get_burst(chan, best_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) desc->sg_req[i].chan_reg.dma_scr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) STM32_DMA_SCR_PBURST(dma_burst) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) STM32_DMA_SCR_MBURST(dma_burst) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) STM32_DMA_SCR_MINC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) STM32_DMA_SCR_PINC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) STM32_DMA_SCR_TCIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) STM32_DMA_SCR_TEIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) desc->sg_req[i].chan_reg.dma_sfcr |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) STM32_DMA_SFCR_FTH(threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) desc->sg_req[i].chan_reg.dma_spar = src + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) desc->sg_req[i].chan_reg.dma_sndtr = xfer_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) desc->sg_req[i].len = xfer_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) desc->num_sgs = num_sgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) desc->cyclic = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) u32 dma_scr, width, ndtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) width = STM32_DMA_SCR_PSIZE_GET(dma_scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return ndtr << width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * stm32_dma_is_current_sg - check that expected sg_req is currently transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * @chan: dma channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * This function called when IRQ are disable, checks that the hardware has not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * switched on the next transfer in double buffer mode. The test is done by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * comparing the next_sg memory address with the hardware related register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * (based on CT bit value).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * Returns true if expected current transfer is still running or double
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * buffer mode is not activated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct stm32_dma_sg_req *sg_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) u32 dma_scr, dma_smar, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) id = chan->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (!(dma_scr & STM32_DMA_SCR_DBM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) sg_req = &chan->desc->sg_req[chan->next_sg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (dma_scr & STM32_DMA_SCR_CT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return (dma_smar == sg_req->chan_reg.dma_sm0ar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return (dma_smar == sg_req->chan_reg.dma_sm1ar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct stm32_dma_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) u32 next_sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) u32 modulo, burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) u32 residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) u32 n_sg = next_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * Calculate the residue means compute the descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * information:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * - the sg_req currently transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * - the Hardware remaining position in this sg (NDTR bits field).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * A race condition may occur if DMA is running in cyclic or double
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * buffer mode, since the DMA register are automatically reloaded at end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * of period transfer. The hardware may have switched to the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * transfer (CT bit updated) just before the position (SxNDTR reg) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * In this case the SxNDTR reg could (or not) correspond to the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * transfer position, and not the expected one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * The strategy implemented in the stm32 driver is to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * - read the SxNDTR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * - crosscheck that hardware is still in current transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * In case of switch, we can assume that the DMA is at the beginning of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * the next transfer. So we approximate the residue in consequence, by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * pointing on the beginning of next transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * This race condition doesn't apply for none cyclic mode, as double
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * buffer is not used. In such situation registers are updated by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) residue = stm32_dma_get_remaining_bytes(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (!stm32_dma_is_current_sg(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) n_sg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (n_sg == chan->desc->num_sgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) n_sg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) residue = sg_req->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * In cyclic mode, for the last period, residue = remaining bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * from NDTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * else for all other periods in cyclic mode, and in sg mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * residue = remaining bytes from NDTR + remaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * periods/sg to be transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (!chan->desc->cyclic || n_sg != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) for (i = n_sg; i < desc->num_sgs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) residue += desc->sg_req[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (!chan->mem_burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) burst_size = chan->mem_burst * chan->mem_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) modulo = residue % burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (modulo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) residue = residue - modulo + burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static enum dma_status stm32_dma_tx_status(struct dma_chan *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct dma_tx_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct virt_dma_desc *vdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) u32 residue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) status = dma_cookie_status(c, cookie, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (status == DMA_COMPLETE || !state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) vdesc = vchan_find_desc(&chan->vchan, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (chan->desc && cookie == chan->desc->vdesc.tx.cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) residue = stm32_dma_desc_residue(chan, chan->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) chan->next_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) else if (vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) residue = stm32_dma_desc_residue(chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) to_stm32_dma_desc(vdesc), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dma_set_residue(state, residue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static int stm32_dma_alloc_chan_resources(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) chan->config_init = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ret = pm_runtime_resume_and_get(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = stm32_dma_disable_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) pm_runtime_put(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static void stm32_dma_free_chan_resources(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (chan->busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) stm32_dma_stop(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) chan->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) pm_runtime_put(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) vchan_free_chan_resources(to_virt_chan(c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static void stm32_dma_desc_free(struct virt_dma_desc *vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) kfree(container_of(vdesc, struct stm32_dma_desc, vdesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static void stm32_dma_set_config(struct stm32_dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct stm32_dma_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) stm32_dma_clear_reg(&chan->chan_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* Enable Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (STM32_DMA_DIRECT_MODE_GET(cfg->features))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) struct stm32_dma_device *dmadev = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct device *dev = dmadev->ddev.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct stm32_dma_cfg cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct stm32_dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct dma_chan *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (dma_spec->args_count < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) dev_err(dev, "Bad number of cells\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) cfg.channel_id = dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) cfg.request_line = dma_spec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) cfg.stream_config = dma_spec->args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) cfg.features = dma_spec->args[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) dev_err(dev, "Bad channel and/or request id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) chan = &dmadev->chan[cfg.channel_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) c = dma_get_slave_channel(&chan->vchan.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (!c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) dev_err(dev, "No more channels available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) stm32_dma_set_config(chan, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static const struct of_device_id stm32_dma_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) { .compatible = "st,stm32-dma", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) MODULE_DEVICE_TABLE(of, stm32_dma_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static int stm32_dma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct stm32_dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct stm32_dma_device *dmadev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) struct dma_device *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) match = of_match_device(stm32_dma_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) dev_err(&pdev->dev, "Error: No device match found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (!dmadev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) dd = &dmadev->ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) dmadev->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (IS_ERR(dmadev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return PTR_ERR(dmadev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) dmadev->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (IS_ERR(dmadev->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk), "Can't get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ret = clk_prepare_enable(dmadev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) "st,mem2mem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) rst = devm_reset_control_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ret = PTR_ERR(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) reset_control_assert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) reset_control_deassert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) dma_set_max_seg_size(&pdev->dev, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) dma_cap_set(DMA_SLAVE, dd->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dma_cap_set(DMA_PRIVATE, dd->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) dma_cap_set(DMA_CYCLIC, dd->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) dd->device_free_chan_resources = stm32_dma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) dd->device_tx_status = stm32_dma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) dd->device_issue_pending = stm32_dma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) dd->device_prep_slave_sg = stm32_dma_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) dd->device_config = stm32_dma_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dd->device_terminate_all = stm32_dma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) dd->device_synchronize = stm32_dma_synchronize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) dd->copy_align = DMAENGINE_ALIGN_32_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) dd->max_burst = STM32_DMA_MAX_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) dd->descriptor_reuse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) dd->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) INIT_LIST_HEAD(&dd->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (dmadev->mem2mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) dma_cap_set(DMA_MEMCPY, dd->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dd->directions |= BIT(DMA_MEM_TO_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) chan = &dmadev->chan[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) chan->id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) chan->vchan.desc_free = stm32_dma_desc_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) vchan_init(&chan->vchan, dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ret = dma_async_device_register(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) chan = &dmadev->chan[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ret = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) goto err_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) chan->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) ret = devm_request_irq(&pdev->dev, chan->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) stm32_dma_chan_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dev_name(chan2dev(chan)), chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) "request_irq failed with err %d channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) ret, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) goto err_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ret = of_dma_controller_register(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) stm32_dma_of_xlate, dmadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) "STM32 DMA DMA OF registration failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) goto err_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) platform_set_drvdata(pdev, dmadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) dev_info(&pdev->dev, "STM32 DMA driver registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) err_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) dma_async_device_unregister(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) clk_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) clk_disable_unprepare(dmadev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) static int stm32_dma_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) clk_disable_unprepare(dmadev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static int stm32_dma_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) ret = clk_prepare_enable(dmadev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) dev_err(dev, "failed to prepare_enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static int stm32_dma_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) int id, ret, scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) ret = pm_runtime_resume_and_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) for (id = 0; id < STM32_DMA_MAX_CHANNELS; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (scr & STM32_DMA_SCR_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) dev_warn(dev, "Suspend is prevented by Chan %i\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static int stm32_dma_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static const struct dev_pm_ops stm32_dma_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) SET_SYSTEM_SLEEP_PM_OPS(stm32_dma_suspend, stm32_dma_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) stm32_dma_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static struct platform_driver stm32_dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .name = "stm32-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .of_match_table = stm32_dma_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .pm = &stm32_dma_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .probe = stm32_dma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static int __init stm32_dma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return platform_driver_register(&stm32_dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) subsys_initcall(stm32_dma_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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