^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) ST-Ericsson SA 2007-2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef STE_DMA40_LL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define STE_DMA40_LL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define D40_DREG_PCBASE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define D40_DREG_PCDELTA (8 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define D40_LLI_ALIGN 16 /* LLI alignment must be 16 bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define D40_LCPA_CHAN_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define D40_LCPA_CHAN_DST_DELTA 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define D40_TYPE_TO_GROUP(type) (type / 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define D40_TYPE_TO_EVENT(type) (type % 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define D40_GROUP_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Most bits of the CFG register are the same in log as in phy mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define D40_SREG_CFG_MST_POS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define D40_SREG_CFG_TIM_POS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define D40_SREG_CFG_EIM_POS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define D40_SREG_CFG_LOG_INCR_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define D40_SREG_CFG_PHY_PEN_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define D40_SREG_CFG_PSIZE_POS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define D40_SREG_CFG_ESIZE_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define D40_SREG_CFG_PRI_POS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define D40_SREG_CFG_LBE_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define D40_SREG_CFG_LOG_GIM_POS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define D40_SREG_CFG_LOG_MFU_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define D40_SREG_CFG_PHY_TM_POS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define D40_SREG_CFG_PHY_EVTL_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Standard channel parameters - basic mode (element register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define D40_SREG_ELEM_PHY_ECNT_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define D40_SREG_ELEM_PHY_EIDX_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Standard channel parameters - basic mode (Link register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define D40_SREG_LNK_PHY_TCP_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define D40_SREG_LNK_PHY_LMP_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define D40_SREG_LNK_PHY_PRE_POS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Source destination link address. Contains the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 29-bit byte word aligned address of the reload area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Standard basic channel logical mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Element register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define D40_SREG_ELEM_LOG_ECNT_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define D40_SREG_ELEM_LOG_LIDX_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define D40_SREG_ELEM_LOG_LOS_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define D40_SREG_ELEM_LOG_TCP_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Link register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define D40_EVENTLINE_POS(i) (2 * i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Standard basic channel logical params in memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* LCSP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define D40_MEM_LCSP0_ECNT_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define D40_MEM_LCSP0_SPTR_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define D40_MEM_LCSP0_ECNT_MASK (0xFFFF << D40_MEM_LCSP0_ECNT_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define D40_MEM_LCSP0_SPTR_MASK (0xFFFF << D40_MEM_LCSP0_SPTR_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* LCSP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define D40_MEM_LCSP1_SPTR_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define D40_MEM_LCSP1_SCFG_MST_POS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define D40_MEM_LCSP1_SCFG_TIM_POS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define D40_MEM_LCSP1_SCFG_EIM_POS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define D40_MEM_LCSP1_SCFG_INCR_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define D40_MEM_LCSP1_SCFG_PSIZE_POS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define D40_MEM_LCSP1_SCFG_ESIZE_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define D40_MEM_LCSP1_SLOS_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define D40_MEM_LCSP1_STCP_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define D40_MEM_LCSP1_SPTR_MASK (0xFFFF << D40_MEM_LCSP1_SPTR_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define D40_MEM_LCSP1_SCFG_TIM_MASK (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define D40_MEM_LCSP1_SCFG_INCR_MASK (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define D40_MEM_LCSP1_SCFG_PSIZE_MASK (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define D40_MEM_LCSP1_SLOS_MASK (0x7F << D40_MEM_LCSP1_SLOS_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define D40_MEM_LCSP1_STCP_MASK (0x1 << D40_MEM_LCSP1_STCP_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* LCSP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define D40_MEM_LCSP2_ECNT_POS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define D40_MEM_LCSP2_ECNT_MASK (0xFFFF << D40_MEM_LCSP2_ECNT_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* LCSP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define D40_MEM_LCSP3_DCFG_MST_POS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define D40_MEM_LCSP3_DCFG_TIM_POS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define D40_MEM_LCSP3_DCFG_EIM_POS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define D40_MEM_LCSP3_DCFG_INCR_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define D40_MEM_LCSP3_DCFG_PSIZE_POS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define D40_MEM_LCSP3_DCFG_ESIZE_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define D40_MEM_LCSP3_DLOS_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define D40_MEM_LCSP3_DTCP_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define D40_MEM_LCSP3_DLOS_MASK (0x7F << D40_MEM_LCSP3_DLOS_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define D40_MEM_LCSP3_DTCP_MASK (0x1 << D40_MEM_LCSP3_DTCP_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Standard channel parameter register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define D40_CHAN_REG_SSCFG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define D40_CHAN_REG_SSELT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define D40_CHAN_REG_SSPTR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define D40_CHAN_REG_SSLNK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define D40_CHAN_REG_SDCFG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define D40_CHAN_REG_SDELT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define D40_CHAN_REG_SDPTR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define D40_CHAN_REG_SDLNK 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* DMA Register Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define D40_DREG_GCC 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define D40_DREG_GCC_ENA 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* This assumes that there are only 4 event groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define D40_DREG_GCC_ENABLE_ALL 0x3ff01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define D40_DREG_GCC_EVTGRP_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define D40_DREG_GCC_SRC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define D40_DREG_GCC_DST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define D40_DREG_GCC_EVTGRP_ENA(x, y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) (1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define D40_DREG_PRTYP 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define D40_DREG_PRSME 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define D40_DREG_PRSMO 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define D40_DREG_PRMSE 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define D40_DREG_PRMSO 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define D40_DREG_PRMOE 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define D40_DREG_PRMOO 0x01C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define D40_DREG_PRMO_PCHAN_BASIC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define D40_DREG_PRMO_PCHAN_MODULO 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define D40_DREG_PRMO_PCHAN_DOUBLE_DST 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define D40_DREG_LCPA 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define D40_DREG_LCLA 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define D40_DREG_SSEG1 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define D40_DREG_SSEG2 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define D40_DREG_SSEG3 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define D40_DREG_SSEG4 0x03C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define D40_DREG_SCEG1 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define D40_DREG_SCEG2 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define D40_DREG_SCEG3 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define D40_DREG_SCEG4 0x04C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define D40_DREG_ACTIVE 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define D40_DREG_ACTIVO 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define D40_DREG_CIDMOD 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define D40_DREG_TCIDV 0x05C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define D40_DREG_PCMIS 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define D40_DREG_PCICR 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define D40_DREG_PCTIS 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define D40_DREG_PCEIS 0x06C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define D40_DREG_SPCMIS 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define D40_DREG_SPCICR 0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define D40_DREG_SPCTIS 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define D40_DREG_SPCEIS 0x07C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define D40_DREG_LCMIS0 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define D40_DREG_LCMIS1 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define D40_DREG_LCMIS2 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define D40_DREG_LCMIS3 0x08C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define D40_DREG_LCICR0 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define D40_DREG_LCICR1 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define D40_DREG_LCICR2 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define D40_DREG_LCICR3 0x09C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define D40_DREG_LCTIS0 0x0A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define D40_DREG_LCTIS1 0x0A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define D40_DREG_LCTIS2 0x0A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define D40_DREG_LCTIS3 0x0AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define D40_DREG_LCEIS0 0x0B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define D40_DREG_LCEIS1 0x0B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define D40_DREG_LCEIS2 0x0B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define D40_DREG_LCEIS3 0x0BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define D40_DREG_SLCMIS1 0x0C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define D40_DREG_SLCMIS2 0x0C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define D40_DREG_SLCMIS3 0x0C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define D40_DREG_SLCMIS4 0x0CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define D40_DREG_SLCICR1 0x0D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define D40_DREG_SLCICR2 0x0D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define D40_DREG_SLCICR3 0x0D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define D40_DREG_SLCICR4 0x0DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define D40_DREG_SLCTIS1 0x0E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define D40_DREG_SLCTIS2 0x0E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define D40_DREG_SLCTIS3 0x0E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define D40_DREG_SLCTIS4 0x0EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define D40_DREG_SLCEIS1 0x0F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define D40_DREG_SLCEIS2 0x0F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define D40_DREG_SLCEIS3 0x0F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define D40_DREG_SLCEIS4 0x0FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define D40_DREG_FSESS1 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define D40_DREG_FSESS2 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define D40_DREG_FSEBS1 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define D40_DREG_FSEBS2 0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define D40_DREG_PSEG1 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define D40_DREG_PSEG2 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define D40_DREG_PSEG3 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define D40_DREG_PSEG4 0x11C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define D40_DREG_PCEG1 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define D40_DREG_PCEG2 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define D40_DREG_PCEG3 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define D40_DREG_PCEG4 0x12C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define D40_DREG_RSEG1 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define D40_DREG_RSEG2 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define D40_DREG_RSEG3 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define D40_DREG_RSEG4 0x13C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define D40_DREG_RCEG1 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define D40_DREG_RCEG2 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define D40_DREG_RCEG3 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define D40_DREG_RCEG4 0x14C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define D40_DREG_PREFOT 0x15C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define D40_DREG_EXTCFG 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define D40_DREG_CPSEG1 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define D40_DREG_CPSEG2 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define D40_DREG_CPSEG3 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define D40_DREG_CPSEG4 0x20C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define D40_DREG_CPSEG5 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define D40_DREG_CPCEG1 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define D40_DREG_CPCEG2 0x224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define D40_DREG_CPCEG3 0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define D40_DREG_CPCEG4 0x22C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define D40_DREG_CPCEG5 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define D40_DREG_CRSEG1 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define D40_DREG_CRSEG2 0x244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define D40_DREG_CRSEG3 0x248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define D40_DREG_CRSEG4 0x24C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define D40_DREG_CRSEG5 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define D40_DREG_CRCEG1 0x260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define D40_DREG_CRCEG2 0x264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define D40_DREG_CRCEG3 0x268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define D40_DREG_CRCEG4 0x26C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define D40_DREG_CRCEG5 0x270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define D40_DREG_CFSESS1 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define D40_DREG_CFSESS2 0x284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define D40_DREG_CFSESS3 0x288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define D40_DREG_CFSEBS1 0x290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define D40_DREG_CFSEBS2 0x294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define D40_DREG_CFSEBS3 0x298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define D40_DREG_CLCMIS1 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define D40_DREG_CLCMIS2 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define D40_DREG_CLCMIS3 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define D40_DREG_CLCMIS4 0x30C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define D40_DREG_CLCMIS5 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define D40_DREG_CLCICR1 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define D40_DREG_CLCICR2 0x324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define D40_DREG_CLCICR3 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define D40_DREG_CLCICR4 0x32C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define D40_DREG_CLCICR5 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define D40_DREG_CLCTIS1 0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define D40_DREG_CLCTIS2 0x344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define D40_DREG_CLCTIS3 0x348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define D40_DREG_CLCTIS4 0x34C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define D40_DREG_CLCTIS5 0x350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define D40_DREG_CLCEIS1 0x360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define D40_DREG_CLCEIS2 0x364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define D40_DREG_CLCEIS3 0x368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define D40_DREG_CLCEIS4 0x36C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define D40_DREG_CLCEIS5 0x370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define D40_DREG_CPCMIS 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define D40_DREG_CPCICR 0x384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define D40_DREG_CPCTIS 0x388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define D40_DREG_CPCEIS 0x38C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define D40_DREG_SCCIDA1 0xE80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define D40_DREG_SCCIDA2 0xE90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define D40_DREG_SCCIDA3 0xEA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define D40_DREG_SCCIDA4 0xEB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define D40_DREG_SCCIDA5 0xEC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define D40_DREG_SCCIDB1 0xE84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define D40_DREG_SCCIDB2 0xE94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define D40_DREG_SCCIDB3 0xEA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define D40_DREG_SCCIDB4 0xEB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define D40_DREG_SCCIDB5 0xEC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define D40_DREG_PRSCCIDA 0xF80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define D40_DREG_PRSCCIDB 0xF84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define D40_DREG_STFU 0xFC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define D40_DREG_ICFG 0xFCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define D40_DREG_PERIPHID0 0xFE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define D40_DREG_PERIPHID1 0xFE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define D40_DREG_PERIPHID2 0xFE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define D40_DREG_PERIPHID3 0xFEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define D40_DREG_CELLID0 0xFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define D40_DREG_CELLID1 0xFF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define D40_DREG_CELLID2 0xFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define D40_DREG_CELLID3 0xFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* LLI related structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * struct d40_phy_lli - The basic configuration register for each physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * @reg_cfg: The configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * @reg_elt: The element register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * @reg_ptr: The pointer register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * @reg_lnk: The link register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * These registers are set up for both physical and logical transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * Note that the bit in each register means differently in logical and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * physical(standard) mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * This struct must be 16 bytes aligned, and only contain physical registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * since it will be directly accessed by the DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct d40_phy_lli {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 reg_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 reg_elt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 reg_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 reg_lnk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * struct d40_phy_lli_bidir - struct for a transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @src: Register settings for src channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @dst: Register settings for dst channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * All DMA transfers have a source and a destination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct d40_phy_lli_bidir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct d40_phy_lli *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct d40_phy_lli *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * struct d40_log_lli - logical lli configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * @lcsp02: Either maps to register lcsp0 if src or lcsp2 if dst.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * @lcsp13: Either maps to register lcsp1 if src or lcsp3 if dst.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * This struct must be 8 bytes aligned since it will be accessed directy by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * the DMA. Never add any none hw mapped registers to this struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct d40_log_lli {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 lcsp02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 lcsp13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * struct d40_log_lli_bidir - For both src and dst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * @src: pointer to src lli configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * @dst: pointer to dst lli configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * You always have a src and a dst when doing DMA transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct d40_log_lli_bidir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct d40_log_lli *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct d40_log_lli *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * struct d40_log_lli_full - LCPA layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * @lcsp0: Logical Channel Standard Param 0 - Src.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * @lcsp1: Logical Channel Standard Param 1 - Src.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * @lcsp2: Logical Channel Standard Param 2 - Dst.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * @lcsp3: Logical Channel Standard Param 3 - Dst.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * This struct maps to LCPA physical memory layout. Must map to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * the hw.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct d40_log_lli_full {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 lcsp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 lcsp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 lcsp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 lcsp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * struct d40_def_lcsp - Default LCSP1 and LCSP3 settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * @lcsp3: The default configuration for dst.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * @lcsp1: The default configuration for src.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct d40_def_lcsp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 lcsp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 lcsp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Physical channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) enum d40_lli_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) LLI_ADDR_INC = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) LLI_TERM_INT = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) LLI_CYCLIC = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) LLI_LAST_LINK = 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 *src_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 *dst_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) void d40_log_cfg(struct stedma40_chan_cfg *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 *lcsp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 *lcsp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int d40_phy_sg_to_lli(struct scatterlist *sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dma_addr_t target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct d40_phy_lli *lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dma_addr_t lli_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 reg_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct stedma40_half_channel_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct stedma40_half_channel_info *otherinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Logical channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int d40_log_sg_to_lli(struct scatterlist *sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dma_addr_t dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct d40_log_lli *lli_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 lcsp13, /* src or dst*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 data_width1, u32 data_width2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct d40_log_lli *lli_dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct d40_log_lli *lli_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int next, unsigned int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct d40_log_lli *lli_dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct d40_log_lli *lli_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int next, unsigned int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #endif /* STE_DMA40_LLI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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