^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) ST-Ericsson SA 2007-2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_data/dma-ste-dma40.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ste_dma40_ll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static u8 d40_width_to_bits(enum dma_slave_buswidth width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) return STEDMA40_ESIZE_8_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) return STEDMA40_ESIZE_16_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) return STEDMA40_ESIZE_64_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) return STEDMA40_ESIZE_32_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Sets up proper LCSP1 and LCSP3 register for a logical channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void d40_log_cfg(struct stedma40_chan_cfg *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 *lcsp1, u32 *lcsp3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 l3 = 0; /* dst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 l1 = 0; /* src */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* src is mem? -> increase address pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if (cfg->dir == DMA_MEM_TO_DEV ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) cfg->dir == DMA_MEM_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) l1 |= BIT(D40_MEM_LCSP1_SCFG_INCR_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* dst is mem? -> increase address pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (cfg->dir == DMA_DEV_TO_MEM ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) cfg->dir == DMA_MEM_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) l3 |= BIT(D40_MEM_LCSP3_DCFG_INCR_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* src is hw? -> master port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (cfg->dir == DMA_DEV_TO_MEM ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) cfg->dir == DMA_DEV_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) l1 |= BIT(D40_MEM_LCSP1_SCFG_MST_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* dst is hw? -> master port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (cfg->dir == DMA_MEM_TO_DEV ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) cfg->dir == DMA_DEV_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) l3 |= BIT(D40_MEM_LCSP3_DCFG_MST_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) l3 |= d40_width_to_bits(cfg->dst_info.data_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) << D40_MEM_LCSP3_DCFG_ESIZE_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) l1 |= d40_width_to_bits(cfg->src_info.data_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) << D40_MEM_LCSP1_SCFG_ESIZE_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *lcsp1 = l1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *lcsp3 = l3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 src = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 dst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if ((cfg->dir == DMA_DEV_TO_MEM) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (cfg->dir == DMA_DEV_TO_DEV)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Set master port to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) src |= BIT(D40_SREG_CFG_MST_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) src |= D40_TYPE_TO_EVENT(cfg->dev_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) src |= BIT(D40_SREG_CFG_PHY_TM_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) src |= 3 << D40_SREG_CFG_PHY_TM_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if ((cfg->dir == DMA_MEM_TO_DEV) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (cfg->dir == DMA_DEV_TO_DEV)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Set master port to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dst |= BIT(D40_SREG_CFG_MST_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dst |= BIT(D40_SREG_CFG_PHY_TM_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Interrupt on end of transfer for destination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dst |= BIT(D40_SREG_CFG_TIM_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Generate interrupt on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) src |= BIT(D40_SREG_CFG_EIM_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dst |= BIT(D40_SREG_CFG_EIM_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* PSIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) src |= BIT(D40_SREG_CFG_PHY_PEN_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dst |= BIT(D40_SREG_CFG_PHY_PEN_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Element size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) src |= d40_width_to_bits(cfg->src_info.data_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) << D40_SREG_CFG_ESIZE_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dst |= d40_width_to_bits(cfg->dst_info.data_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) << D40_SREG_CFG_ESIZE_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Set the priority bit to high for the physical channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (cfg->high_priority) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) src |= BIT(D40_SREG_CFG_PRI_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dst |= BIT(D40_SREG_CFG_PRI_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (cfg->src_info.big_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) src |= BIT(D40_SREG_CFG_LBE_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (cfg->dst_info.big_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dst |= BIT(D40_SREG_CFG_LBE_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *src_cfg = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *dst_cfg = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int d40_phy_fill_lli(struct d40_phy_lli *lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dma_addr_t data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 data_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dma_addr_t next_lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 reg_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct stedma40_half_channel_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bool addr_inc = flags & LLI_ADDR_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool term_int = flags & LLI_TERM_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int data_width = info->data_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int psize = info->psize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int num_elems;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (psize == STEDMA40_PSIZE_PHY_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) num_elems = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) num_elems = 2 << psize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Must be aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!IS_ALIGNED(data, data_width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Transfer size can't be smaller than (num_elms * elem_size) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (data_size < num_elems * data_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* The number of elements. IE now many chunks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) lli->reg_elt = (data_size / data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Distance to next element sized entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Usually the size of the element unless you want gaps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (addr_inc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) lli->reg_elt |= data_width << D40_SREG_ELEM_PHY_EIDX_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Where the data is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) lli->reg_ptr = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) lli->reg_cfg = reg_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* If this scatter list entry is the last one, no next link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (next_lli == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) lli->reg_lnk = next_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Set/clear interrupt generation on this link item.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (term_int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Post link - D40_SREG_LNK_PHY_PRE_POS = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Relink happens after transfer completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int d40_seg_size(int size, int data_width1, int data_width2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 max_w = max(data_width1, data_width2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 min_w = min(data_width1, data_width2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (seg_max > STEDMA40_MAX_SEG_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) seg_max -= max_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (size <= seg_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (size <= 2 * seg_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return ALIGN(size / 2, max_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return seg_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct d40_phy_lli *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) d40_phy_buf_to_lli(struct d40_phy_lli *lli, dma_addr_t addr, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct stedma40_half_channel_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct stedma40_half_channel_info *otherinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) bool lastlink = flags & LLI_LAST_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) bool addr_inc = flags & LLI_ADDR_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) bool term_int = flags & LLI_TERM_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) bool cyclic = flags & LLI_CYCLIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dma_addr_t next = lli_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int size_rest = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int size_seg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * This piece may be split up based on d40_seg_size(); we only want the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * term int on the last part.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (term_int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) flags &= ~LLI_TERM_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) size_seg = d40_seg_size(size_rest, info->data_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) otherinfo->data_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) size_rest -= size_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (size_rest == 0 && term_int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) flags |= LLI_TERM_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (size_rest == 0 && lastlink)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) next = cyclic ? first_phys : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) next = ALIGN(next + sizeof(struct d40_phy_lli),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) D40_LLI_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) err = d40_phy_fill_lli(lli, addr, size_seg, next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) reg_cfg, info, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) lli++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (addr_inc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) addr += size_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } while (size_rest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int d40_phy_sg_to_lli(struct scatterlist *sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dma_addr_t target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct d40_phy_lli *lli_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dma_addr_t lli_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 reg_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct stedma40_half_channel_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct stedma40_half_channel_info *otherinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int total_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct scatterlist *current_sg = sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct d40_phy_lli *lli = lli_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dma_addr_t l_phys = lli_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) flags |= LLI_ADDR_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) for_each_sg(sg, current_sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dma_addr_t sg_addr = sg_dma_address(current_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int len = sg_dma_len(current_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dma_addr_t dst = target ?: sg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) total_size += sg_dma_len(current_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (i == sg_len - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) flags |= LLI_TERM_INT | LLI_LAST_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) l_phys = ALIGN(lli_phys + (lli - lli_sg) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) sizeof(struct d40_phy_lli), D40_LLI_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) lli = d40_phy_buf_to_lli(lli, dst, len, l_phys, lli_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) reg_cfg, info, otherinfo, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (lli == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* DMA logical lli operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static void d40_log_lli_link(struct d40_log_lli *lli_dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct d40_log_lli *lli_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int next, unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) bool interrupt = flags & LLI_TERM_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 slos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 dlos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (next != -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) slos = next * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dlos = next * 2 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (interrupt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) (slos << D40_MEM_LCSP1_SLOS_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) (dlos << D40_MEM_LCSP1_SLOS_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct d40_log_lli *lli_dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct d40_log_lli *lli_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int next, unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) d40_log_lli_link(lli_dst, lli_src, next, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct d40_log_lli *lli_dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct d40_log_lli *lli_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int next, unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) d40_log_lli_link(lli_dst, lli_src, next, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void d40_log_fill_lli(struct d40_log_lli *lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dma_addr_t data, u32 data_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 reg_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 data_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) bool addr_inc = flags & LLI_ADDR_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) lli->lcsp13 = reg_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* The number of elements to transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) lli->lcsp02 = ((data_size / data_width) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) BUG_ON((data_size / data_width) > STEDMA40_MAX_SEG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* 16 LSBs address of the current element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* 16 MSBs address of the current element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (addr_inc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dma_addr_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 lcsp13, /* src or dst*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u32 data_width1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 data_width2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) bool addr_inc = flags & LLI_ADDR_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct d40_log_lli *lli = lli_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int size_rest = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int size_seg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) size_seg = d40_seg_size(size_rest, data_width1, data_width2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) size_rest -= size_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) d40_log_fill_lli(lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) size_seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) lcsp13, data_width1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (addr_inc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) addr += size_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) lli++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } while (size_rest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int d40_log_sg_to_lli(struct scatterlist *sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dma_addr_t dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct d40_log_lli *lli_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 lcsp13, /* src or dst*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 data_width1, u32 data_width2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int total_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct scatterlist *current_sg = sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct d40_log_lli *lli = lli_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!dev_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) flags |= LLI_ADDR_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) for_each_sg(sg, current_sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dma_addr_t sg_addr = sg_dma_address(current_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int len = sg_dma_len(current_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dma_addr_t addr = dev_addr ?: sg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) total_size += sg_dma_len(current_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) lli = d40_log_buf_to_lli(lli, addr, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) lcsp13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) data_width1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) data_width2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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