Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * DMA driver header for STMicroelectronics STi FDMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Ludovic Barre <Ludovic.barre@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef __DMA_ST_FDMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define __DMA_ST_FDMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/remoteproc/st_slim_rproc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define ST_FDMA_NR_DREQS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define FW_NAME_SIZE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DRIVER_NAME "st-fdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * struct st_fdma_generic_node - Free running/paced generic node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * @length: Length in bytes of a line in a 2D mem to mem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * @sstride: Stride, in bytes, between source lines in a 2D data move
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * @dstride: Stride, in bytes, between destination lines in a 2D data move
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct st_fdma_generic_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32 sstride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32 dstride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * struct st_fdma_hw_node - Node structure used by fdma hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * @next: Pointer to next node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * @control: Transfer Control Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * @nbytes: Number of Bytes to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * @saddr: Source address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * @daddr: Destination address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * @generic: generic node for free running/paced transfert type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * 2 others transfert type are possible, but not yet implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * The NODE structures must be aligned to a 32 byte boundary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct st_fdma_hw_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u32 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u32 nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u32 saddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u32 daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		struct st_fdma_generic_node generic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * node control parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define FDMA_NODE_CTRL_REQ_MAP_MASK	GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define FDMA_NODE_CTRL_REQ_MAP_FREE_RUN	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define FDMA_NODE_CTRL_REQ_MAP_DREQ(n)	((n)&FDMA_NODE_CTRL_REQ_MAP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define FDMA_NODE_CTRL_REQ_MAP_EXT		FDMA_NODE_CTRL_REQ_MAP_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define FDMA_NODE_CTRL_SRC_MASK		GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define FDMA_NODE_CTRL_SRC_STATIC	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define FDMA_NODE_CTRL_SRC_INCR		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define FDMA_NODE_CTRL_DST_MASK		GENMASK(8, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define FDMA_NODE_CTRL_DST_STATIC	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define FDMA_NODE_CTRL_DST_INCR		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define FDMA_NODE_CTRL_SECURE		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define FDMA_NODE_CTRL_PAUSE_EON	BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define FDMA_NODE_CTRL_INT_EON		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * struct st_fdma_sw_node - descriptor structure for link list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * @pdesc: Physical address of desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * @node: link used for putting this into a channel queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) struct st_fdma_sw_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	dma_addr_t pdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct st_fdma_hw_node *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define NAME_SZ 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) struct st_fdma_driverdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	char name[NAME_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) struct st_fdma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct virt_dma_desc vdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct st_fdma_chan *fchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	bool iscyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned int n_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct st_fdma_sw_node node[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum st_fdma_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ST_FDMA_TYPE_FREE_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	ST_FDMA_TYPE_PACED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct st_fdma_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct device_node *of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	enum st_fdma_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	dma_addr_t dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	enum dma_transfer_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int req_line; /* request line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	long req_ctrl; /* Request control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct st_fdma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct st_fdma_dev *fdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct dma_pool *node_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct dma_slave_config scfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct st_fdma_cfg cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int dreq_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct virt_dma_chan vchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct st_fdma_desc *fdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	enum dma_status	status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct st_fdma_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	const struct st_fdma_driverdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct dma_device dma_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct st_slim_rproc *slim_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct st_fdma_chan *chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	spinlock_t dreq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	unsigned long dreq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u32 nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	char fw_name[FW_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Peripheral Registers*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define FDMA_CMD_STA_OFST	0xFC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define FDMA_CMD_SET_OFST	0xFC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define FDMA_CMD_CLR_OFST	0xFC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define FDMA_CMD_MASK_OFST	0xFCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define FDMA_CMD_START(ch)		(0x1 << (ch << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define FDMA_CMD_PAUSE(ch)		(0x2 << (ch << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define FDMA_CMD_FLUSH(ch)		(0x3 << (ch << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define FDMA_INT_STA_OFST	0xFD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define FDMA_INT_STA_CH			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define FDMA_INT_STA_ERR		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define FDMA_INT_SET_OFST	0xFD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define FDMA_INT_CLR_OFST	0xFD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define FDMA_INT_MASK_OFST	0xFDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define fdma_read(fdev, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	readl((fdev)->slim_rproc->peri + name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define fdma_write(fdev, val, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	writel((val), (fdev)->slim_rproc->peri + name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* fchan interface (dmem) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FDMA_CH_CMD_OFST	0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FDMA_CH_CMD_STA_MASK		GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define FDMA_CH_CMD_STA_IDLE		(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define FDMA_CH_CMD_STA_START		(0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define FDMA_CH_CMD_STA_RUNNING		(0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define FDMA_CH_CMD_STA_PAUSED		(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define FDMA_CH_CMD_ERR_MASK		GENMASK(4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define FDMA_CH_CMD_ERR_INT		(0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define FDMA_CH_CMD_ERR_NAND		(0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define FDMA_CH_CMD_ERR_MCHI		(0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FDMA_CH_CMD_DATA_MASK		GENMASK(31, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define fchan_read(fchan, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	readl((fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			+ (fchan)->vchan.chan.chan_id * 0x4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			+ name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define fchan_write(fchan, val, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			+ (fchan)->vchan.chan.chan_id * 0x4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			+ name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* req interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define FDMA_REQ_CTRL_OFST	0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define dreq_write(fchan, val, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			+ fchan->dreq_line * 0x04 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			+ name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* node interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define FDMA_NODE_SZ 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define FDMA_PTRN_OFST		0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define FDMA_CNTN_OFST		0x808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define FDMA_SADDRN_OFST	0x80c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define FDMA_DADDRN_OFST	0x810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define fnode_read(fchan, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	readl((fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			+ (fchan)->vchan.chan.chan_id * FDMA_NODE_SZ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			+ name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define fnode_write(fchan, val, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			+ (fchan)->vchan.chan.chan_id * FDMA_NODE_SZ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			+ name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * request control bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define FDMA_REQ_CTRL_NUM_OPS_MASK	GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define FDMA_REQ_CTRL_NUM_OPS(n)	(FDMA_REQ_CTRL_NUM_OPS_MASK & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 					((n) << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define FDMA_REQ_CTRL_INITIATOR_MASK	BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define FDMA_REQ_CTRL_INIT0		(0x0 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define FDMA_REQ_CTRL_INIT1		(0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define FDMA_REQ_CTRL_INC_ADDR_ON	BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define FDMA_REQ_CTRL_DATA_SWAP_ON	BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define FDMA_REQ_CTRL_WNR		BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define FDMA_REQ_CTRL_OPCODE_MASK	GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define FDMA_REQ_CTRL_OPCODE_LD_ST1	(0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define FDMA_REQ_CTRL_OPCODE_LD_ST2	(0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define FDMA_REQ_CTRL_OPCODE_LD_ST4	(0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define FDMA_REQ_CTRL_OPCODE_LD_ST8	(0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define FDMA_REQ_CTRL_OPCODE_LD_ST16	(0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define FDMA_REQ_CTRL_OPCODE_LD_ST32	(0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define FDMA_REQ_CTRL_OPCODE_LD_ST64	(0x6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define FDMA_REQ_CTRL_HOLDOFF_MASK	GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define FDMA_REQ_CTRL_HOLDOFF(n)	((n) & FDMA_REQ_CTRL_HOLDOFF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* bits used by client to configure request control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define FDMA_REQ_CTRL_CFG_MASK (FDMA_REQ_CTRL_HOLDOFF_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 				FDMA_REQ_CTRL_DATA_SWAP_ON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				FDMA_REQ_CTRL_INC_ADDR_ON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				FDMA_REQ_CTRL_INITIATOR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #endif	/* __DMA_ST_FDMA_H */