^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DMA driver for STMicroelectronics STi FDMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Ludovic Barre <Ludovic.barre@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Peter Griffin <peter.griffin@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/remoteproc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "st_fdma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static inline struct st_fdma_chan *to_st_fdma_chan(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return container_of(c, struct st_fdma_chan, vchan.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct st_fdma_desc *to_st_fdma_desc(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) return container_of(vd, struct st_fdma_desc, vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int st_fdma_dreq_get(struct st_fdma_chan *fchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct st_fdma_dev *fdev = fchan->fdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 req_line_cfg = fchan->cfg.req_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 dreq_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int try = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * dreq_mask is shared for n channels of fdma, so all accesses must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * atomic. if the dreq_mask is changed between ffz and set_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * we retry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (fdev->dreq_mask == ~0L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) dev_err(fdev->dev, "No req lines available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (try || req_line_cfg >= ST_FDMA_NR_DREQS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) dev_err(fdev->dev, "Invalid or used req line\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dreq_line = req_line_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) try++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) } while (test_and_set_bit(dreq_line, &fdev->dreq_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev_dbg(fdev->dev, "get dreq_line:%d mask:%#lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) dreq_line, fdev->dreq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return dreq_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void st_fdma_dreq_put(struct st_fdma_chan *fchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct st_fdma_dev *fdev = fchan->fdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) dev_dbg(fdev->dev, "put dreq_line:%#x\n", fchan->dreq_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clear_bit(fchan->dreq_line, &fdev->dreq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void st_fdma_xfer_desc(struct st_fdma_chan *fchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct virt_dma_desc *vdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long nbytes, ch_cmd, cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) vdesc = vchan_next_desc(&fchan->vchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) fchan->fdesc = to_st_fdma_desc(vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) nbytes = fchan->fdesc->node[0].desc->nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) cmd = FDMA_CMD_START(fchan->vchan.chan.chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ch_cmd = fchan->fdesc->node[0].pdesc | FDMA_CH_CMD_STA_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* start the channel for the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) fnode_write(fchan, nbytes, FDMA_CNTN_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) fchan_write(fchan, ch_cmd, FDMA_CH_CMD_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel(cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) fchan->fdev->slim_rproc->peri + FDMA_CMD_SET_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev_dbg(fchan->fdev->dev, "start chan:%d\n", fchan->vchan.chan.chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void st_fdma_ch_sta_update(struct st_fdma_chan *fchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long int_sta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long ch_sta, ch_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int ch_id = fchan->vchan.chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct st_fdma_dev *fdev = fchan->fdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ch_sta = fchan_read(fchan, FDMA_CH_CMD_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ch_err = ch_sta & FDMA_CH_CMD_ERR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ch_sta &= FDMA_CH_CMD_STA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (int_sta & FDMA_INT_STA_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_warn(fdev->dev, "chan:%d, error:%ld\n", ch_id, ch_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) fchan->status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) switch (ch_sta) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case FDMA_CH_CMD_STA_PAUSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) fchan->status = DMA_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case FDMA_CH_CMD_STA_RUNNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) fchan->status = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static irqreturn_t st_fdma_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct st_fdma_dev *fdev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct st_fdma_chan *fchan = &fdev->chans[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long int_sta, clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int_sta = fdma_read(fdev, FDMA_INT_STA_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) clr = int_sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) for (; int_sta != 0 ; int_sta >>= 2, fchan++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!(int_sta & (FDMA_INT_STA_CH | FDMA_INT_STA_ERR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) spin_lock(&fchan->vchan.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) st_fdma_ch_sta_update(fchan, int_sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (fchan->fdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!fchan->fdesc->iscyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) list_del(&fchan->fdesc->vdesc.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) vchan_cookie_complete(&fchan->fdesc->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) fchan->fdesc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) fchan->status = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) vchan_cyclic_callback(&fchan->fdesc->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Start the next descriptor (if available) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!fchan->fdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) st_fdma_xfer_desc(fchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) spin_unlock(&fchan->vchan.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) fdma_write(fdev, clr, FDMA_INT_CLR_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct dma_chan *st_fdma_of_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct st_fdma_dev *fdev = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct st_fdma_chan *fchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (dma_spec->args_count < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (fdev->dma_device.dev->of_node != dma_spec->np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = rproc_boot(fdev->slim_rproc->rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) else if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) chan = dma_get_any_slave_channel(&fdev->dma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) goto err_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) fchan = to_st_fdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) fchan->cfg.of_node = dma_spec->np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) fchan->cfg.req_line = dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) fchan->cfg.req_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) fchan->cfg.type = ST_FDMA_TYPE_FREE_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (dma_spec->args_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) fchan->cfg.req_ctrl = dma_spec->args[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) & FDMA_REQ_CTRL_CFG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (dma_spec->args_count > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) fchan->cfg.type = dma_spec->args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (fchan->cfg.type == ST_FDMA_TYPE_FREE_RUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) fchan->dreq_line = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) fchan->dreq_line = st_fdma_dreq_get(fchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (IS_ERR_VALUE(fchan->dreq_line)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) chan = ERR_PTR(fchan->dreq_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) goto err_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_dbg(fdev->dev, "xlate req_line:%d type:%d req_ctrl:%#lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) fchan->cfg.req_line, fchan->cfg.type, fchan->cfg.req_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) err_chan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) rproc_shutdown(fdev->slim_rproc->rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void st_fdma_free_desc(struct virt_dma_desc *vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct st_fdma_desc *fdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) fdesc = to_st_fdma_desc(vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (i = 0; i < fdesc->n_nodes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dma_pool_free(fdesc->fchan->node_pool, fdesc->node[i].desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) fdesc->node[i].pdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) kfree(fdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static struct st_fdma_desc *st_fdma_alloc_desc(struct st_fdma_chan *fchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int sg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct st_fdma_desc *fdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) fdesc = kzalloc(struct_size(fdesc, node, sg_len), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!fdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) fdesc->fchan = fchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) fdesc->n_nodes = sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) for (i = 0; i < sg_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) fdesc->node[i].desc = dma_pool_alloc(fchan->node_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) GFP_NOWAIT, &fdesc->node[i].pdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!fdesc->node[i].desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return fdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dma_pool_free(fchan->node_pool, fdesc->node[i].desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) fdesc->node[i].pdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) kfree(fdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int st_fdma_alloc_chan_res(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Create the dma pool for descriptor allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) fchan->node_pool = dma_pool_create(dev_name(&chan->dev->device),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) fchan->fdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sizeof(struct st_fdma_hw_node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __alignof__(struct st_fdma_hw_node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!fchan->node_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_err(fchan->fdev->dev, "unable to allocate desc pool\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_dbg(fchan->fdev->dev, "alloc ch_id:%d type:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) fchan->vchan.chan.chan_id, fchan->cfg.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void st_fdma_free_chan_res(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct rproc *rproc = fchan->fdev->slim_rproc->rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_dbg(fchan->fdev->dev, "%s: freeing chan:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __func__, fchan->vchan.chan.chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (fchan->cfg.type != ST_FDMA_TYPE_FREE_RUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) st_fdma_dreq_put(fchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) spin_lock_irqsave(&fchan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) fchan->fdesc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) spin_unlock_irqrestore(&fchan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dma_pool_destroy(fchan->node_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) fchan->node_pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) memset(&fchan->cfg, 0, sizeof(struct st_fdma_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) rproc_shutdown(rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct dma_async_tx_descriptor *st_fdma_prep_dma_memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct st_fdma_chan *fchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct st_fdma_desc *fdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct st_fdma_hw_node *hw_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) fchan = to_st_fdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* We only require a single descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) fdesc = st_fdma_alloc_desc(fchan, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!fdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev_err(fchan->fdev->dev, "no memory for desc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) hw_node = fdesc->node[0].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) hw_node->next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) hw_node->control = FDMA_NODE_CTRL_REQ_MAP_FREE_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) hw_node->control |= FDMA_NODE_CTRL_SRC_INCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) hw_node->control |= FDMA_NODE_CTRL_DST_INCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) hw_node->control |= FDMA_NODE_CTRL_INT_EON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) hw_node->nbytes = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) hw_node->saddr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) hw_node->daddr = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) hw_node->generic.length = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) hw_node->generic.sstride = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) hw_node->generic.dstride = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int config_reqctrl(struct st_fdma_chan *fchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) enum dma_transfer_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 maxburst = 0, addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) enum dma_slave_buswidth width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int ch_id = fchan->vchan.chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct st_fdma_dev *fdev = fchan->fdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) fchan->cfg.req_ctrl &= ~FDMA_REQ_CTRL_WNR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) maxburst = fchan->scfg.src_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) width = fchan->scfg.src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) addr = fchan->scfg.src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_WNR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) maxburst = fchan->scfg.dst_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) width = fchan->scfg.dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) addr = fchan->scfg.dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) fchan->cfg.req_ctrl &= ~FDMA_REQ_CTRL_OPCODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_OPCODE_LD_ST1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_OPCODE_LD_ST2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_OPCODE_LD_ST4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case DMA_SLAVE_BUSWIDTH_8_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_OPCODE_LD_ST8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) fchan->cfg.req_ctrl &= ~FDMA_REQ_CTRL_NUM_OPS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) fchan->cfg.req_ctrl |= FDMA_REQ_CTRL_NUM_OPS(maxburst-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dreq_write(fchan, fchan->cfg.req_ctrl, FDMA_REQ_CTRL_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) fchan->cfg.dev_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) fchan->cfg.dir = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_dbg(fdev->dev, "chan:%d config_reqctrl:%#x req_ctrl:%#lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ch_id, addr, fchan->cfg.req_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static void fill_hw_node(struct st_fdma_hw_node *hw_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct st_fdma_chan *fchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) enum dma_transfer_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (direction == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) hw_node->control |= FDMA_NODE_CTRL_SRC_INCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) hw_node->control |= FDMA_NODE_CTRL_DST_STATIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) hw_node->daddr = fchan->cfg.dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) hw_node->control |= FDMA_NODE_CTRL_SRC_STATIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) hw_node->control |= FDMA_NODE_CTRL_DST_INCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) hw_node->saddr = fchan->cfg.dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) hw_node->generic.sstride = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) hw_node->generic.dstride = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static inline struct st_fdma_chan *st_fdma_prep_common(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) size_t len, enum dma_transfer_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct st_fdma_chan *fchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!chan || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) fchan = to_st_fdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!is_slave_direction(direction)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_err(fchan->fdev->dev, "bad direction?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return fchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static struct dma_async_tx_descriptor *st_fdma_prep_dma_cyclic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct dma_chan *chan, dma_addr_t buf_addr, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) size_t period_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct st_fdma_chan *fchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct st_fdma_desc *fdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int sg_len, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) fchan = st_fdma_prep_common(chan, len, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!fchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!period_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (config_reqctrl(fchan, direction)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_err(fchan->fdev->dev, "bad width or direction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* the buffer length must be a multiple of period_len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (len % period_len != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_err(fchan->fdev->dev, "len is not multiple of period\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) sg_len = len / period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) fdesc = st_fdma_alloc_desc(fchan, sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!fdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(fchan->fdev->dev, "no memory for desc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) fdesc->iscyclic = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) for (i = 0; i < sg_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct st_fdma_hw_node *hw_node = fdesc->node[i].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) hw_node->next = fdesc->node[(i + 1) % sg_len].pdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) hw_node->control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) FDMA_NODE_CTRL_REQ_MAP_DREQ(fchan->dreq_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) hw_node->control |= FDMA_NODE_CTRL_INT_EON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) fill_hw_node(hw_node, fchan, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (direction == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) hw_node->saddr = buf_addr + (i * period_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) hw_node->daddr = buf_addr + (i * period_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) hw_node->nbytes = period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) hw_node->generic.length = period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static struct dma_async_tx_descriptor *st_fdma_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct dma_chan *chan, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned int sg_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct st_fdma_chan *fchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct st_fdma_desc *fdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct st_fdma_hw_node *hw_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) fchan = st_fdma_prep_common(chan, sg_len, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (!fchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (!sgl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) fdesc = st_fdma_alloc_desc(fchan, sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (!fdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dev_err(fchan->fdev->dev, "no memory for desc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) fdesc->iscyclic = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) for_each_sg(sgl, sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) hw_node = fdesc->node[i].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) hw_node->next = fdesc->node[(i + 1) % sg_len].pdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) hw_node->control = FDMA_NODE_CTRL_REQ_MAP_DREQ(fchan->dreq_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) fill_hw_node(hw_node, fchan, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (direction == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) hw_node->saddr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) hw_node->daddr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) hw_node->nbytes = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) hw_node->generic.length = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* interrupt at end of last node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) hw_node->control |= FDMA_NODE_CTRL_INT_EON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static size_t st_fdma_desc_residue(struct st_fdma_chan *fchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct virt_dma_desc *vdesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) bool in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct st_fdma_desc *fdesc = fchan->fdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) size_t residue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dma_addr_t cur_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) cur_addr = fchan_read(fchan, FDMA_CH_CMD_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) cur_addr &= FDMA_CH_CMD_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) for (i = fchan->fdesc->n_nodes - 1 ; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (cur_addr == fdesc->node[i].pdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) residue += fnode_read(fchan, FDMA_CNTN_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) residue += fdesc->node[i].desc->nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static enum dma_status st_fdma_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct virt_dma_desc *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) enum dma_status ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (ret == DMA_COMPLETE || !txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) spin_lock_irqsave(&fchan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) vd = vchan_find_desc(&fchan->vchan, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (fchan->fdesc && cookie == fchan->fdesc->vdesc.tx.cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) txstate->residue = st_fdma_desc_residue(fchan, vd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) else if (vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) txstate->residue = st_fdma_desc_residue(fchan, vd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) txstate->residue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) spin_unlock_irqrestore(&fchan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void st_fdma_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) spin_lock_irqsave(&fchan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (vchan_issue_pending(&fchan->vchan) && !fchan->fdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) st_fdma_xfer_desc(fchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) spin_unlock_irqrestore(&fchan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int st_fdma_pause(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) int ch_id = fchan->vchan.chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) unsigned long cmd = FDMA_CMD_PAUSE(ch_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dev_dbg(fchan->fdev->dev, "pause chan:%d\n", ch_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) spin_lock_irqsave(&fchan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (fchan->fdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) fdma_write(fchan->fdev, cmd, FDMA_CMD_SET_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) spin_unlock_irqrestore(&fchan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int st_fdma_resume(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int ch_id = fchan->vchan.chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) dev_dbg(fchan->fdev->dev, "resume chan:%d\n", ch_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) spin_lock_irqsave(&fchan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (fchan->fdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) val = fchan_read(fchan, FDMA_CH_CMD_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) val &= FDMA_CH_CMD_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) fchan_write(fchan, val, FDMA_CH_CMD_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) spin_unlock_irqrestore(&fchan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int st_fdma_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) int ch_id = fchan->vchan.chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned long cmd = FDMA_CMD_PAUSE(ch_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_dbg(fchan->fdev->dev, "terminate chan:%d\n", ch_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) spin_lock_irqsave(&fchan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) fdma_write(fchan->fdev, cmd, FDMA_CMD_SET_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) fchan->fdesc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) vchan_get_all_descriptors(&fchan->vchan, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) spin_unlock_irqrestore(&fchan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) vchan_dma_desc_free_list(&fchan->vchan, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int st_fdma_slave_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct dma_slave_config *slave_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) memcpy(&fchan->scfg, slave_cfg, sizeof(fchan->scfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static const struct st_fdma_driverdata fdma_mpe31_stih407_11 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .name = "STiH407",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const struct st_fdma_driverdata fdma_mpe31_stih407_12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .name = "STiH407",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const struct st_fdma_driverdata fdma_mpe31_stih407_13 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .name = "STiH407",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .id = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static const struct of_device_id st_fdma_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) { .compatible = "st,stih407-fdma-mpe31-11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) , .data = &fdma_mpe31_stih407_11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { .compatible = "st,stih407-fdma-mpe31-12"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) , .data = &fdma_mpe31_stih407_12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { .compatible = "st,stih407-fdma-mpe31-13"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) , .data = &fdma_mpe31_stih407_13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) MODULE_DEVICE_TABLE(of, st_fdma_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int st_fdma_parse_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) const struct st_fdma_driverdata *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct st_fdma_dev *fdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) snprintf(fdev->fw_name, FW_NAME_SIZE, "fdma_%s_%d.elf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) drvdata->name, drvdata->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return of_property_read_u32(pdev->dev.of_node, "dma-channels",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) &fdev->nr_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define FDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static void st_fdma_free(struct st_fdma_dev *fdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct st_fdma_chan *fchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) for (i = 0; i < fdev->nr_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) fchan = &fdev->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) list_del(&fchan->vchan.chan.device_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) tasklet_kill(&fchan->vchan.task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static int st_fdma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct st_fdma_dev *fdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) const struct st_fdma_driverdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) match = of_match_device((st_fdma_match), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (!match || !match->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev_err(&pdev->dev, "No device match found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) drvdata = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) fdev = devm_kzalloc(&pdev->dev, sizeof(*fdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (!fdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = st_fdma_parse_dt(pdev, drvdata, fdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_err(&pdev->dev, "unable to find platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) fdev->chans = devm_kcalloc(&pdev->dev, fdev->nr_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) sizeof(struct st_fdma_chan), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (!fdev->chans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) fdev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) fdev->drvdata = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) platform_set_drvdata(pdev, fdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) fdev->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (fdev->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = devm_request_irq(&pdev->dev, fdev->irq, st_fdma_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dev_name(&pdev->dev), fdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dev_err(&pdev->dev, "Failed to request irq (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) fdev->slim_rproc = st_slim_rproc_alloc(pdev, fdev->fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (IS_ERR(fdev->slim_rproc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ret = PTR_ERR(fdev->slim_rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dev_err(&pdev->dev, "slim_rproc_alloc failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Initialise list of FDMA channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) INIT_LIST_HEAD(&fdev->dma_device.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) for (i = 0; i < fdev->nr_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct st_fdma_chan *fchan = &fdev->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) fchan->fdev = fdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) fchan->vchan.desc_free = st_fdma_free_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) vchan_init(&fchan->vchan, &fdev->dma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Initialise the FDMA dreq (reserve 0 & 31 for FDMA use) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) fdev->dreq_mask = BIT(0) | BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dma_cap_set(DMA_SLAVE, fdev->dma_device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dma_cap_set(DMA_CYCLIC, fdev->dma_device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dma_cap_set(DMA_MEMCPY, fdev->dma_device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) fdev->dma_device.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) fdev->dma_device.device_alloc_chan_resources = st_fdma_alloc_chan_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) fdev->dma_device.device_free_chan_resources = st_fdma_free_chan_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) fdev->dma_device.device_prep_dma_cyclic = st_fdma_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) fdev->dma_device.device_prep_slave_sg = st_fdma_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) fdev->dma_device.device_prep_dma_memcpy = st_fdma_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) fdev->dma_device.device_tx_status = st_fdma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) fdev->dma_device.device_issue_pending = st_fdma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) fdev->dma_device.device_terminate_all = st_fdma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) fdev->dma_device.device_config = st_fdma_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) fdev->dma_device.device_pause = st_fdma_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) fdev->dma_device.device_resume = st_fdma_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) fdev->dma_device.src_addr_widths = FDMA_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) fdev->dma_device.dst_addr_widths = FDMA_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) fdev->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) fdev->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ret = dmaenginem_async_device_register(&fdev->dma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) "Failed to register DMA device (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto err_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ret = of_dma_controller_register(np, st_fdma_of_xlate, fdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) "Failed to register controller (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) goto err_rproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_info(&pdev->dev, "ST FDMA engine driver, irq:%d\n", fdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) err_rproc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) st_fdma_free(fdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) st_slim_rproc_put(fdev->slim_rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static int st_fdma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct st_fdma_dev *fdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) devm_free_irq(&pdev->dev, fdev->irq, fdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) st_slim_rproc_put(fdev->slim_rproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) of_dma_controller_free(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static struct platform_driver st_fdma_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .of_match_table = st_fdma_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .probe = st_fdma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .remove = st_fdma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) module_platform_driver(st_fdma_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) MODULE_DESCRIPTION("STMicroelectronics FDMA engine driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) MODULE_AUTHOR("Ludovic.barre <Ludovic.barre@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) MODULE_AUTHOR("Peter Griffin <peter.griffin@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) MODULE_ALIAS("platform:" DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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