^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2017 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma/sprd-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPRD_DMA_CHN_REG_OFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPRD_DMA_CHN_REG_LENGTH 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPRD_DMA_MEMCPY_MIN_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* DMA global registers definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPRD_DMA_GLB_PAUSE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPRD_DMA_GLB_FRAG_WAIT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPRD_DMA_GLB_REQ_PEND0_EN 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPRD_DMA_GLB_REQ_PEND1_EN 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPRD_DMA_GLB_INT_RAW_STS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPRD_DMA_GLB_INT_MSK_STS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPRD_DMA_GLB_REQ_STS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPRD_DMA_GLB_CHN_EN_STS 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPRD_DMA_GLB_DEBUG_STS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPRD_DMA_GLB_ARB_SEL_STS 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPRD_DMA_GLB_2STAGE_GRP1 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPRD_DMA_GLB_2STAGE_GRP2 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPRD_DMA_GLB_REQ_UID(uid) (0x4 * ((uid) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPRD_DMA_GLB_REQ_UID_OFFSET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* DMA channel registers definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPRD_DMA_CHN_PAUSE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPRD_DMA_CHN_REQ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPRD_DMA_CHN_CFG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPRD_DMA_CHN_INTC 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPRD_DMA_CHN_SRC_ADDR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPRD_DMA_CHN_DES_ADDR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPRD_DMA_CHN_FRG_LEN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPRD_DMA_CHN_BLK_LEN 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPRD_DMA_CHN_TRSC_LEN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPRD_DMA_CHN_TRSF_STEP 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPRD_DMA_CHN_WARP_PTR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPRD_DMA_CHN_WARP_TO 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPRD_DMA_CHN_LLIST_PTR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPRD_DMA_CHN_FRAG_STEP 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPRD_DMA_CHN_SRC_BLK_STEP 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPRD_DMA_CHN_DES_BLK_STEP 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* SPRD_DMA_GLB_2STAGE_GRP register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPRD_DMA_GLB_2STAGE_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPRD_DMA_GLB_CHN_INT_MASK GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPRD_DMA_GLB_DEST_INT BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPRD_DMA_GLB_SRC_INT BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPRD_DMA_GLB_LIST_DONE_TRG BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPRD_DMA_GLB_TRANS_DONE_TRG BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPRD_DMA_GLB_BLOCK_DONE_TRG BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPRD_DMA_GLB_FRAG_DONE_TRG BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPRD_DMA_GLB_TRG_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPRD_DMA_GLB_DEST_CHN_MASK GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPRD_DMA_GLB_DEST_CHN_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SPRD_DMA_GLB_SRC_CHN_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* SPRD_DMA_CHN_INTC register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPRD_DMA_INT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SPRD_DMA_INT_CLR_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPRD_DMA_FRAG_INT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPRD_DMA_BLK_INT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPRD_DMA_TRANS_INT_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SPRD_DMA_LIST_INT_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SPRD_DMA_CFG_ERR_INT_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* SPRD_DMA_CHN_CFG register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPRD_DMA_CHN_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SPRD_DMA_LINKLIST_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SPRD_DMA_WAIT_BDONE_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SPRD_DMA_DONOT_WAIT_BDONE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* SPRD_DMA_CHN_REQ register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SPRD_DMA_REQ_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* SPRD_DMA_CHN_PAUSE register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SPRD_DMA_PAUSE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPRD_DMA_PAUSE_STS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SPRD_DMA_PAUSE_CNT 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* DMA_CHN_WARP_* register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPRD_DMA_HIGH_ADDR_MASK GENMASK(31, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPRD_DMA_LOW_ADDR_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SPRD_DMA_WRAP_ADDR_MASK GENMASK(27, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SPRD_DMA_HIGH_ADDR_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* SPRD_DMA_CHN_INTC register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SPRD_DMA_FRAG_INT_STS BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SPRD_DMA_BLK_INT_STS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SPRD_DMA_TRSC_INT_STS BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SPRD_DMA_LIST_INT_STS BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SPRD_DMA_CFGERR_INT_STS BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SPRD_DMA_CHN_INT_STS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) (SPRD_DMA_FRAG_INT_STS | SPRD_DMA_BLK_INT_STS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SPRD_DMA_TRSC_INT_STS | SPRD_DMA_LIST_INT_STS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SPRD_DMA_CFGERR_INT_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* SPRD_DMA_CHN_FRG_LEN register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SPRD_DMA_SRC_DATAWIDTH_OFFSET 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SPRD_DMA_DES_DATAWIDTH_OFFSET 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SPRD_DMA_SWT_MODE_OFFSET 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SPRD_DMA_REQ_MODE_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SPRD_DMA_REQ_MODE_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SPRD_DMA_WRAP_SEL_DEST BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SPRD_DMA_WRAP_EN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SPRD_DMA_FIX_SEL_OFFSET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SPRD_DMA_FIX_EN_OFFSET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SPRD_DMA_LLIST_END BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SPRD_DMA_FRG_LEN_MASK GENMASK(16, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* SPRD_DMA_CHN_BLK_LEN register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SPRD_DMA_BLK_LEN_MASK GENMASK(16, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* SPRD_DMA_CHN_TRSC_LEN register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SPRD_DMA_TRSC_LEN_MASK GENMASK(27, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* SPRD_DMA_CHN_TRSF_STEP register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SPRD_DMA_DEST_TRSF_STEP_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SPRD_DMA_SRC_TRSF_STEP_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SPRD_DMA_TRSF_STEP_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* SPRD DMA_SRC_BLK_STEP register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SPRD_DMA_LLIST_HIGH_MASK GENMASK(31, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SPRD_DMA_LLIST_HIGH_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* define DMA channel mode & trigger mode mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SPRD_DMA_CHN_MODE_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SPRD_DMA_TRG_MODE_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SPRD_DMA_INT_TYPE_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* define the DMA transfer step type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SPRD_DMA_NONE_STEP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SPRD_DMA_BYTE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SPRD_DMA_SHORT_STEP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SPRD_DMA_WORD_STEP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SPRD_DMA_DWORD_STEP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SPRD_DMA_SOFTWARE_UID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* dma data width values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) enum sprd_dma_datawidth {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SPRD_DMA_DATAWIDTH_1_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SPRD_DMA_DATAWIDTH_2_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SPRD_DMA_DATAWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SPRD_DMA_DATAWIDTH_8_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* dma channel hardware configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct sprd_dma_chn_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 des_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 frg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 blk_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 trsc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 trsf_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 wrap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 wrap_to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 llist_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 frg_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 src_blk_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 des_blk_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* dma request description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct sprd_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct virt_dma_desc vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct sprd_dma_chn_hw chn_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) enum dma_transfer_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* dma channel description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct sprd_dma_chn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct virt_dma_chan vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void __iomem *chn_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct sprd_dma_linklist linklist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct dma_slave_config slave_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 chn_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) enum sprd_dma_chn_mode chn_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) enum sprd_dma_trg_mode trg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) enum sprd_dma_int_type int_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct sprd_dma_desc *cur_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* SPRD dma device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct sprd_dma_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct dma_device dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void __iomem *glb_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct clk *ashb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 total_chns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct sprd_dma_chn channels[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void sprd_dma_free_desc(struct virt_dma_desc *vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static bool sprd_dma_filter_fn(struct dma_chan *chan, void *param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct of_dma_filter_info sprd_dma_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .filter_fn = sprd_dma_filter_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static inline struct sprd_dma_chn *to_sprd_dma_chan(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return container_of(c, struct sprd_dma_chn, vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static inline struct sprd_dma_dev *to_sprd_dma_dev(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct sprd_dma_chn *schan = to_sprd_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return container_of(schan, struct sprd_dma_dev, channels[c->chan_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline struct sprd_dma_desc *to_sprd_dma_desc(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return container_of(vd, struct sprd_dma_desc, vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void sprd_dma_glb_update(struct sprd_dma_dev *sdev, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 orig = readl(sdev->glb_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tmp = (orig & ~mask) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) writel(tmp, sdev->glb_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void sprd_dma_chn_update(struct sprd_dma_chn *schan, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 orig = readl(schan->chn_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) tmp = (orig & ~mask) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) writel(tmp, schan->chn_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int sprd_dma_enable(struct sprd_dma_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = clk_prepare_enable(sdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * The ashb_clk is optional and only for AGCP DMA controller, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * need add one condition to check if the ashb_clk need enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!IS_ERR(sdev->ashb_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = clk_prepare_enable(sdev->ashb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void sprd_dma_disable(struct sprd_dma_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) clk_disable_unprepare(sdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Need to check if we need disable the optional ashb_clk for AGCP DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!IS_ERR(sdev->ashb_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clk_disable_unprepare(sdev->ashb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void sprd_dma_set_uid(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 dev_id = schan->dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (dev_id != SPRD_DMA_SOFTWARE_UID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 uid_offset = SPRD_DMA_GLB_REQ_UID_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) SPRD_DMA_GLB_REQ_UID(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) writel(schan->chn_num + 1, sdev->glb_base + uid_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void sprd_dma_unset_uid(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 dev_id = schan->dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (dev_id != SPRD_DMA_SOFTWARE_UID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 uid_offset = SPRD_DMA_GLB_REQ_UID_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SPRD_DMA_GLB_REQ_UID(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) writel(0, sdev->glb_base + uid_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static void sprd_dma_clear_int(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) sprd_dma_chn_update(schan, SPRD_DMA_CHN_INTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) SPRD_DMA_INT_MASK << SPRD_DMA_INT_CLR_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) SPRD_DMA_INT_MASK << SPRD_DMA_INT_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void sprd_dma_enable_chn(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) sprd_dma_chn_update(schan, SPRD_DMA_CHN_CFG, SPRD_DMA_CHN_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SPRD_DMA_CHN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void sprd_dma_disable_chn(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) sprd_dma_chn_update(schan, SPRD_DMA_CHN_CFG, SPRD_DMA_CHN_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void sprd_dma_soft_request(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) sprd_dma_chn_update(schan, SPRD_DMA_CHN_REQ, SPRD_DMA_REQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) SPRD_DMA_REQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void sprd_dma_pause_resume(struct sprd_dma_chn *schan, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 pause, timeout = SPRD_DMA_PAUSE_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) sprd_dma_chn_update(schan, SPRD_DMA_CHN_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SPRD_DMA_PAUSE_EN, SPRD_DMA_PAUSE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pause = readl(schan->chn_base + SPRD_DMA_CHN_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (pause & SPRD_DMA_PAUSE_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } while (--timeout > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_warn(sdev->dma_dev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "pause dma controller timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) sprd_dma_chn_update(schan, SPRD_DMA_CHN_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SPRD_DMA_PAUSE_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void sprd_dma_stop_and_disable(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 cfg = readl(schan->chn_base + SPRD_DMA_CHN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (!(cfg & SPRD_DMA_CHN_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) sprd_dma_pause_resume(schan, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) sprd_dma_disable_chn(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static unsigned long sprd_dma_get_src_addr(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned long addr, addr_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) addr = readl(schan->chn_base + SPRD_DMA_CHN_SRC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) addr_high = readl(schan->chn_base + SPRD_DMA_CHN_WARP_PTR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) SPRD_DMA_HIGH_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return addr | (addr_high << SPRD_DMA_HIGH_ADDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static unsigned long sprd_dma_get_dst_addr(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned long addr, addr_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) addr = readl(schan->chn_base + SPRD_DMA_CHN_DES_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) addr_high = readl(schan->chn_base + SPRD_DMA_CHN_WARP_TO) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) SPRD_DMA_HIGH_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return addr | (addr_high << SPRD_DMA_HIGH_ADDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static enum sprd_dma_int_type sprd_dma_get_int_type(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 intc_sts = readl(schan->chn_base + SPRD_DMA_CHN_INTC) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) SPRD_DMA_CHN_INT_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) switch (intc_sts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case SPRD_DMA_CFGERR_INT_STS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return SPRD_DMA_CFGERR_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case SPRD_DMA_LIST_INT_STS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return SPRD_DMA_LIST_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case SPRD_DMA_TRSC_INT_STS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return SPRD_DMA_TRANS_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case SPRD_DMA_BLK_INT_STS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return SPRD_DMA_BLK_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case SPRD_DMA_FRAG_INT_STS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return SPRD_DMA_FRAG_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_warn(sdev->dma_dev.dev, "incorrect dma interrupt type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return SPRD_DMA_NO_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static enum sprd_dma_req_mode sprd_dma_get_req_type(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 frag_reg = readl(schan->chn_base + SPRD_DMA_CHN_FRG_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return (frag_reg >> SPRD_DMA_REQ_MODE_OFFSET) & SPRD_DMA_REQ_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 val, chn = schan->chn_num + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) switch (schan->chn_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case SPRD_DMA_SRC_CHN0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) val |= SPRD_DMA_GLB_2STAGE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (schan->int_type != SPRD_DMA_NO_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) val |= SPRD_DMA_GLB_SRC_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case SPRD_DMA_SRC_CHN1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) val |= SPRD_DMA_GLB_2STAGE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (schan->int_type != SPRD_DMA_NO_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) val |= SPRD_DMA_GLB_SRC_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case SPRD_DMA_DST_CHN0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) SPRD_DMA_GLB_DEST_CHN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) val |= SPRD_DMA_GLB_2STAGE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (schan->int_type != SPRD_DMA_NO_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) val |= SPRD_DMA_GLB_DEST_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case SPRD_DMA_DST_CHN1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) SPRD_DMA_GLB_DEST_CHN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) val |= SPRD_DMA_GLB_2STAGE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (schan->int_type != SPRD_DMA_NO_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) val |= SPRD_DMA_GLB_DEST_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_err(sdev->dma_dev.dev, "invalid channel mode setting %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) schan->chn_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static void sprd_dma_set_pending(struct sprd_dma_chn *schan, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 reg, val, req_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (schan->dev_id == SPRD_DMA_SOFTWARE_UID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* The DMA request id always starts from 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) req_id = schan->dev_id - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (req_id < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) reg = SPRD_DMA_GLB_REQ_PEND0_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) val = BIT(req_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) reg = SPRD_DMA_GLB_REQ_PEND1_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) val = BIT(req_id - 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) sprd_dma_glb_update(sdev, reg, val, enable ? val : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static void sprd_dma_set_chn_config(struct sprd_dma_chn *schan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct sprd_dma_desc *sdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct sprd_dma_chn_hw *cfg = &sdesc->chn_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) writel(cfg->pause, schan->chn_base + SPRD_DMA_CHN_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) writel(cfg->cfg, schan->chn_base + SPRD_DMA_CHN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) writel(cfg->intc, schan->chn_base + SPRD_DMA_CHN_INTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) writel(cfg->src_addr, schan->chn_base + SPRD_DMA_CHN_SRC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) writel(cfg->des_addr, schan->chn_base + SPRD_DMA_CHN_DES_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) writel(cfg->frg_len, schan->chn_base + SPRD_DMA_CHN_FRG_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) writel(cfg->blk_len, schan->chn_base + SPRD_DMA_CHN_BLK_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) writel(cfg->trsc_len, schan->chn_base + SPRD_DMA_CHN_TRSC_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) writel(cfg->trsf_step, schan->chn_base + SPRD_DMA_CHN_TRSF_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) writel(cfg->wrap_ptr, schan->chn_base + SPRD_DMA_CHN_WARP_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) writel(cfg->wrap_to, schan->chn_base + SPRD_DMA_CHN_WARP_TO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) writel(cfg->llist_ptr, schan->chn_base + SPRD_DMA_CHN_LLIST_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) writel(cfg->frg_step, schan->chn_base + SPRD_DMA_CHN_FRAG_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) writel(cfg->src_blk_step, schan->chn_base + SPRD_DMA_CHN_SRC_BLK_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) writel(cfg->des_blk_step, schan->chn_base + SPRD_DMA_CHN_DES_BLK_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) writel(cfg->req, schan->chn_base + SPRD_DMA_CHN_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static void sprd_dma_start(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct virt_dma_desc *vd = vchan_next_desc(&schan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (!vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) list_del(&vd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) schan->cur_desc = to_sprd_dma_desc(vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * Set 2-stage configuration if the channel starts one 2-stage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (schan->chn_mode && sprd_dma_set_2stage_config(schan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * Copy the DMA configuration from DMA descriptor to this hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) sprd_dma_set_chn_config(schan, schan->cur_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) sprd_dma_set_uid(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) sprd_dma_set_pending(schan, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) sprd_dma_enable_chn(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (schan->dev_id == SPRD_DMA_SOFTWARE_UID &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) schan->chn_mode != SPRD_DMA_DST_CHN0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) schan->chn_mode != SPRD_DMA_DST_CHN1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) sprd_dma_soft_request(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static void sprd_dma_stop(struct sprd_dma_chn *schan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) sprd_dma_stop_and_disable(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) sprd_dma_set_pending(schan, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) sprd_dma_unset_uid(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) sprd_dma_clear_int(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) schan->cur_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static bool sprd_dma_check_trans_done(struct sprd_dma_desc *sdesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) enum sprd_dma_int_type int_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) enum sprd_dma_req_mode req_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (int_type == SPRD_DMA_NO_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (int_type >= req_mode + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static irqreturn_t dma_irq_handle(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct sprd_dma_dev *sdev = (struct sprd_dma_dev *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 irq_status = readl(sdev->glb_base + SPRD_DMA_GLB_INT_MSK_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct sprd_dma_chn *schan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct sprd_dma_desc *sdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) enum sprd_dma_req_mode req_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) enum sprd_dma_int_type int_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) bool trans_done = false, cyclic = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) while (irq_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) i = __ffs(irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) irq_status &= (irq_status - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) schan = &sdev->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) spin_lock(&schan->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) sdesc = schan->cur_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!sdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) spin_unlock(&schan->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int_type = sprd_dma_get_int_type(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) req_type = sprd_dma_get_req_type(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) sprd_dma_clear_int(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* cyclic mode schedule callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) cyclic = schan->linklist.phy_addr ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (cyclic == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) vchan_cyclic_callback(&sdesc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Check if the dma request descriptor is done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) trans_done = sprd_dma_check_trans_done(sdesc, int_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) req_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (trans_done == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) vchan_cookie_complete(&sdesc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) schan->cur_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) sprd_dma_start(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) spin_unlock(&schan->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int sprd_dma_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return pm_runtime_get_sync(chan->device->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void sprd_dma_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct virt_dma_desc *cur_vd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) spin_lock_irqsave(&schan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (schan->cur_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) cur_vd = &schan->cur_desc->vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) sprd_dma_stop(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) spin_unlock_irqrestore(&schan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (cur_vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) sprd_dma_free_desc(cur_vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) vchan_free_chan_resources(&schan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) pm_runtime_put(chan->device->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static enum dma_status sprd_dma_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct virt_dma_desc *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) enum dma_status ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u32 pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ret == DMA_COMPLETE || !txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) spin_lock_irqsave(&schan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) vd = vchan_find_desc(&schan->vc, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (vd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct sprd_dma_desc *sdesc = to_sprd_dma_desc(vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct sprd_dma_chn_hw *hw = &sdesc->chn_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (hw->trsc_len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) pos = hw->trsc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) else if (hw->blk_len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) pos = hw->blk_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) else if (hw->frg_len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) pos = hw->frg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) } else if (schan->cur_desc && schan->cur_desc->vd.tx.cookie == cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct sprd_dma_desc *sdesc = schan->cur_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (sdesc->dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pos = sprd_dma_get_dst_addr(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) pos = sprd_dma_get_src_addr(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) spin_unlock_irqrestore(&schan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dma_set_residue(txstate, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static void sprd_dma_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) spin_lock_irqsave(&schan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (vchan_issue_pending(&schan->vc) && !schan->cur_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) sprd_dma_start(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) spin_unlock_irqrestore(&schan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static int sprd_dma_get_datawidth(enum dma_slave_buswidth buswidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) switch (buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) case DMA_SLAVE_BUSWIDTH_8_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return ffs(buswidth) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int sprd_dma_get_step(enum dma_slave_buswidth buswidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) switch (buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) case DMA_SLAVE_BUSWIDTH_8_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int sprd_dma_fill_desc(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct sprd_dma_chn_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) unsigned int sglen, int sg_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dma_addr_t src, dma_addr_t dst, u32 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct dma_slave_config *slave_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct sprd_dma_dev *sdev = to_sprd_dma_dev(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) enum sprd_dma_chn_mode chn_mode = schan->chn_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 req_mode = (flags >> SPRD_DMA_REQ_SHIFT) & SPRD_DMA_REQ_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u32 int_mode = flags & SPRD_DMA_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int src_datawidth, dst_datawidth, src_step, dst_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u32 temp, fix_mode = 0, fix_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) phys_addr_t llist_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) src_step = sprd_dma_get_step(slave_cfg->src_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (src_step < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dev_err(sdev->dma_dev.dev, "invalid source step\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return src_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * For 2-stage transfer, destination channel step can not be 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * since destination device is AON IRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (chn_mode == SPRD_DMA_DST_CHN0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) chn_mode == SPRD_DMA_DST_CHN1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dst_step = src_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dst_step = SPRD_DMA_NONE_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dst_step = sprd_dma_get_step(slave_cfg->dst_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (dst_step < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dev_err(sdev->dma_dev.dev, "invalid destination step\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return dst_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) src_step = SPRD_DMA_NONE_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) src_datawidth = sprd_dma_get_datawidth(slave_cfg->src_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (src_datawidth < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dev_err(sdev->dma_dev.dev, "invalid source datawidth\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return src_datawidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dst_datawidth = sprd_dma_get_datawidth(slave_cfg->dst_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (dst_datawidth < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_err(sdev->dma_dev.dev, "invalid destination datawidth\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return dst_datawidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (slave_cfg->slave_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) schan->dev_id = slave_cfg->slave_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * wrap_ptr and wrap_to will save the high 4 bits source address and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * destination address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) hw->wrap_ptr = (src >> SPRD_DMA_HIGH_ADDR_OFFSET) & SPRD_DMA_HIGH_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) hw->wrap_to = (dst >> SPRD_DMA_HIGH_ADDR_OFFSET) & SPRD_DMA_HIGH_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) hw->src_addr = src & SPRD_DMA_LOW_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) hw->des_addr = dst & SPRD_DMA_LOW_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * If the src step and dst step both are 0 or both are not 0, that means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * we can not enable the fix mode. If one is 0 and another one is not,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * we can enable the fix mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if ((src_step != 0 && dst_step != 0) || (src_step | dst_step) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) fix_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) fix_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (src_step)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) fix_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) fix_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) hw->intc = int_mode | SPRD_DMA_CFG_ERR_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) temp = src_datawidth << SPRD_DMA_SRC_DATAWIDTH_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) temp |= dst_datawidth << SPRD_DMA_DES_DATAWIDTH_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) temp |= req_mode << SPRD_DMA_REQ_MODE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) temp |= fix_mode << SPRD_DMA_FIX_SEL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) temp |= fix_en << SPRD_DMA_FIX_EN_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) temp |= schan->linklist.wrap_addr ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) SPRD_DMA_WRAP_EN | SPRD_DMA_WRAP_SEL_DEST : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) temp |= slave_cfg->src_maxburst & SPRD_DMA_FRG_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) hw->frg_len = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) hw->blk_len = slave_cfg->src_maxburst & SPRD_DMA_BLK_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) hw->trsc_len = len & SPRD_DMA_TRSC_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) temp = (dst_step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_DEST_TRSF_STEP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) temp |= (src_step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_SRC_TRSF_STEP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) hw->trsf_step = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* link-list configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (schan->linklist.phy_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) hw->cfg |= SPRD_DMA_LINKLIST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* link-list index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) temp = sglen ? (sg_index + 1) % sglen : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* Next link-list configuration's physical address offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) temp = temp * sizeof(*hw) + SPRD_DMA_CHN_SRC_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * Set the link-list pointer point to next link-list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * configuration's physical address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) llist_ptr = schan->linklist.phy_addr + temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) hw->llist_ptr = lower_32_bits(llist_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) hw->src_blk_step = (upper_32_bits(llist_ptr) << SPRD_DMA_LLIST_HIGH_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) SPRD_DMA_LLIST_HIGH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (schan->linklist.wrap_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) hw->wrap_ptr |= schan->linklist.wrap_addr &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) SPRD_DMA_WRAP_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) hw->wrap_to |= dst & SPRD_DMA_WRAP_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) hw->llist_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) hw->src_blk_step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) hw->frg_step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) hw->des_blk_step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static int sprd_dma_fill_linklist_desc(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) unsigned int sglen, int sg_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dma_addr_t src, dma_addr_t dst, u32 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct dma_slave_config *slave_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct sprd_dma_chn_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (!schan->linklist.virt_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) hw = (struct sprd_dma_chn_hw *)(schan->linklist.virt_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) sg_index * sizeof(*hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return sprd_dma_fill_desc(chan, hw, sglen, sg_index, src, dst, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dir, flags, slave_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) sprd_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct sprd_dma_desc *sdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct sprd_dma_chn_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) enum sprd_dma_datawidth datawidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) u32 step, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (!sdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) hw = &sdesc->chn_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) hw->intc = SPRD_DMA_TRANS_INT | SPRD_DMA_CFG_ERR_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) hw->src_addr = src & SPRD_DMA_LOW_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) hw->des_addr = dest & SPRD_DMA_LOW_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) hw->wrap_ptr = (src >> SPRD_DMA_HIGH_ADDR_OFFSET) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) SPRD_DMA_HIGH_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) hw->wrap_to = (dest >> SPRD_DMA_HIGH_ADDR_OFFSET) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) SPRD_DMA_HIGH_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (IS_ALIGNED(len, 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) datawidth = SPRD_DMA_DATAWIDTH_8_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) step = SPRD_DMA_DWORD_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) } else if (IS_ALIGNED(len, 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) datawidth = SPRD_DMA_DATAWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) step = SPRD_DMA_WORD_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) } else if (IS_ALIGNED(len, 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) datawidth = SPRD_DMA_DATAWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) step = SPRD_DMA_SHORT_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) datawidth = SPRD_DMA_DATAWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) step = SPRD_DMA_BYTE_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) temp = datawidth << SPRD_DMA_SRC_DATAWIDTH_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) temp |= datawidth << SPRD_DMA_DES_DATAWIDTH_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) temp |= SPRD_DMA_TRANS_REQ << SPRD_DMA_REQ_MODE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) temp |= len & SPRD_DMA_FRG_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) hw->frg_len = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) hw->blk_len = len & SPRD_DMA_BLK_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) hw->trsc_len = len & SPRD_DMA_TRSC_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) temp = (step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_DEST_TRSF_STEP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) temp |= (step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_SRC_TRSF_STEP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) hw->trsf_step = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return vchan_tx_prep(&schan->vc, &sdesc->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) sprd_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) unsigned int sglen, enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct dma_slave_config *slave_cfg = &schan->slave_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dma_addr_t src = 0, dst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dma_addr_t start_src = 0, start_dst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct sprd_dma_desc *sdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u32 len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (!is_slave_direction(dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (context) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct sprd_dma_linklist *ll_cfg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) (struct sprd_dma_linklist *)context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) schan->linklist.phy_addr = ll_cfg->phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) schan->linklist.virt_addr = ll_cfg->virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) schan->linklist.wrap_addr = ll_cfg->wrap_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) schan->linklist.phy_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) schan->linklist.virt_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) schan->linklist.wrap_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * Set channel mode, interrupt mode and trigger mode for 2-stage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) schan->chn_mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) (flags >> SPRD_DMA_CHN_MODE_SHIFT) & SPRD_DMA_CHN_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) schan->trg_mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) (flags >> SPRD_DMA_TRG_MODE_SHIFT) & SPRD_DMA_TRG_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) schan->int_type = flags & SPRD_DMA_INT_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (!sdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) sdesc->dir = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) for_each_sg(sgl, sg, sglen, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) src = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) dst = slave_cfg->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) src = slave_cfg->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dst = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (!i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) start_src = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) start_dst = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * The link-list mode needs at least 2 link-list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * configurations. If there is only one sg, it doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * need to fill the link-list configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (sglen < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ret = sprd_dma_fill_linklist_desc(chan, sglen, i, src, dst, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dir, flags, slave_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) kfree(sdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = sprd_dma_fill_desc(chan, &sdesc->chn_hw, 0, 0, start_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) start_dst, len, dir, flags, slave_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) kfree(sdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return vchan_tx_prep(&schan->vc, &sdesc->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static int sprd_dma_slave_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct dma_slave_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct dma_slave_config *slave_cfg = &schan->slave_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) memcpy(slave_cfg, config, sizeof(*config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static int sprd_dma_pause(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) spin_lock_irqsave(&schan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) sprd_dma_pause_resume(schan, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) spin_unlock_irqrestore(&schan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static int sprd_dma_resume(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) spin_lock_irqsave(&schan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) sprd_dma_pause_resume(schan, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) spin_unlock_irqrestore(&schan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static int sprd_dma_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct virt_dma_desc *cur_vd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) spin_lock_irqsave(&schan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (schan->cur_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) cur_vd = &schan->cur_desc->vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) sprd_dma_stop(schan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) vchan_get_all_descriptors(&schan->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) spin_unlock_irqrestore(&schan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (cur_vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) sprd_dma_free_desc(cur_vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) vchan_dma_desc_free_list(&schan->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static void sprd_dma_free_desc(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct sprd_dma_desc *sdesc = to_sprd_dma_desc(vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) kfree(sdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static bool sprd_dma_filter_fn(struct dma_chan *chan, void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) u32 slave_id = *(u32 *)param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) schan->dev_id = slave_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static int sprd_dma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct sprd_dma_dev *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct sprd_dma_chn *dma_chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) u32 chn_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ret = device_property_read_u32(&pdev->dev, "#dma-channels", &chn_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dev_err(&pdev->dev, "get dma channels count failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) sdev = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct_size(sdev, channels, chn_count),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (!sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) sdev->clk = devm_clk_get(&pdev->dev, "enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (IS_ERR(sdev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dev_err(&pdev->dev, "get enable clock failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return PTR_ERR(sdev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* ashb clock is optional for AGCP DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) sdev->ashb_clk = devm_clk_get(&pdev->dev, "ashb_eb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (IS_ERR(sdev->ashb_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) dev_warn(&pdev->dev, "no optional ashb eb clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * We have three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * DMA controller, it can or do not request the irq, which will save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * system power without resuming system by DMA interrupts if AGCP DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * does not request the irq. Thus the DMA interrupts property should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * be optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) sdev->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (sdev->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ret = devm_request_irq(&pdev->dev, sdev->irq, dma_irq_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) 0, "sprd_dma", (void *)sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) dev_err(&pdev->dev, "request dma irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) dev_warn(&pdev->dev, "no interrupts for the dma controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) sdev->glb_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (IS_ERR(sdev->glb_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return PTR_ERR(sdev->glb_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) dma_cap_set(DMA_MEMCPY, sdev->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) sdev->total_chns = chn_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) sdev->dma_dev.chancnt = chn_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) INIT_LIST_HEAD(&sdev->dma_dev.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) INIT_LIST_HEAD(&sdev->dma_dev.global_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) sdev->dma_dev.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) sdev->dma_dev.device_alloc_chan_resources = sprd_dma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) sdev->dma_dev.device_free_chan_resources = sprd_dma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) sdev->dma_dev.device_tx_status = sprd_dma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) sdev->dma_dev.device_issue_pending = sprd_dma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) sdev->dma_dev.device_prep_dma_memcpy = sprd_dma_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) sdev->dma_dev.device_prep_slave_sg = sprd_dma_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) sdev->dma_dev.device_config = sprd_dma_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) sdev->dma_dev.device_pause = sprd_dma_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) sdev->dma_dev.device_resume = sprd_dma_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) sdev->dma_dev.device_terminate_all = sprd_dma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) for (i = 0; i < chn_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) dma_chn = &sdev->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) dma_chn->chn_num = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) dma_chn->cur_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* get each channel's registers base address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dma_chn->chn_base = sdev->glb_base + SPRD_DMA_CHN_REG_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) SPRD_DMA_CHN_REG_LENGTH * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) dma_chn->vc.desc_free = sprd_dma_free_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) vchan_init(&dma_chn->vc, &sdev->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) platform_set_drvdata(pdev, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ret = sprd_dma_enable(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ret = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) goto err_rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ret = dma_async_device_register(&sdev->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dev_err(&pdev->dev, "register dma device failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) sprd_dma_info.dma_cap = sdev->dma_dev.cap_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret = of_dma_controller_register(np, of_dma_simple_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) &sprd_dma_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) goto err_of_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) err_of_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dma_async_device_unregister(&sdev->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) err_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) err_rpm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) sprd_dma_disable(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static int sprd_dma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct sprd_dma_dev *sdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct sprd_dma_chn *c, *cn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ret = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* explicitly free the irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (sdev->irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) devm_free_irq(&pdev->dev, sdev->irq, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) list_for_each_entry_safe(c, cn, &sdev->dma_dev.channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) vc.chan.device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) list_del(&c->vc.chan.device_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) tasklet_kill(&c->vc.task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) of_dma_controller_free(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dma_async_device_unregister(&sdev->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) sprd_dma_disable(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static const struct of_device_id sprd_dma_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) { .compatible = "sprd,sc9860-dma", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) MODULE_DEVICE_TABLE(of, sprd_dma_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static int __maybe_unused sprd_dma_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) struct sprd_dma_dev *sdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) sprd_dma_disable(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static int __maybe_unused sprd_dma_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct sprd_dma_dev *sdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ret = sprd_dma_enable(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) dev_err(sdev->dma_dev.dev, "enable dma failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static const struct dev_pm_ops sprd_dma_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) SET_RUNTIME_PM_OPS(sprd_dma_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) sprd_dma_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static struct platform_driver sprd_dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .probe = sprd_dma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .remove = sprd_dma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .name = "sprd-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .of_match_table = sprd_dma_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .pm = &sprd_dma_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) module_platform_driver(sprd_dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) MODULE_DESCRIPTION("DMA driver for Spreadtrum");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) MODULE_AUTHOR("Eric Long <eric.long@spreadtrum.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) MODULE_ALIAS("platform:sprd-dma");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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