Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Renesas SuperH DMA Engine support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __DMA_SHDMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __DMA_SHDMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sh_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/shdma-base.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SH_DMAE_MAX_CHANNELS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SH_DMAE_TCR_MAX 0x00FFFFFF	/* 16MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct sh_dmae_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct shdma_chan shdma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	const struct sh_dmae_slave_config *config; /* Slave DMA configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	int xmit_shift;			/* log_2(bytes_per_xfer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	char dev_id[16];		/* unique name per DMAC of channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	int pm_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	dma_addr_t slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct sh_dmae_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	struct shdma_dev shdma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	const struct sh_dmae_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	void __iomem *chan_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	void __iomem *dmars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	unsigned int chcr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	u32 chcr_ie_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct sh_dmae_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	u32 sar; /* SAR / source address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	u32 dar; /* DAR / destination address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	u32 tcr; /* TCR / transfer count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct sh_dmae_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	struct sh_dmae_regs hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	struct shdma_desc shdma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, shdma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 				     struct sh_dmae_device, shdma_dev.dma_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif	/* __DMA_SHDMA_H */