Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Renesas SuperH DMA Engine support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2013 Renesas Electronics, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef SHDMA_ARM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define SHDMA_ARM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "shdma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Transmit sizes and respective CHCR register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	XMIT_SZ_8BIT		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	XMIT_SZ_16BIT		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	XMIT_SZ_32BIT		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	XMIT_SZ_64BIT		= 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	XMIT_SZ_128BIT		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	XMIT_SZ_256BIT		= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	XMIT_SZ_512BIT		= 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* log2(size / 8) - used to calculate number of transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SH_DMAE_TS_SHIFT {		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	[XMIT_SZ_8BIT]		= 0,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	[XMIT_SZ_16BIT]		= 1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	[XMIT_SZ_32BIT]		= 2,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	[XMIT_SZ_64BIT]		= 3,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	[XMIT_SZ_128BIT]	= 4,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	[XMIT_SZ_256BIT]	= 5,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	[XMIT_SZ_512BIT]	= 6,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TS_LOW_BIT	0x3 /* --xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TS_HI_BIT	0xc /* xx-- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TS_LOW_SHIFT	(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TS_HI_SHIFT	(20 - 2)	/* 2 bits for shifted low TS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TS_INDEX2VAL(i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	 (((i) & TS_HI_BIT)  << TS_HI_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL((xmit_sz)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL((xmit_sz)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif