^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SiFive FU540 Platform DMA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2019 SiFive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based partially on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * - drivers/dma/fsl-edma.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - drivers/dma/dw-edma/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * - drivers/dma/pxa-dma.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * See the following sources for further documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - Chapter 12 "Platform DMA Engine (PDMA)" of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * SiFive FU540-C000 v1.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "sf-pdma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifndef readq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static inline unsigned long long readq(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return readl(addr) | (((unsigned long long)readl(addr + 4)) << 32LL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifndef writeq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static inline void writeq(unsigned long long v, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) writel(lower_32_bits(v), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) writel(upper_32_bits(v), addr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static inline struct sf_pdma_chan *to_sf_pdma_chan(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return container_of(dchan, struct sf_pdma_chan, vchan.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static inline struct sf_pdma_desc *to_sf_pdma_desc(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return container_of(vd, struct sf_pdma_desc, vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct sf_pdma_desc *sf_pdma_alloc_desc(struct sf_pdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct sf_pdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (chan->desc && !chan->desc->in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return chan->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) desc->chan = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void sf_pdma_fill_desc(struct sf_pdma_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u64 dst, u64 src, u64 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) desc->xfer_type = PDMA_FULL_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) desc->xfer_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) desc->dst_addr = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) desc->src_addr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void sf_pdma_disclaim_chan(struct sf_pdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct pdma_regs *regs = &chan->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writel(PDMA_CLEAR_CTRL, regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) sf_pdma_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dest, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct sf_pdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (chan && (!len || !dest || !src)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_err(chan->pdma->dma_dev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "Please check dma len, dest, src!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) desc = sf_pdma_alloc_desc(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) desc->in_use = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) desc->dirn = DMA_MEM_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) desc->async_tx = vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) chan->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sf_pdma_fill_desc(desc, dest, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return desc->async_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int sf_pdma_slave_config(struct dma_chan *dchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct dma_slave_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) memcpy(&chan->cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int sf_pdma_alloc_chan_resources(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct pdma_regs *regs = &chan->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dma_cookie_init(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel(PDMA_CLAIM_MASK, regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void sf_pdma_disable_request(struct sf_pdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct pdma_regs *regs = &chan->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel(readl(regs->ctrl) & ~PDMA_RUN_MASK, regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void sf_pdma_free_chan_resources(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) sf_pdma_disable_request(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) kfree(chan->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) chan->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) vchan_get_all_descriptors(&chan->vchan, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) sf_pdma_disclaim_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) vchan_dma_desc_free_list(&chan->vchan, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static size_t sf_pdma_desc_residue(struct sf_pdma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dma_cookie_t cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct virt_dma_desc *vd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct pdma_regs *regs = &chan->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u64 residue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct sf_pdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tx = &chan->desc->vdesc.tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (cookie == tx->chan->completed_cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (cookie == tx->cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) residue = readq(regs->residue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) vd = vchan_find_desc(&chan->vchan, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) desc = to_sf_pdma_desc(vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) residue = desc->xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static enum dma_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sf_pdma_tx_status(struct dma_chan *dchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) status = dma_cookie_status(dchan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (txstate && status != DMA_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dma_set_residue(txstate, sf_pdma_desc_residue(chan, cookie));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int sf_pdma_terminate_all(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) sf_pdma_disable_request(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) kfree(chan->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) chan->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) chan->xfer_err = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) vchan_get_all_descriptors(&chan->vchan, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) vchan_dma_desc_free_list(&chan->vchan, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void sf_pdma_enable_request(struct sf_pdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct pdma_regs *regs = &chan->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) v = PDMA_CLAIM_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PDMA_ENABLE_DONE_INT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PDMA_ENABLE_ERR_INT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PDMA_RUN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel(v, regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void sf_pdma_xfer_desc(struct sf_pdma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct sf_pdma_desc *desc = chan->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct pdma_regs *regs = &chan->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_err(chan->pdma->dma_dev.dev, "NULL desc.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writel(desc->xfer_type, regs->xfer_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) writeq(desc->xfer_size, regs->xfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) writeq(desc->dst_addr, regs->dst_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) writeq(desc->src_addr, regs->src_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) chan->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) chan->status = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) sf_pdma_enable_request(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void sf_pdma_issue_pending(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (vchan_issue_pending(&chan->vchan) && chan->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) sf_pdma_xfer_desc(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void sf_pdma_free_desc(struct virt_dma_desc *vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct sf_pdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) desc = to_sf_pdma_desc(vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) desc->in_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void sf_pdma_donebh_tasklet(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct sf_pdma_chan *chan = from_tasklet(chan, t, done_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (chan->xfer_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) chan->retries = MAX_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) chan->status = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) chan->xfer_err = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) list_del(&chan->desc->vdesc.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) vchan_cookie_complete(&chan->desc->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void sf_pdma_errbh_tasklet(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct sf_pdma_chan *chan = from_tasklet(chan, t, err_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct sf_pdma_desc *desc = chan->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (chan->retries <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* fail to recover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dmaengine_desc_get_callback_invoke(desc->async_tx, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) chan->retries--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) chan->xfer_err = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) chan->status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) sf_pdma_enable_request(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static irqreturn_t sf_pdma_done_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct sf_pdma_chan *chan = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct pdma_regs *regs = &chan->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u64 residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) spin_lock_irqsave(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) writel((readl(regs->ctrl)) & ~PDMA_DONE_STATUS_MASK, regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) residue = readq(regs->residue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!residue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) tasklet_hi_schedule(&chan->done_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* submit next trascatioin if possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct sf_pdma_desc *desc = chan->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) desc->src_addr += desc->xfer_size - residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) desc->dst_addr += desc->xfer_size - residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) desc->xfer_size = residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) sf_pdma_xfer_desc(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) spin_unlock_irqrestore(&chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static irqreturn_t sf_pdma_err_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct sf_pdma_chan *chan = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct pdma_regs *regs = &chan->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) writel((readl(regs->ctrl)) & ~PDMA_ERR_STATUS_MASK, regs->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) tasklet_schedule(&chan->err_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * sf_pdma_irq_init() - Init PDMA IRQ Handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * @pdev: pointer of platform_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * @pdma: pointer of PDMA engine. Caller should check NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Initialize DONE and ERROR interrupt handler for 4 channels. Caller should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * make sure the pointer passed in are non-NULL. This function should be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * only one time during the device probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * Context: Any context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * * 0 - OK to init all IRQ handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * * -EINVAL - Fail to request IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int sf_pdma_irq_init(struct platform_device *pdev, struct sf_pdma *pdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int irq, r, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct sf_pdma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) for (i = 0; i < pdma->n_chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) chan = &pdma->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) irq = platform_get_irq(pdev, i * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_err(&pdev->dev, "ch(%d) Can't get done irq.\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) r = devm_request_irq(&pdev->dev, irq, sf_pdma_done_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_name(&pdev->dev), (void *)chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(&pdev->dev, "Fail to attach done ISR: %d\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) chan->txirq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) irq = platform_get_irq(pdev, (i * 2) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(&pdev->dev, "ch(%d) Can't get err irq.\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) r = devm_request_irq(&pdev->dev, irq, sf_pdma_err_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_name(&pdev->dev), (void *)chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_err(&pdev->dev, "Fail to attach err ISR: %d\n", r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) chan->errirq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * sf_pdma_setup_chans() - Init settings of each channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * @pdma: pointer of PDMA engine. Caller should check NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Initialize all data structure and register base. Caller should make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * the pointer passed in are non-NULL. This function should be called only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * one time during the device probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * Context: Any context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * Return: none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static void sf_pdma_setup_chans(struct sf_pdma *pdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct sf_pdma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) INIT_LIST_HEAD(&pdma->dma_dev.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) for (i = 0; i < pdma->n_chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) chan = &pdma->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) chan->regs.ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) SF_PDMA_REG_BASE(i) + PDMA_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) chan->regs.xfer_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) SF_PDMA_REG_BASE(i) + PDMA_XFER_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) chan->regs.xfer_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) SF_PDMA_REG_BASE(i) + PDMA_XFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) chan->regs.dst_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) SF_PDMA_REG_BASE(i) + PDMA_DST_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) chan->regs.src_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) SF_PDMA_REG_BASE(i) + PDMA_SRC_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) chan->regs.act_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) SF_PDMA_REG_BASE(i) + PDMA_ACT_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) chan->regs.residue =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) SF_PDMA_REG_BASE(i) + PDMA_REMAINING_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) chan->regs.cur_dst_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) SF_PDMA_REG_BASE(i) + PDMA_CUR_DST_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) chan->regs.cur_src_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) SF_PDMA_REG_BASE(i) + PDMA_CUR_SRC_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) chan->pdma = pdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) chan->pm_state = RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) chan->slave_id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) chan->xfer_err = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) spin_lock_init(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) chan->vchan.desc_free = sf_pdma_free_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) vchan_init(&chan->vchan, &pdma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) writel(PDMA_CLEAR_CTRL, chan->regs.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) tasklet_setup(&chan->done_tasklet, sf_pdma_donebh_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) tasklet_setup(&chan->err_tasklet, sf_pdma_errbh_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int sf_pdma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct sf_pdma *pdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct sf_pdma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int len, chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) const enum dma_slave_buswidth widths =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) DMA_SLAVE_BUSWIDTH_4_BYTES | DMA_SLAVE_BUSWIDTH_8_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) DMA_SLAVE_BUSWIDTH_16_BYTES | DMA_SLAVE_BUSWIDTH_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DMA_SLAVE_BUSWIDTH_64_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) chans = PDMA_NR_CH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) len = sizeof(*pdma) + sizeof(*chan) * chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!pdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pdma->n_chans = chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) pdma->membase = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (IS_ERR(pdma->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return PTR_ERR(pdma->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = sf_pdma_irq_init(pdev, pdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) sf_pdma_setup_chans(pdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pdma->dma_dev.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Setup capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dma_cap_set(DMA_MEMCPY, pdma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pdma->dma_dev.copy_align = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pdma->dma_dev.src_addr_widths = widths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pdma->dma_dev.dst_addr_widths = widths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) pdma->dma_dev.directions = BIT(DMA_MEM_TO_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pdma->dma_dev.descriptor_reuse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Setup DMA APIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pdma->dma_dev.device_alloc_chan_resources =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) sf_pdma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pdma->dma_dev.device_free_chan_resources =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) sf_pdma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pdma->dma_dev.device_tx_status = sf_pdma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pdma->dma_dev.device_prep_dma_memcpy = sf_pdma_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pdma->dma_dev.device_config = sf_pdma_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pdma->dma_dev.device_terminate_all = sf_pdma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pdma->dma_dev.device_issue_pending = sf_pdma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) platform_set_drvdata(pdev, pdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) "Failed to set DMA mask. Fall back to default.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = dma_async_device_register(&pdma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "Can't register SiFive Platform DMA. (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int sf_pdma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct sf_pdma *pdma = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct sf_pdma_chan *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) for (i = 0; i < PDMA_NR_CH; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ch = &pdma->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) devm_free_irq(&pdev->dev, ch->txirq, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) devm_free_irq(&pdev->dev, ch->errirq, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) list_del(&ch->vchan.chan.device_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) tasklet_kill(&ch->vchan.task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) tasklet_kill(&ch->done_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) tasklet_kill(&ch->err_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dma_async_device_unregister(&pdma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static const struct of_device_id sf_pdma_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { .compatible = "sifive,fu540-c000-pdma" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) MODULE_DEVICE_TABLE(of, sf_pdma_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static struct platform_driver sf_pdma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .probe = sf_pdma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .remove = sf_pdma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .name = "sf-pdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .of_match_table = of_match_ptr(sf_pdma_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int __init sf_pdma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return platform_driver_register(&sf_pdma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static void __exit sf_pdma_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) platform_driver_unregister(&sf_pdma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* do early init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) subsys_initcall(sf_pdma_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) module_exit(sf_pdma_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MODULE_DESCRIPTION("SiFive Platform DMA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MODULE_AUTHOR("Green Wan <green.wan@sifive.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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