Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Qualcomm Technologies HIDMA DMA engine Management interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "hidma_mgmt.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define HIDMA_QOS_N_OFFSET		0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define HIDMA_CFG_OFFSET		0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define HIDMA_MAX_BUS_REQ_LEN_OFFSET	0x41C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define HIDMA_MAX_XACTIONS_OFFSET	0x420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define HIDMA_HW_VERSION_OFFSET	0x424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define HIDMA_CHRESET_TIMEOUT_OFFSET	0x418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define HIDMA_MAX_WR_XACTIONS_MASK	GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define HIDMA_MAX_RD_XACTIONS_MASK	GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define HIDMA_WEIGHT_MASK		GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define HIDMA_MAX_BUS_REQ_LEN_MASK	GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define HIDMA_CHRESET_TIMEOUT_MASK	GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define HIDMA_MAX_WR_XACTIONS_BIT_POS	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define HIDMA_MAX_BUS_WR_REQ_BIT_POS	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define HIDMA_WRR_BIT_POS		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define HIDMA_PRIORITY_BIT_POS		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define HIDMA_AUTOSUSPEND_TIMEOUT	2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define HIDMA_MAX_CHANNEL_WEIGHT	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static unsigned int max_write_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) module_param(max_write_request, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) MODULE_PARM_DESC(max_write_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		"maximum write burst (default: ACPI/DT value)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static unsigned int max_read_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) module_param(max_read_request, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) MODULE_PARM_DESC(max_read_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		"maximum read burst (default: ACPI/DT value)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static unsigned int max_wr_xactions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) module_param(max_wr_xactions, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) MODULE_PARM_DESC(max_wr_xactions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	"maximum number of write transactions (default: ACPI/DT value)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static unsigned int max_rd_xactions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) module_param(max_rd_xactions, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) MODULE_PARM_DESC(max_rd_xactions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	"maximum number of read transactions (default: ACPI/DT value)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (!is_power_of_2(mgmtdev->max_write_request) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	    (mgmtdev->max_write_request < 128) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	    (mgmtdev->max_write_request > 1024)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			mgmtdev->max_write_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (!is_power_of_2(mgmtdev->max_read_request) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	    (mgmtdev->max_read_request < 128) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	    (mgmtdev->max_read_request > 1024)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		dev_err(&mgmtdev->pdev->dev, "invalid read request %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			mgmtdev->max_read_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (mgmtdev->max_wr_xactions > HIDMA_MAX_WR_XACTIONS_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		dev_err(&mgmtdev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			"max_wr_xactions cannot be bigger than %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			HIDMA_MAX_WR_XACTIONS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (mgmtdev->max_rd_xactions > HIDMA_MAX_RD_XACTIONS_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		dev_err(&mgmtdev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			"max_rd_xactions cannot be bigger than %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			HIDMA_MAX_RD_XACTIONS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	for (i = 0; i < mgmtdev->dma_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		if (mgmtdev->priority[i] > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			dev_err(&mgmtdev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 				"priority can be 0 or 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		if (mgmtdev->weight[i] > HIDMA_MAX_CHANNEL_WEIGHT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			dev_err(&mgmtdev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				"max value of weight can be %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				HIDMA_MAX_CHANNEL_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		/* weight needs to be at least one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		if (mgmtdev->weight[i] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			mgmtdev->weight[i] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	pm_runtime_get_sync(&mgmtdev->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	val &= ~(HIDMA_MAX_BUS_REQ_LEN_MASK << HIDMA_MAX_BUS_WR_REQ_BIT_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	val &= ~HIDMA_MAX_BUS_REQ_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	val |= mgmtdev->max_read_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	val &= ~(HIDMA_MAX_WR_XACTIONS_MASK << HIDMA_MAX_WR_XACTIONS_BIT_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	val &= ~HIDMA_MAX_RD_XACTIONS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	val |= mgmtdev->max_rd_xactions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	mgmtdev->hw_version =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	    readl(mgmtdev->virtaddr + HIDMA_HW_VERSION_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	mgmtdev->hw_version_major = (mgmtdev->hw_version >> 28) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	mgmtdev->hw_version_minor = (mgmtdev->hw_version >> 16) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	for (i = 0; i < mgmtdev->dma_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		u32 weight = mgmtdev->weight[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		u32 priority = mgmtdev->priority[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		val &= ~(1 << HIDMA_PRIORITY_BIT_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		val |= (priority & 0x1) << HIDMA_PRIORITY_BIT_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		val &= ~(HIDMA_WEIGHT_MASK << HIDMA_WRR_BIT_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		val |= (weight & HIDMA_WEIGHT_MASK) << HIDMA_WRR_BIT_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	val &= ~HIDMA_CHRESET_TIMEOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	pm_runtime_mark_last_busy(&mgmtdev->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	pm_runtime_put_autosuspend(&mgmtdev->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) EXPORT_SYMBOL_GPL(hidma_mgmt_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int hidma_mgmt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct hidma_mgmt_dev *mgmtdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	void __iomem *virtaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	virtaddr = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (IS_ERR(virtaddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		rc = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	mgmtdev = devm_kzalloc(&pdev->dev, sizeof(*mgmtdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (!mgmtdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	mgmtdev->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	mgmtdev->addrsize = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	mgmtdev->virtaddr = virtaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	rc = device_property_read_u32(&pdev->dev, "dma-channels",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				      &mgmtdev->dma_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		dev_err(&pdev->dev, "number of channels missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	rc = device_property_read_u32(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				      "channel-reset-timeout-cycles",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				      &mgmtdev->chreset_timeout_cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		dev_err(&pdev->dev, "channel reset timeout missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	rc = device_property_read_u32(&pdev->dev, "max-write-burst-bytes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 				      &mgmtdev->max_write_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		dev_err(&pdev->dev, "max-write-burst-bytes missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (max_write_request &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			(max_write_request != mgmtdev->max_write_request)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		dev_info(&pdev->dev, "overriding max-write-burst-bytes: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			max_write_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		mgmtdev->max_write_request = max_write_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		max_write_request = mgmtdev->max_write_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	rc = device_property_read_u32(&pdev->dev, "max-read-burst-bytes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 				      &mgmtdev->max_read_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		dev_err(&pdev->dev, "max-read-burst-bytes missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (max_read_request &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			(max_read_request != mgmtdev->max_read_request)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		dev_info(&pdev->dev, "overriding max-read-burst-bytes: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			max_read_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		mgmtdev->max_read_request = max_read_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		max_read_request = mgmtdev->max_read_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	rc = device_property_read_u32(&pdev->dev, "max-write-transactions",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 				      &mgmtdev->max_wr_xactions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		dev_err(&pdev->dev, "max-write-transactions missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (max_wr_xactions &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			(max_wr_xactions != mgmtdev->max_wr_xactions)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		dev_info(&pdev->dev, "overriding max-write-transactions: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			max_wr_xactions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		mgmtdev->max_wr_xactions = max_wr_xactions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		max_wr_xactions = mgmtdev->max_wr_xactions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	rc = device_property_read_u32(&pdev->dev, "max-read-transactions",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				      &mgmtdev->max_rd_xactions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		dev_err(&pdev->dev, "max-read-transactions missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (max_rd_xactions &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			(max_rd_xactions != mgmtdev->max_rd_xactions)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		dev_info(&pdev->dev, "overriding max-read-transactions: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			max_rd_xactions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		mgmtdev->max_rd_xactions = max_rd_xactions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		max_rd_xactions = mgmtdev->max_rd_xactions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	mgmtdev->priority = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 					 mgmtdev->dma_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 					 sizeof(*mgmtdev->priority),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 					 GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (!mgmtdev->priority) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	mgmtdev->weight = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 				       mgmtdev->dma_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 				       sizeof(*mgmtdev->weight), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (!mgmtdev->weight) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	rc = hidma_mgmt_setup(mgmtdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		dev_err(&pdev->dev, "setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/* start the HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	val |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	rc = hidma_mgmt_init_sys(mgmtdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		dev_err(&pdev->dev, "sysfs setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		 "HW rev: %d.%d @ %pa with %d physical channels\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		 mgmtdev->hw_version_major, mgmtdev->hw_version_minor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		 &res->start, mgmtdev->dma_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	platform_set_drvdata(pdev, mgmtdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	pm_runtime_mark_last_busy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	pm_runtime_put_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	pm_runtime_put_sync_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #if IS_ENABLED(CONFIG_ACPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct acpi_device_id hidma_mgmt_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	{"QCOM8060"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MODULE_DEVICE_TABLE(acpi, hidma_mgmt_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct of_device_id hidma_mgmt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	{.compatible = "qcom,hidma-mgmt-1.0",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MODULE_DEVICE_TABLE(of, hidma_mgmt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct platform_driver hidma_mgmt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.probe = hidma_mgmt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		   .name = "hidma-mgmt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		   .of_match_table = hidma_mgmt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		   .acpi_match_table = ACPI_PTR(hidma_mgmt_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int object_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int __init hidma_mgmt_of_populate_channels(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct platform_device *pdev_parent = of_find_device_by_node(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	struct platform_device_info pdevinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	/* allocate a resource array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	res = kcalloc(3, sizeof(*res), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	for_each_available_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		struct platform_device *new_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		ret = of_address_to_resource(child, 0, &res[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		ret = of_address_to_resource(child, 1, &res[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		ret = of_irq_to_resource(child, 0, &res[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		memset(&pdevinfo, 0, sizeof(pdevinfo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		pdevinfo.fwnode = &child->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		pdevinfo.parent = pdev_parent ? &pdev_parent->dev : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		pdevinfo.name = child->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		pdevinfo.id = object_counter++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		pdevinfo.res = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		pdevinfo.num_res = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		pdevinfo.data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		pdevinfo.size_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		pdevinfo.dma_mask = DMA_BIT_MASK(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		new_pdev = platform_device_register_full(&pdevinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		if (IS_ERR(new_pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			ret = PTR_ERR(new_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		new_pdev->dev.of_node = child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		of_dma_configure(&new_pdev->dev, child, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		 * It is assumed that calling of_msi_configure is safe on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		 * platforms with or without MSI support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		of_msi_configure(&new_pdev->dev, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	kfree(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	kfree(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int __init hidma_mgmt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	for_each_matching_node(child, hidma_mgmt_match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		/* device tree based firmware here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		hidma_mgmt_of_populate_channels(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	 * We do not check for return value here, as it is assumed that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	 * platform_driver_register must not fail. The reason for this is that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	 * the (potential) hidma_mgmt_of_populate_channels calls above are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	 * cleaned up if it does fail, and to do this work is quite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	 * complicated. In particular, various calls of of_address_to_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	 * of_irq_to_resource, platform_device_register_full, of_dma_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	 * and of_msi_configure which then call other functions and so on, must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	 * be cleaned up - this is not a trivial exercise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	 * Currently, this module is not intended to be unloaded, and there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	 * no module_exit function defined which does the needed cleanup. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	 * this reason, we have to assume success here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	platform_driver_register(&hidma_mgmt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) module_init(hidma_mgmt_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MODULE_LICENSE("GPL v2");