^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Qualcomm Technologies HIDMA DMA engine low level code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kfifo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "hidma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HIDMA_EVRE_SIZE 16 /* each EVRE is 16 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HIDMA_TRCA_CTRLSTS_REG 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HIDMA_TRCA_RING_LOW_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HIDMA_TRCA_RING_HIGH_REG 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HIDMA_TRCA_RING_LEN_REG 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HIDMA_TRCA_DOORBELL_REG 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HIDMA_EVCA_CTRLSTS_REG 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HIDMA_EVCA_INTCTRL_REG 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HIDMA_EVCA_RING_LOW_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HIDMA_EVCA_RING_HIGH_REG 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HIDMA_EVCA_RING_LEN_REG 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HIDMA_EVCA_WRITE_PTR_REG 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HIDMA_EVCA_DOORBELL_REG 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HIDMA_EVCA_IRQ_STAT_REG 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HIDMA_EVCA_IRQ_CLR_REG 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HIDMA_EVCA_IRQ_EN_REG 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HIDMA_EVRE_CFG_IDX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HIDMA_EVRE_ERRINFO_BIT_POS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HIDMA_EVRE_CODE_BIT_POS 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HIDMA_EVRE_ERRINFO_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HIDMA_EVRE_CODE_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HIDMA_CH_CONTROL_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HIDMA_CH_STATE_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HIDMA_CH_STATE_BIT_POS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HIDMA_IRQ_EV_CH_EOB_IRQ_BIT_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HIDMA_IRQ_EV_CH_WR_RESP_BIT_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HIDMA_IRQ_TR_CH_TRE_RD_RSP_ER_BIT_POS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HIDMA_IRQ_TR_CH_DATA_RD_ER_BIT_POS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HIDMA_IRQ_TR_CH_DATA_WR_ER_BIT_POS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HIDMA_IRQ_TR_CH_INVALID_TRE_BIT_POS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ENABLE_IRQS (BIT(HIDMA_IRQ_EV_CH_EOB_IRQ_BIT_POS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) BIT(HIDMA_IRQ_EV_CH_WR_RESP_BIT_POS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) BIT(HIDMA_IRQ_TR_CH_TRE_RD_RSP_ER_BIT_POS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) BIT(HIDMA_IRQ_TR_CH_DATA_RD_ER_BIT_POS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) BIT(HIDMA_IRQ_TR_CH_DATA_WR_ER_BIT_POS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) BIT(HIDMA_IRQ_TR_CH_INVALID_TRE_BIT_POS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HIDMA_INCREMENT_ITERATOR(iter, size, ring_size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) iter += size; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (iter >= ring_size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) iter -= ring_size; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HIDMA_CH_STATE(val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ((val >> HIDMA_CH_STATE_BIT_POS) & HIDMA_CH_STATE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HIDMA_ERR_INT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) (BIT(HIDMA_IRQ_TR_CH_INVALID_TRE_BIT_POS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) BIT(HIDMA_IRQ_TR_CH_TRE_RD_RSP_ER_BIT_POS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) BIT(HIDMA_IRQ_EV_CH_WR_RESP_BIT_POS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) BIT(HIDMA_IRQ_TR_CH_DATA_RD_ER_BIT_POS) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) BIT(HIDMA_IRQ_TR_CH_DATA_WR_ER_BIT_POS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum ch_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) HIDMA_CH_DISABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) HIDMA_CH_ENABLE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) HIDMA_CH_SUSPEND = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) HIDMA_CH_RESET = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum ch_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) HIDMA_CH_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) HIDMA_CH_ENABLED = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) HIDMA_CH_RUNNING = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) HIDMA_CH_SUSPENDED = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) HIDMA_CH_STOPPED = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) enum err_code {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) HIDMA_EVRE_STATUS_COMPLETE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) HIDMA_EVRE_STATUS_ERROR = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int hidma_is_chan_enabled(int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case HIDMA_CH_ENABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case HIDMA_CH_RUNNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void hidma_ll_free(struct hidma_lldev *lldev, u32 tre_ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct hidma_tre *tre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (tre_ch >= lldev->nr_tres) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(lldev->dev, "invalid TRE number in free:%d", tre_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) tre = &lldev->trepool[tre_ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (atomic_read(&tre->allocated) != true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev_err(lldev->dev, "trying to free an unused TRE:%d", tre_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) atomic_set(&tre->allocated, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int hidma_ll_request(struct hidma_lldev *lldev, u32 sig, const char *dev_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void (*callback)(void *data), void *data, u32 *tre_ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct hidma_tre *tre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 *tre_local;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (!tre_ch || !lldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* need to have at least one empty spot in the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) for (i = 0; i < lldev->nr_tres - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (atomic_add_unless(&lldev->trepool[i].allocated, 1, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (i == (lldev->nr_tres - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) tre = &lldev->trepool[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tre->dma_sig = sig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) tre->dev_name = dev_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tre->callback = callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tre->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tre->idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) tre->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) tre->queued = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tre->err_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tre->err_info = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tre->lldev = lldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) tre_local = &tre->tre_local[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) tre_local[HIDMA_TRE_CFG_IDX] = (lldev->chidx & 0xFF) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) tre_local[HIDMA_TRE_CFG_IDX] |= BIT(16); /* set IEOB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *tre_ch = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (callback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) callback(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Multiple TREs may be queued and waiting in the pending queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void hidma_ll_tre_complete(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct hidma_lldev *lldev = from_tasklet(lldev, t, task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct hidma_tre *tre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) while (kfifo_out(&lldev->handoff_fifo, &tre, 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* call the user if it has been read by the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (tre->callback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) tre->callback(tre->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int hidma_post_completed(struct hidma_lldev *lldev, u8 err_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 err_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct hidma_tre *tre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 tre_iterator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) spin_lock_irqsave(&lldev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) tre_iterator = lldev->tre_processed_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tre = lldev->pending_tre_list[tre_iterator / HIDMA_TRE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!tre) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spin_unlock_irqrestore(&lldev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_warn(lldev->dev, "tre_index [%d] and tre out of sync\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) tre_iterator / HIDMA_TRE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) lldev->pending_tre_list[tre->tre_index] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Keep track of pending TREs that SW is expecting to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * from HW. We got one now. Decrement our counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (atomic_dec_return(&lldev->pending_tre_count) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_warn(lldev->dev, "tre count mismatch on completion");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) atomic_set(&lldev->pending_tre_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) HIDMA_INCREMENT_ITERATOR(tre_iterator, HIDMA_TRE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) lldev->tre_ring_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) lldev->tre_processed_off = tre_iterator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spin_unlock_irqrestore(&lldev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) tre->err_info = err_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tre->err_code = err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tre->queued = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) kfifo_put(&lldev->handoff_fifo, tre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tasklet_schedule(&lldev->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Called to handle the interrupt for the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Return a positive number if TRE or EVRE were consumed on this run.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Return a positive number if there are pending TREs or EVREs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Return 0 if there is nothing to consume or no pending TREs/EVREs found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int hidma_handle_tre_completion(struct hidma_lldev *lldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 evre_ring_size = lldev->evre_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 err_info, err_code, evre_write_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 evre_iterator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 num_completed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) evre_write_off = readl_relaxed(lldev->evca + HIDMA_EVCA_WRITE_PTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) evre_iterator = lldev->evre_processed_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if ((evre_write_off > evre_ring_size) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) (evre_write_off % HIDMA_EVRE_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_err(lldev->dev, "HW reports invalid EVRE write offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * By the time control reaches here the number of EVREs and TREs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * may not match. Only consume the ones that hardware told us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) while ((evre_iterator != evre_write_off)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 *current_evre = lldev->evre_ring + evre_iterator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) cfg = current_evre[HIDMA_EVRE_CFG_IDX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) err_info = cfg >> HIDMA_EVRE_ERRINFO_BIT_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) err_info &= HIDMA_EVRE_ERRINFO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) err_code =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) (cfg >> HIDMA_EVRE_CODE_BIT_POS) & HIDMA_EVRE_CODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (hidma_post_completed(lldev, err_info, err_code))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) HIDMA_INCREMENT_ITERATOR(evre_iterator, HIDMA_EVRE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) evre_ring_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Read the new event descriptor written by the HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * As we are processing the delivered events, other events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * get queued to the SW for processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) evre_write_off =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) readl_relaxed(lldev->evca + HIDMA_EVCA_WRITE_PTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) num_completed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * An error interrupt might have arrived while we are processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * the completed interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!hidma_ll_isenabled(lldev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (num_completed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 evre_read_off = (lldev->evre_processed_off +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) HIDMA_EVRE_SIZE * num_completed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) evre_read_off = evre_read_off % evre_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) writel(evre_read_off, lldev->evca + HIDMA_EVCA_DOORBELL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* record the last processed tre offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) lldev->evre_processed_off = evre_read_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return num_completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void hidma_cleanup_pending_tre(struct hidma_lldev *lldev, u8 err_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 err_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) while (atomic_read(&lldev->pending_tre_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (hidma_post_completed(lldev, err_info, err_code))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int hidma_ll_reset(struct hidma_lldev *lldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) val = readl(lldev->trca + HIDMA_TRCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) val &= ~(HIDMA_CH_CONTROL_MASK << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) val |= HIDMA_CH_RESET << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) writel(val, lldev->trca + HIDMA_TRCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Delay 10ms after reset to allow DMA logic to quiesce.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Do a polled read up to 1ms and 10ms maximum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = readl_poll_timeout(lldev->trca + HIDMA_TRCA_CTRLSTS_REG, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) HIDMA_CH_STATE(val) == HIDMA_CH_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 1000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_err(lldev->dev, "transfer channel did not reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) val &= ~(HIDMA_CH_CONTROL_MASK << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) val |= HIDMA_CH_RESET << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Delay 10ms after reset to allow DMA logic to quiesce.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Do a polled read up to 1ms and 10ms maximum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) HIDMA_CH_STATE(val) == HIDMA_CH_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 1000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) lldev->trch_state = HIDMA_CH_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) lldev->evch_state = HIDMA_CH_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * The interrupt handler for HIDMA will try to consume as many pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * EVRE from the event queue as possible. Each EVRE has an associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * TRE that holds the user interface parameters. EVRE reports the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * result of the transaction. Hardware guarantees ordering between EVREs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * and TREs. We use last processed offset to figure out which TRE is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * associated with which EVRE. If two TREs are consumed by HW, the EVREs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * are in order in the event ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * This handler will do a one pass for consuming EVREs. Other EVREs may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * be delivered while we are working. It will try to consume incoming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * EVREs one more time and return.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * For unprocessed EVREs, hardware will trigger another interrupt until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * all the interrupt bits are cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * Hardware guarantees that by the time interrupt is observed, all data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * transactions in flight are delivered to their respective places and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * are visible to the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * On demand paging for IOMMU is only supported for PCIe via PRI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * (Page Request Interface) not for HIDMA. All other hardware instances
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * including HIDMA work on pinned DMA addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * HIDMA is not aware of IOMMU presence since it follows the DMA API. All
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * IOMMU latency will be built into the data movement time. By the time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * interrupt happens, IOMMU lookups + data movement has already taken place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * While the first read in a typical PCI endpoint ISR flushes all outstanding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * requests traditionally to the destination, this concept does not apply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * here for this HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void hidma_ll_int_handler_internal(struct hidma_lldev *lldev, int cause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (cause & HIDMA_ERR_INT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_err(lldev->dev, "error 0x%x, disabling...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) cause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Clear out pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) writel(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* No further submissions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) hidma_ll_disable(lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Driver completes the txn and intimates the client.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) hidma_cleanup_pending_tre(lldev, 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) HIDMA_EVRE_STATUS_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) spin_lock_irqsave(&lldev->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) spin_unlock_irqrestore(&lldev->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * Fine tuned for this HW...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * This ISR has been designed for this particular hardware. Relaxed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * read and write accessors are used for performance reasons due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * interrupt delivery guarantees. Do not copy this code blindly and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * expect that to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * Try to consume as many EVREs as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) hidma_handle_tre_completion(lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) irqreturn_t hidma_ll_inthandler(int chirq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct hidma_lldev *lldev = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 cause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) status = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) enable = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) cause = status & enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) while (cause) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) hidma_ll_int_handler_internal(lldev, cause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * Another interrupt might have arrived while we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * processing this one. Read the new cause.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) status = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) enable = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) cause = status & enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) irqreturn_t hidma_ll_inthandler_msi(int chirq, void *arg, int cause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct hidma_lldev *lldev = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) hidma_ll_int_handler_internal(lldev, cause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int hidma_ll_enable(struct hidma_lldev *lldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) val &= ~(HIDMA_CH_CONTROL_MASK << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) val |= HIDMA_CH_ENABLE << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) hidma_is_chan_enabled(HIDMA_CH_STATE(val)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 1000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_err(lldev->dev, "event channel did not get enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) val = readl(lldev->trca + HIDMA_TRCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) val &= ~(HIDMA_CH_CONTROL_MASK << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) val |= HIDMA_CH_ENABLE << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) writel(val, lldev->trca + HIDMA_TRCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = readl_poll_timeout(lldev->trca + HIDMA_TRCA_CTRLSTS_REG, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) hidma_is_chan_enabled(HIDMA_CH_STATE(val)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 1000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_err(lldev->dev, "transfer channel did not get enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) lldev->trch_state = HIDMA_CH_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) lldev->evch_state = HIDMA_CH_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* enable irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) void hidma_ll_start(struct hidma_lldev *lldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) spin_lock_irqsave(&lldev->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) writel(lldev->tre_write_offset, lldev->trca + HIDMA_TRCA_DOORBELL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) spin_unlock_irqrestore(&lldev->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) bool hidma_ll_isenabled(struct hidma_lldev *lldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) val = readl(lldev->trca + HIDMA_TRCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) lldev->trch_state = HIDMA_CH_STATE(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) lldev->evch_state = HIDMA_CH_STATE(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* both channels have to be enabled before calling this function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (hidma_is_chan_enabled(lldev->trch_state) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) hidma_is_chan_enabled(lldev->evch_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) void hidma_ll_queue_request(struct hidma_lldev *lldev, u32 tre_ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct hidma_tre *tre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) tre = &lldev->trepool[tre_ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* copy the TRE into its location in the TRE ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) spin_lock_irqsave(&lldev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) tre->tre_index = lldev->tre_write_offset / HIDMA_TRE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) lldev->pending_tre_list[tre->tre_index] = tre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) memcpy(lldev->tre_ring + lldev->tre_write_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) &tre->tre_local[0], HIDMA_TRE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) tre->err_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) tre->err_info = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) tre->queued = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) atomic_inc(&lldev->pending_tre_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) lldev->tre_write_offset = (lldev->tre_write_offset + HIDMA_TRE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) % lldev->tre_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) spin_unlock_irqrestore(&lldev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * Note that even though we stop this channel if there is a pending transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * in flight it will complete and follow the callback. This request will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * prevent further requests to be made.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int hidma_ll_disable(struct hidma_lldev *lldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* The channel needs to be in working state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (!hidma_ll_isenabled(lldev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) val = readl(lldev->trca + HIDMA_TRCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) val &= ~(HIDMA_CH_CONTROL_MASK << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) val |= HIDMA_CH_SUSPEND << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) writel(val, lldev->trca + HIDMA_TRCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * Start the wait right after the suspend is confirmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * Do a polled read up to 1ms and 10ms maximum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = readl_poll_timeout(lldev->trca + HIDMA_TRCA_CTRLSTS_REG, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) HIDMA_CH_STATE(val) == HIDMA_CH_SUSPENDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 1000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) val &= ~(HIDMA_CH_CONTROL_MASK << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) val |= HIDMA_CH_SUSPEND << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * Start the wait right after the suspend is confirmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * Delay up to 10ms after reset to allow DMA logic to quiesce.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) HIDMA_CH_STATE(val) == HIDMA_CH_SUSPENDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 1000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) lldev->trch_state = HIDMA_CH_SUSPENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) lldev->evch_state = HIDMA_CH_SUSPENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) void hidma_ll_set_transfer_params(struct hidma_lldev *lldev, u32 tre_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dma_addr_t src, dma_addr_t dest, u32 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u32 flags, u32 txntype)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct hidma_tre *tre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u32 *tre_local;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (tre_ch >= lldev->nr_tres) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_err(lldev->dev, "invalid TRE number in transfer params:%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) tre_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) tre = &lldev->trepool[tre_ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (atomic_read(&tre->allocated) != true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dev_err(lldev->dev, "trying to set params on an unused TRE:%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) tre_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) tre_local = &tre->tre_local[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) tre_local[HIDMA_TRE_CFG_IDX] &= ~GENMASK(7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) tre_local[HIDMA_TRE_CFG_IDX] |= txntype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) tre_local[HIDMA_TRE_LEN_IDX] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) tre_local[HIDMA_TRE_SRC_LOW_IDX] = lower_32_bits(src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) tre_local[HIDMA_TRE_SRC_HI_IDX] = upper_32_bits(src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) tre_local[HIDMA_TRE_DEST_LOW_IDX] = lower_32_bits(dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) tre_local[HIDMA_TRE_DEST_HI_IDX] = upper_32_bits(dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) tre->int_flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * Called during initialization and after an error condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * to restore hardware state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int hidma_ll_setup(struct hidma_lldev *lldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 nr_tres = lldev->nr_tres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) atomic_set(&lldev->pending_tre_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) lldev->tre_processed_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) lldev->evre_processed_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) lldev->tre_write_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* clear all pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) rc = hidma_ll_reset(lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * Clear all pending interrupts again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * Otherwise, we observe reset complete interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* disable interrupts again after reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) addr = lldev->tre_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) writel(lower_32_bits(addr), lldev->trca + HIDMA_TRCA_RING_LOW_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) writel(upper_32_bits(addr), lldev->trca + HIDMA_TRCA_RING_HIGH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) writel(lldev->tre_ring_size, lldev->trca + HIDMA_TRCA_RING_LEN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) addr = lldev->evre_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) writel(lower_32_bits(addr), lldev->evca + HIDMA_EVCA_RING_LOW_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) writel(upper_32_bits(addr), lldev->evca + HIDMA_EVCA_RING_HIGH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) writel(HIDMA_EVRE_SIZE * nr_tres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) lldev->evca + HIDMA_EVCA_RING_LEN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* configure interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) hidma_ll_setup_irq(lldev, lldev->msi_support);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) rc = hidma_ll_enable(lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) void hidma_ll_setup_irq(struct hidma_lldev *lldev, bool msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) lldev->msi_support = msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* disable interrupts again after reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) writel(0, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* support IRQ by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) val = readl(lldev->evca + HIDMA_EVCA_INTCTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) val &= ~0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (!lldev->msi_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) val = val | 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) writel(val, lldev->evca + HIDMA_EVCA_INTCTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* clear all pending interrupts and enable them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct hidma_lldev *hidma_ll_init(struct device *dev, u32 nr_tres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) void __iomem *trca, void __iomem *evca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u8 chidx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u32 required_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct hidma_lldev *lldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) size_t sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (!trca || !evca || !dev || !nr_tres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* need at least four TREs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (nr_tres < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* need an extra space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) nr_tres += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) lldev = devm_kzalloc(dev, sizeof(struct hidma_lldev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!lldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) lldev->evca = evca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) lldev->trca = trca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) lldev->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) sz = sizeof(struct hidma_tre);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) lldev->trepool = devm_kcalloc(lldev->dev, nr_tres, sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (!lldev->trepool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) required_bytes = sizeof(lldev->pending_tre_list[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) lldev->pending_tre_list = devm_kcalloc(dev, nr_tres, required_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!lldev->pending_tre_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) sz = (HIDMA_TRE_SIZE + 1) * nr_tres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) lldev->tre_ring = dmam_alloc_coherent(dev, sz, &lldev->tre_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (!lldev->tre_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) lldev->tre_ring_size = HIDMA_TRE_SIZE * nr_tres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) lldev->nr_tres = nr_tres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* the TRE ring has to be TRE_SIZE aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (!IS_ALIGNED(lldev->tre_dma, HIDMA_TRE_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u8 tre_ring_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) tre_ring_shift = lldev->tre_dma % HIDMA_TRE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) tre_ring_shift = HIDMA_TRE_SIZE - tre_ring_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) lldev->tre_dma += tre_ring_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) lldev->tre_ring += tre_ring_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) sz = (HIDMA_EVRE_SIZE + 1) * nr_tres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) lldev->evre_ring = dmam_alloc_coherent(dev, sz, &lldev->evre_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (!lldev->evre_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) lldev->evre_ring_size = HIDMA_EVRE_SIZE * nr_tres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* the EVRE ring has to be EVRE_SIZE aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (!IS_ALIGNED(lldev->evre_dma, HIDMA_EVRE_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u8 evre_ring_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) evre_ring_shift = lldev->evre_dma % HIDMA_EVRE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) evre_ring_shift = HIDMA_EVRE_SIZE - evre_ring_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) lldev->evre_dma += evre_ring_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) lldev->evre_ring += evre_ring_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) lldev->nr_tres = nr_tres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) lldev->chidx = chidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) sz = nr_tres * sizeof(struct hidma_tre *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) rc = kfifo_alloc(&lldev->handoff_fifo, sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) rc = hidma_ll_setup(lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) spin_lock_init(&lldev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) tasklet_setup(&lldev->task, hidma_ll_tre_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) lldev->initialized = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return lldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int hidma_ll_uninit(struct hidma_lldev *lldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u32 required_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (!lldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (!lldev->initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) lldev->initialized = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) required_bytes = sizeof(struct hidma_tre) * lldev->nr_tres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) tasklet_kill(&lldev->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) memset(lldev->trepool, 0, required_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) lldev->trepool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) atomic_set(&lldev->pending_tre_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) lldev->tre_write_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) rc = hidma_ll_reset(lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * Clear all pending interrupts again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * Otherwise, we observe reset complete interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) enum dma_status hidma_ll_status(struct hidma_lldev *lldev, u32 tre_ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) enum dma_status ret = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct hidma_tre *tre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u8 err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) spin_lock_irqsave(&lldev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) tre = &lldev->trepool[tre_ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) err_code = tre->err_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (err_code & HIDMA_EVRE_STATUS_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ret = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) else if (err_code & HIDMA_EVRE_STATUS_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ret = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ret = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) spin_unlock_irqrestore(&lldev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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