^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Qualcomm Technologies HIDMA DMA engine interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * it under the terms of the GNU General Public License version 2 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * only version 2 as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Copyright (C) Semihalf 2009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Copyright (C) Ilya Yanok, Emcraft Systems 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Copyright (C) Alexander Popov, Promcontroller 2014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * (defines, structures and comments) was taken from MPC5121 DMA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * written by Hongjun Chen <hong-jun.chen@freescale.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Approved as OSADL project by a majority of OSADL members and funded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * by OSADL membership fees in 2009; for details see www.osadl.org.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * under the terms of the GNU General Public License as published by the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Software Foundation; either version 2 of the License, or (at your option)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * This program is distributed in the hope that it will be useful, but WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * The full GNU General Public License is included in this distribution in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * file called COPYING.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Linux Foundation elects GPLv2 license only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include "../dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include "hidma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Default idle time is 2 seconds. This parameter can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * be overridden by changing the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * /sys/bus/platform/devices/QCOM8061:<xy>/power/autosuspend_delay_ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * during kernel boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HIDMA_AUTOSUSPEND_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HIDMA_ERR_INFO_SW 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HIDMA_ERR_CODE_UNEXPECTED_TERMINATE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HIDMA_NR_DEFAULT_DESC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HIDMA_MSI_INTS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static inline struct hidma_dev *to_hidma_dev(struct dma_device *dmadev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return container_of(dmadev, struct hidma_dev, ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct hidma_dev *to_hidma_dev_from_lldev(struct hidma_lldev **_lldevp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return container_of(_lldevp, struct hidma_dev, lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline struct hidma_chan *to_hidma_chan(struct dma_chan *dmach)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return container_of(dmach, struct hidma_chan, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct hidma_desc *to_hidma_desc(struct dma_async_tx_descriptor *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return container_of(t, struct hidma_desc, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void hidma_free(struct hidma_dev *dmadev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) INIT_LIST_HEAD(&dmadev->ddev.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static unsigned int nr_desc_prm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) module_param(nr_desc_prm, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MODULE_PARM_DESC(nr_desc_prm, "number of descriptors (default: 0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum hidma_cap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) HIDMA_MSI_CAP = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) HIDMA_IDENTITY_CAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* process completed descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void hidma_process_completed(struct hidma_chan *mchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct dma_device *ddev = mchan->chan.device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct hidma_dev *mdma = to_hidma_dev(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dma_cookie_t last_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct hidma_desc *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct hidma_desc *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) INIT_LIST_HEAD(&list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Get all completed descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spin_lock_irqsave(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) list_splice_tail_init(&mchan->completed, &list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) spin_unlock_irqrestore(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Execute callbacks and run dependencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) list_for_each_entry_safe(mdesc, next, &list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) enum dma_status llstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct dmaengine_desc_callback cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct dmaengine_result result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) desc = &mdesc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) last_cookie = desc->cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) llstat = hidma_ll_status(mdma->lldev, mdesc->tre_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) spin_lock_irqsave(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (llstat == DMA_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mchan->last_success = last_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) result.result = DMA_TRANS_NOERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) result.result = DMA_TRANS_ABORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dma_cookie_complete(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) spin_unlock_irqrestore(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dmaengine_desc_get_callback(desc, &cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dma_run_dependencies(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) spin_lock_irqsave(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) list_move(&mdesc->node, &mchan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) spin_unlock_irqrestore(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dmaengine_desc_callback_invoke(&cb, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Called once for each submitted descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * PM is locked once for each descriptor that is currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * in execution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void hidma_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct hidma_desc *mdesc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct hidma_chan *mchan = to_hidma_chan(mdesc->desc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct dma_device *ddev = mchan->chan.device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct hidma_dev *dmadev = to_hidma_dev(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bool queued = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) spin_lock_irqsave(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (mdesc->node.next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Delete from the active list, add to completed list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) list_move_tail(&mdesc->node, &mchan->completed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) queued = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* calculate the next running descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mchan->running = list_first_entry(&mchan->active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct hidma_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) spin_unlock_irqrestore(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) hidma_process_completed(mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (queued) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pm_runtime_mark_last_busy(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pm_runtime_put_autosuspend(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int hidma_chan_init(struct hidma_dev *dmadev, u32 dma_sig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct hidma_chan *mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct dma_device *ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mchan = devm_kzalloc(dmadev->ddev.dev, sizeof(*mchan), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!mchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ddev = &dmadev->ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mchan->dma_sig = dma_sig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mchan->dmadev = dmadev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mchan->chan.device = ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dma_cookie_init(&mchan->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) INIT_LIST_HEAD(&mchan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) INIT_LIST_HEAD(&mchan->prepared);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) INIT_LIST_HEAD(&mchan->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) INIT_LIST_HEAD(&mchan->completed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) INIT_LIST_HEAD(&mchan->queued);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) spin_lock_init(&mchan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) list_add_tail(&mchan->chan.device_node, &ddev->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dmadev->ddev.chancnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void hidma_issue_task(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct hidma_dev *dmadev = from_tasklet(dmadev, t, task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pm_runtime_get_sync(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) hidma_ll_start(dmadev->lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void hidma_issue_pending(struct dma_chan *dmach)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct hidma_chan *mchan = to_hidma_chan(dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct hidma_dev *dmadev = mchan->dmadev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct hidma_desc *qdesc, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) spin_lock_irqsave(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) list_for_each_entry_safe(qdesc, next, &mchan->queued, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) hidma_ll_queue_request(dmadev->lldev, qdesc->tre_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) list_move_tail(&qdesc->node, &mchan->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!mchan->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct hidma_desc *desc = list_first_entry(&mchan->active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct hidma_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mchan->running = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spin_unlock_irqrestore(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* PM will be released in hidma_callback function. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) status = pm_runtime_get(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) tasklet_schedule(&dmadev->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) hidma_ll_start(dmadev->lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static inline bool hidma_txn_is_success(dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dma_cookie_t last_success, dma_cookie_t last_used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (last_success <= last_used) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if ((cookie <= last_success) || (cookie > last_used))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if ((cookie <= last_success) && (cookie > last_used))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static enum dma_status hidma_tx_status(struct dma_chan *dmach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct hidma_chan *mchan = to_hidma_chan(dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) enum dma_status ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = dma_cookie_status(dmach, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret == DMA_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) bool is_success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) is_success = hidma_txn_is_success(cookie, mchan->last_success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dmach->cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return is_success ? ret : DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (mchan->paused && (ret == DMA_IN_PROGRESS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dma_cookie_t runcookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) spin_lock_irqsave(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (mchan->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) runcookie = mchan->running->desc.cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) runcookie = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (runcookie == cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = DMA_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) spin_unlock_irqrestore(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Submit descriptor to hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * Lock the PM for each descriptor we are sending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static dma_cookie_t hidma_tx_submit(struct dma_async_tx_descriptor *txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct hidma_chan *mchan = to_hidma_chan(txd->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct hidma_dev *dmadev = mchan->dmadev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct hidma_desc *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pm_runtime_get_sync(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!hidma_ll_isenabled(dmadev->lldev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pm_runtime_mark_last_busy(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pm_runtime_put_autosuspend(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pm_runtime_mark_last_busy(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pm_runtime_put_autosuspend(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mdesc = container_of(txd, struct hidma_desc, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) spin_lock_irqsave(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Move descriptor to queued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) list_move_tail(&mdesc->node, &mchan->queued);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Update cookie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) cookie = dma_cookie_assign(txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) spin_unlock_irqrestore(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int hidma_alloc_chan_resources(struct dma_chan *dmach)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct hidma_chan *mchan = to_hidma_chan(dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct hidma_dev *dmadev = mchan->dmadev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct hidma_desc *mdesc, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) LIST_HEAD(descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (mchan->allocated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Alloc descriptors for this channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) for (i = 0; i < dmadev->nr_descriptors; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) mdesc = kzalloc(sizeof(struct hidma_desc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!mdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dma_async_tx_descriptor_init(&mdesc->desc, dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mdesc->desc.tx_submit = hidma_tx_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) rc = hidma_ll_request(dmadev->lldev, mchan->dma_sig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "DMA engine", hidma_callback, mdesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) &mdesc->tre_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_err(dmach->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "channel alloc failed at %u\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) kfree(mdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) list_add_tail(&mdesc->node, &descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* return the allocated descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) list_for_each_entry_safe(mdesc, tmp, &descs, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) hidma_ll_free(dmadev->lldev, mdesc->tre_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) kfree(mdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) spin_lock_irqsave(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) list_splice_tail_init(&descs, &mchan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mchan->allocated = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) spin_unlock_irqrestore(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) hidma_prep_dma_memcpy(struct dma_chan *dmach, dma_addr_t dest, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct hidma_chan *mchan = to_hidma_chan(dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct hidma_desc *mdesc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct hidma_dev *mdma = mchan->dmadev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Get free descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) spin_lock_irqsave(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!list_empty(&mchan->free)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mdesc = list_first_entry(&mchan->free, struct hidma_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) list_del(&mdesc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) spin_unlock_irqrestore(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) mdesc->desc.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) src, dest, len, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) HIDMA_TRE_MEMCPY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Place descriptor in prepared list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) spin_lock_irqsave(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) list_add_tail(&mdesc->node, &mchan->prepared);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) spin_unlock_irqrestore(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return &mdesc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) hidma_prep_dma_memset(struct dma_chan *dmach, dma_addr_t dest, int value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct hidma_chan *mchan = to_hidma_chan(dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct hidma_desc *mdesc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct hidma_dev *mdma = mchan->dmadev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Get free descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) spin_lock_irqsave(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!list_empty(&mchan->free)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mdesc = list_first_entry(&mchan->free, struct hidma_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) list_del(&mdesc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) spin_unlock_irqrestore(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) mdesc->desc.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) value, dest, len, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) HIDMA_TRE_MEMSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Place descriptor in prepared list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) spin_lock_irqsave(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) list_add_tail(&mdesc->node, &mchan->prepared);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) spin_unlock_irqrestore(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return &mdesc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int hidma_terminate_channel(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct hidma_chan *mchan = to_hidma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct hidma_dev *dmadev = to_hidma_dev(mchan->chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct hidma_desc *tmp, *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) LIST_HEAD(list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pm_runtime_get_sync(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* give completed requests a chance to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) hidma_process_completed(mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) spin_lock_irqsave(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) mchan->last_success = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) list_splice_init(&mchan->active, &list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) list_splice_init(&mchan->prepared, &list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) list_splice_init(&mchan->completed, &list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) list_splice_init(&mchan->queued, &list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) spin_unlock_irqrestore(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* this suspends the existing transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) rc = hidma_ll_disable(dmadev->lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(dmadev->ddev.dev, "channel did not pause\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* return all user requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) list_for_each_entry_safe(mdesc, tmp, &list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct dma_async_tx_descriptor *txd = &mdesc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dma_descriptor_unmap(txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dmaengine_desc_get_callback_invoke(txd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dma_run_dependencies(txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* move myself to free_list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) list_move(&mdesc->node, &mchan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) rc = hidma_ll_enable(dmadev->lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pm_runtime_mark_last_busy(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pm_runtime_put_autosuspend(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int hidma_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct hidma_chan *mchan = to_hidma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct hidma_dev *dmadev = to_hidma_dev(mchan->chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) rc = hidma_terminate_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* reinitialize the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pm_runtime_get_sync(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) rc = hidma_ll_setup(dmadev->lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pm_runtime_mark_last_busy(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) pm_runtime_put_autosuspend(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static void hidma_free_chan_resources(struct dma_chan *dmach)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct hidma_chan *mchan = to_hidma_chan(dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct hidma_dev *mdma = mchan->dmadev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct hidma_desc *mdesc, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) LIST_HEAD(descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* terminate running transactions and free descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) hidma_terminate_channel(dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) spin_lock_irqsave(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Move data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) list_splice_tail_init(&mchan->free, &descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Free descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) list_for_each_entry_safe(mdesc, tmp, &descs, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) hidma_ll_free(mdma->lldev, mdesc->tre_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) list_del(&mdesc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) kfree(mdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mchan->allocated = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) spin_unlock_irqrestore(&mchan->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int hidma_pause(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct hidma_chan *mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct hidma_dev *dmadev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mchan = to_hidma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dmadev = to_hidma_dev(mchan->chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!mchan->paused) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pm_runtime_get_sync(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (hidma_ll_disable(dmadev->lldev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_warn(dmadev->ddev.dev, "channel did not stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mchan->paused = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) pm_runtime_mark_last_busy(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pm_runtime_put_autosuspend(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int hidma_resume(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct hidma_chan *mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct hidma_dev *dmadev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mchan = to_hidma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dmadev = to_hidma_dev(mchan->chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (mchan->paused) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pm_runtime_get_sync(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) rc = hidma_ll_enable(dmadev->lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) mchan->paused = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_err(dmadev->ddev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) "failed to resume the channel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pm_runtime_mark_last_busy(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pm_runtime_put_autosuspend(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static irqreturn_t hidma_chirq_handler(int chirq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct hidma_lldev *lldev = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * All interrupts are request driven.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * HW doesn't send an interrupt by itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return hidma_ll_inthandler(chirq, lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static irqreturn_t hidma_chirq_handler_msi(int chirq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct hidma_lldev **lldevp = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct hidma_dev *dmadev = to_hidma_dev_from_lldev(lldevp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return hidma_ll_inthandler_msi(chirq, *lldevp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 1 << (chirq - dmadev->msi_virqbase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static ssize_t hidma_show_values(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct hidma_dev *mdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) buf[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (strcmp(attr->attr.name, "chid") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) sprintf(buf, "%d\n", mdev->chidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return strlen(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static inline void hidma_sysfs_uninit(struct hidma_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) device_remove_file(dev->ddev.dev, dev->chid_attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static struct device_attribute*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) hidma_create_sysfs_entry(struct hidma_dev *dev, char *name, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct device_attribute *attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) char *name_copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) attrs = devm_kmalloc(dev->ddev.dev, sizeof(struct device_attribute),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (!attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) name_copy = devm_kstrdup(dev->ddev.dev, name, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!name_copy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) attrs->attr.name = name_copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) attrs->attr.mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) attrs->show = hidma_show_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) sysfs_attr_init(&attrs->attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int hidma_sysfs_init(struct hidma_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dev->chid_attrs = hidma_create_sysfs_entry(dev, "chid", S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (!dev->chid_attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return device_create_file(dev->ddev.dev, dev->chid_attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static void hidma_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct device *dev = msi_desc_to_dev(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct hidma_dev *dmadev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (!desc->platform.msi_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) writel(msg->address_lo, dmadev->dev_evca + 0x118);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) writel(msg->address_hi, dmadev->dev_evca + 0x11C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) writel(msg->data, dmadev->dev_evca + 0x120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static void hidma_free_msis(struct hidma_dev *dmadev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct device *dev = dmadev->ddev.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct msi_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* free allocated MSI interrupts above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) for_each_msi_entry(desc, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) devm_free_irq(dev, desc->irq, &dmadev->lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) platform_msi_domain_free_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static int hidma_request_msi(struct hidma_dev *dmadev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct msi_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct msi_desc *failed_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) rc = platform_msi_domain_alloc_irqs(&pdev->dev, HIDMA_MSI_INTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) hidma_write_msi_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) for_each_msi_entry(desc, &pdev->dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (!desc->platform.msi_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dmadev->msi_virqbase = desc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) rc = devm_request_irq(&pdev->dev, desc->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) hidma_chirq_handler_msi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 0, "qcom-hidma-msi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) &dmadev->lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) failed_desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* free allocated MSI interrupts above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) for_each_msi_entry(desc, &pdev->dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (desc == failed_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) devm_free_irq(&pdev->dev, desc->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) &dmadev->lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Add callback to free MSIs on teardown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) hidma_ll_setup_irq(dmadev->lldev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) "failed to request MSI irq, falling back to wired IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static bool hidma_test_capability(struct device *dev, enum hidma_cap test_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) enum hidma_cap cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) cap = (enum hidma_cap) device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return cap ? ((cap & test_cap) > 0) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static int hidma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct hidma_dev *dmadev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct resource *trca_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct resource *evca_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int chirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) void __iomem *evca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) void __iomem *trca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) bool msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) trca_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) trca = devm_ioremap_resource(&pdev->dev, trca_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (IS_ERR(trca)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) evca_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) evca = devm_ioremap_resource(&pdev->dev, evca_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (IS_ERR(evca)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * This driver only handles the channel IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * Common IRQ is handled by the management driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) chirq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (chirq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (!dmadev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) goto bailout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) INIT_LIST_HEAD(&dmadev->ddev.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) spin_lock_init(&dmadev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dmadev->ddev.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pm_runtime_get_sync(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dma_cap_set(DMA_MEMCPY, dmadev->ddev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dma_cap_set(DMA_MEMSET, dmadev->ddev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (WARN_ON(!pdev->dev.dma_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) rc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) goto dmafree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dmadev->dev_evca = evca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dmadev->evca_resource = evca_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dmadev->dev_trca = trca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dmadev->trca_resource = trca_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dmadev->ddev.device_prep_dma_memcpy = hidma_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dmadev->ddev.device_prep_dma_memset = hidma_prep_dma_memset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dmadev->ddev.device_alloc_chan_resources = hidma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dmadev->ddev.device_free_chan_resources = hidma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dmadev->ddev.device_tx_status = hidma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dmadev->ddev.device_issue_pending = hidma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dmadev->ddev.device_pause = hidma_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dmadev->ddev.device_resume = hidma_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dmadev->ddev.device_terminate_all = hidma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dmadev->ddev.copy_align = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * Determine the MSI capability of the platform. Old HW doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * support MSI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) msi = hidma_test_capability(&pdev->dev, HIDMA_MSI_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) device_property_read_u32(&pdev->dev, "desc-count",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) &dmadev->nr_descriptors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (nr_desc_prm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_info(&pdev->dev, "overriding number of descriptors as %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) nr_desc_prm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dmadev->nr_descriptors = nr_desc_prm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (!dmadev->nr_descriptors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dmadev->nr_descriptors = HIDMA_NR_DEFAULT_DESC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (hidma_test_capability(&pdev->dev, HIDMA_IDENTITY_CAP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dmadev->chidx = readl(dmadev->dev_trca + 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dmadev->chidx = readl(dmadev->dev_trca + 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* Set DMA mask to 64 bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_warn(&pdev->dev, "unable to set coherent mask to 64");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) goto dmafree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dmadev->lldev = hidma_ll_init(dmadev->ddev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dmadev->nr_descriptors, dmadev->dev_trca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dmadev->dev_evca, dmadev->chidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (!dmadev->lldev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) rc = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) goto dmafree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) platform_set_drvdata(pdev, dmadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) rc = hidma_request_msi(dmadev, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (!msi || rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) hidma_ll_setup_irq(dmadev->lldev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) rc = devm_request_irq(&pdev->dev, chirq, hidma_chirq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) 0, "qcom-hidma", dmadev->lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) goto uninit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) INIT_LIST_HEAD(&dmadev->ddev.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) rc = hidma_chan_init(dmadev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) goto uninit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) rc = dma_async_device_register(&dmadev->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) goto uninit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dmadev->irq = chirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) tasklet_setup(&dmadev->task, hidma_issue_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) hidma_debug_init(dmadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) hidma_sysfs_init(dmadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dev_info(&pdev->dev, "HI-DMA engine driver registration complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) pm_runtime_mark_last_busy(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) pm_runtime_put_autosuspend(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) uninit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) hidma_free_msis(dmadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) hidma_ll_uninit(dmadev->lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dmafree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (dmadev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) hidma_free(dmadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) bailout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static void hidma_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct hidma_dev *dmadev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev_info(dmadev->ddev.dev, "HI-DMA engine shutdown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) pm_runtime_get_sync(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (hidma_ll_disable(dmadev->lldev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dev_warn(dmadev->ddev.dev, "channel did not stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) pm_runtime_mark_last_busy(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) pm_runtime_put_autosuspend(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int hidma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct hidma_dev *dmadev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) pm_runtime_get_sync(dmadev->ddev.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dma_async_device_unregister(&dmadev->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (!dmadev->lldev->msi_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) devm_free_irq(dmadev->ddev.dev, dmadev->irq, dmadev->lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) hidma_free_msis(dmadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) tasklet_kill(&dmadev->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) hidma_sysfs_uninit(dmadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) hidma_debug_uninit(dmadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) hidma_ll_uninit(dmadev->lldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) hidma_free(dmadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) dev_info(&pdev->dev, "HI-DMA engine removed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) pm_runtime_put_sync_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #if IS_ENABLED(CONFIG_ACPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static const struct acpi_device_id hidma_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {"QCOM8061"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {"QCOM8062", HIDMA_MSI_CAP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {"QCOM8063", (HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static const struct of_device_id hidma_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {.compatible = "qcom,hidma-1.0",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {.compatible = "qcom,hidma-1.1", .data = (void *)(HIDMA_MSI_CAP),},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {.compatible = "qcom,hidma-1.2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .data = (void *)(HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP),},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) MODULE_DEVICE_TABLE(of, hidma_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static struct platform_driver hidma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .probe = hidma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .remove = hidma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .shutdown = hidma_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .name = "hidma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .of_match_table = hidma_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .acpi_match_table = ACPI_PTR(hidma_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) module_platform_driver(hidma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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