^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * 440SPe's XOR engines support header file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * 2006-2009 (C) DENX Software Engineering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Yuri Tikhonov <yur@emcraft.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the term of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * version 2. The program licensed "as is" without any warranty of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef _PPC440SPE_XOR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define _PPC440SPE_XOR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Number of XOR engines available on the contoller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define XOR_ENGINES_NUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Number of operands supported in the h/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define XOR_MAX_OPS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * XOR Command Block Control Register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define XOR_CBCR_LNK_BIT (1<<31) /* link present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define XOR_CBCR_TGT_BIT (1<<30) /* target present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XOR_CBCR_CBCE_BIT (1<<29) /* command block compete enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XOR_CBCR_RNZE_BIT (1<<28) /* result not zero enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define XOR_CBCR_XNOR_BIT (1<<15) /* XOR/XNOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XOR_CDCR_OAC_MSK (0x7F) /* operand address count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * XORCore Status Register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XOR_SR_XCP_BIT (1<<31) /* core processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define XOR_SR_ICB_BIT (1<<17) /* invalid CB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define XOR_SR_IC_BIT (1<<16) /* invalid command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XOR_SR_IPE_BIT (1<<15) /* internal parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XOR_SR_RNZ_BIT (1<<2) /* result not Zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define XOR_SR_CBC_BIT (1<<1) /* CB complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define XOR_SR_CBLC_BIT (1<<0) /* CB list complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * XORCore Control Set and Reset Register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define XOR_CRSR_XASR_BIT (1<<31) /* soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define XOR_CRSR_XAE_BIT (1<<30) /* enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XOR_CRSR_RCBE_BIT (1<<29) /* refetch CB enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define XOR_CRSR_PAUS_BIT (1<<28) /* pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define XOR_CRSR_64BA_BIT (1<<27) /* 64/32 CB format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define XOR_CRSR_CLP_BIT (1<<25) /* continue list processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * XORCore Interrupt Enable Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define XOR_IE_ICBIE_BIT (1<<17) /* Invalid Command Block IRQ Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define XOR_IE_ICIE_BIT (1<<16) /* Invalid Command IRQ Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define XOR_IE_RPTIE_BIT (1<<14) /* Read PLB Timeout Error IRQ Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define XOR_IE_CBCIE_BIT (1<<1) /* CB complete interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define XOR_IE_CBLCI_BIT (1<<0) /* CB list complete interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * XOR Accelerator engine Command Block Type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct xor_cb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Basic 64-bit format XOR CB (Table 19-1, p.463, 440spe_um_1_22.pdf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 cbc; /* control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 cbbc; /* byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 cbs; /* status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 pad0[4]; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 cbtah; /* target address high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 cbtal; /* target address low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 cblah; /* link address high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 cblal; /* link address low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) } __attribute__ ((packed)) ops[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * XOR hardware registers Table 19-3, UM 1.22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct xor_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 op_ar[16][2]; /* operand address[0]-high,[1]-low registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 pad0[352]; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 cbcr; /* CB control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 cbbcr; /* CB byte count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 cbsr; /* CB status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 pad1[4]; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 cbtahr; /* operand target address high register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 cbtalr; /* operand target address low register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 cblahr; /* CB link address high register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 cblalr; /* CB link address low register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 crsr; /* control set register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 crrr; /* control reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 ccbahr; /* current CB address high register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 ccbalr; /* current CB address low register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 plbr; /* PLB configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 ier; /* interrupt enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 pecr; /* parity error count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 sr; /* status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 revidr; /* revision ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif /* _PPC440SPE_XOR_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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