^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 Samsung Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Jaswinder Singh <jassi.brar@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PL330_MAX_CHAN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PL330_MAX_IRQS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PL330_MAX_PERI 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PL330_MAX_BURST 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PL330_QUIRK_PERIPH_BURST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) enum pl330_cachectrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CCTRL0, /* Noncacheable and nonbufferable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) CCTRL1, /* Bufferable only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) CCTRL2, /* Cacheable, but do not allocate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) CCTRL3, /* Cacheable and bufferable, but do not allocate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) INVALID1, /* AWCACHE = 0x1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) INVALID2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) CCTRL6, /* Cacheable write-through, allocate on writes only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CCTRL7, /* Cacheable write-back, allocate on writes only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) enum pl330_byteswap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SWAP_NO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SWAP_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SWAP_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SWAP_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SWAP_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Register and Bit field Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DS_ST_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DS_ST_EXEC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DS_ST_CMISS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DS_ST_UPDTPC 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DS_ST_WFE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DS_ST_ATBRR 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DS_ST_QBUSY 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DS_ST_WFP 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DS_ST_KILL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DS_ST_CMPLT 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DS_ST_FLTCMP 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DS_ST_FAULT 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DPC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define INTEN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ES 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define INTSTATUS 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define INTCLR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FSM 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FSC 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FTM 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define _FTC 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FTC(n) (_FTC + (n)*0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define _CS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CS(n) (_CS + (n)*0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CS_CNS (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define _CPC 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CPC(n) (_CPC + (n)*0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define _SA 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SA(n) (_SA + (n)*0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define _DA 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DA(n) (_DA + (n)*0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define _CC 0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CC(n) (_CC + (n)*0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CC_SRCINC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CC_DSTINC (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CC_SRCPRI (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CC_DSTPRI (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CC_SRCNS (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CC_DSTNS (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CC_SRCIA (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CC_DSTIA (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CC_SRCBRSTLEN_SHFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CC_DSTBRSTLEN_SHFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CC_SRCBRSTSIZE_SHFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CC_DSTBRSTSIZE_SHFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CC_SRCCCTRL_SHFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CC_SRCCCTRL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CC_DSTCCTRL_SHFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CC_DRCCCTRL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CC_SWAP_SHFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define _LC0 0x40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LC0(n) (_LC0 + (n)*0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define _LC1 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LC1(n) (_LC1 + (n)*0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DBGSTATUS 0xd00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DBG_BUSY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DBGCMD 0xd04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DBGINST0 0xd08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DBGINST1 0xd0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CR0 0xe00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CR1 0xe04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CR2 0xe08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CR3 0xe0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CR4 0xe10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CRD 0xe14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PERIPH_ID 0xfe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PERIPH_REV_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PERIPH_REV_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PERIPH_REV_R0P0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PERIPH_REV_R1P0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PERIPH_REV_R1P1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CR0_PERIPH_REQ_SET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CR0_BOOT_EN_SET (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CR0_BOOT_MAN_NS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CR0_NUM_CHANS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CR0_NUM_CHANS_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CR0_NUM_PERIPH_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CR0_NUM_PERIPH_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CR0_NUM_EVENTS_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CR0_NUM_EVENTS_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CR1_ICACHE_LEN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CR1_ICACHE_LEN_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CR1_NUM_ICACHELINES_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CR1_NUM_ICACHELINES_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CRD_DATA_WIDTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CRD_DATA_WIDTH_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CRD_WR_CAP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CRD_WR_CAP_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CRD_WR_Q_DEP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CRD_WR_Q_DEP_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CRD_RD_CAP_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CRD_RD_CAP_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CRD_RD_Q_DEP_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CRD_RD_Q_DEP_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CRD_DATA_BUFF_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CRD_DATA_BUFF_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PART 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DESIGNER 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define REVISION 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define INTEG_CFG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PL330_STATE_STOPPED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PL330_STATE_EXECUTING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PL330_STATE_WFE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PL330_STATE_FAULTING (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PL330_STATE_COMPLETING (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PL330_STATE_WFP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PL330_STATE_KILLING (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PL330_STATE_FAULT_COMPLETING (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PL330_STATE_CACHEMISS (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PL330_STATE_UPDTPC (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PL330_STATE_ATBARRIER (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PL330_STATE_QUEUEBUSY (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PL330_STATE_INVALID (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) | PL330_STATE_WFE | PL330_STATE_FAULTING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CMD_DMAADDH 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CMD_DMAEND 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CMD_DMAFLUSHP 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CMD_DMAGO 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CMD_DMALD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CMD_DMALDP 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CMD_DMALP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CMD_DMALPEND 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CMD_DMAKILL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CMD_DMAMOV 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CMD_DMANOP 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CMD_DMARMB 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CMD_DMASEV 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CMD_DMAST 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CMD_DMASTP 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CMD_DMASTZ 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CMD_DMAWFE 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CMD_DMAWFP 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CMD_DMAWMB 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SZ_DMAADDH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SZ_DMAEND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SZ_DMAFLUSHP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SZ_DMALD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SZ_DMALDP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SZ_DMALP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SZ_DMALPEND 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SZ_DMAKILL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SZ_DMAMOV 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SZ_DMANOP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SZ_DMARMB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SZ_DMASEV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SZ_DMAST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SZ_DMASTP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SZ_DMASTZ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SZ_DMAWFE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SZ_DMAWFP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SZ_DMAWMB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SZ_DMAGO 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define BYTE_MOD_BURST_LEN(b, ccr) (((b) / BRST_SIZE(ccr)) % BRST_LEN(ccr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * at 1byte/burst for P<->M and M<->M respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * should be enough for P<->M and M<->M respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MCODE_BUFF_PER_REQ 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Use this _only_ to wait on transient states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #ifdef PL330_DEBUG_MCGEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static unsigned cmd_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define PL330_DBGCMD_DUMP(off, x...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) printk("%x:", cmd_line); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) printk(KERN_CONT x); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) cmd_line += off; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define PL330_DBGMC_START(addr) (cmd_line = addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define PL330_DBGMC_START(addr) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* The number of default descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define NR_DEFAULT_DESC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Delay for runtime PM autosuspend, ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define PL330_AUTOSUSPEND_DELAY 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Populated by the PL330 core driver for DMA API driver's info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct pl330_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 periph_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DMAC_MODE_NS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned int data_bus_width:10; /* In number of bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned int data_buf_dep:11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int num_chan:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int num_peri:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 peri_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int num_events:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 irq_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * Request Configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * The PL330 core does not modify this and uses the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * working configuration if the request doesn't provide any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * The Client may want to provide this info only for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * first request and a request with new settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct pl330_reqcfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Address Incrementing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned dst_inc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned src_inc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * For now, the SRC & DST protection levels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * and burst size/length are assumed same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) bool nonsecure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) bool privileged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) bool insnaccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned brst_len:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned brst_size:3; /* in power of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) enum pl330_cachectrl dcctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) enum pl330_cachectrl scctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) enum pl330_byteswap swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct pl330_config *pcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * One cycle of DMAC operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * There may be more than one xfer in a request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct pl330_xfer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Size to xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* The xfer callbacks are made with one of these arguments. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) enum pl330_op_err {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* The all xfers in the request were success. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PL330_ERR_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* If req aborted due to global error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PL330_ERR_ABORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* If req failed due to problem with Channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PL330_ERR_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) enum dmamov_dst {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) SAR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) CCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) DAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) enum pl330_dst {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) SRC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) DST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) enum pl330_cond {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) BURST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ALWAYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct dma_pl330_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct _pl330_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 mc_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) void *mc_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct dma_pl330_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* ToBeDone for tasklet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct _pl330_tbd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) bool reset_dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) bool reset_mngr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u8 reset_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* A DMAC Thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct pl330_thread {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* If the channel is not yet acquired by any client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) bool free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Parent DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct pl330_dmac *dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Only two at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct _pl330_req req[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Index of the last enqueued request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned lstenq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Index of the last submitted request or -1 if the DMA is stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int req_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) enum pl330_dmac_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) UNINIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DYING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) enum desc_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* In the DMAC pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) FREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * Allocated to some channel during prep_xxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Also may be sitting on the work_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PREP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * Sitting on the work_list and already submitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * to the PL330 core. Not more than two descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * of a channel can be BUSY at any time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Sitting on the channel work_list but xfer done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * by PL330 core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct dma_pl330_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Schedule desc completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct tasklet_struct task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* DMA-Engine Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct dma_chan chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* List of submitted descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct list_head submitted_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* List of issued descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct list_head work_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* List of completed descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct list_head completed_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Pointer to the DMAC that manages this channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * NULL if the channel is available to be acquired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * As the parent, this DMAC also provides descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * to the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct pl330_dmac *dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* To protect channel manipulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * Hardware channel thread of PL330 DMAC. NULL if the channel is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct pl330_thread *thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* For D-to-M and M-to-D channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int burst_sz; /* the peripheral fifo width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int burst_len; /* the number of burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) phys_addr_t fifo_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dma_addr_t fifo_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) enum dma_data_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct dma_slave_config slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* for runtime pm tracking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) bool active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct pl330_dmac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* DMA-Engine Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct dma_device ddma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Pool of descriptors available for the DMAC's channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct list_head desc_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* To protect desc_pool manipulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) spinlock_t pool_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Size of MicroCode buffers for each channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned mcbufsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* ioremap'ed address of PL330 registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Populated by the PL330 core driver during pl330_add */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct pl330_config pcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Maximum possible events/irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int events[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* BUS address of MicroCode buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dma_addr_t mcode_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* CPU address of MicroCode buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) void *mcode_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* List of all Channel threads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct pl330_thread *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Pointer to the MANAGER thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct pl330_thread *manager;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* To handle bad news in interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct tasklet_struct tasks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct _pl330_tbd dmac_tbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* State of DMAC operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) enum pl330_dmac_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Holds list of reqs with due callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct list_head req_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Peripheral channels connected to this DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned int num_peripherals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct dma_pl330_chan *peripherals; /* keep at end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct reset_control *rstc_ocp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static struct pl330_of_quirks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) char *quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) } of_quirks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .quirk = "arm,pl330-broken-no-flushp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .quirk = "arm,pl330-periph-burst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .id = PL330_QUIRK_PERIPH_BURST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct dma_pl330_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* To attach to a queue as child */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Descriptor for the DMA Engine API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct dma_async_tx_descriptor txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Xfer for PL330 core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct pl330_xfer px;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct pl330_reqcfg rqcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) enum desc_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int bytes_requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) bool last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* The channel which currently holds this desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct dma_pl330_chan *pchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) enum dma_transfer_direction rqtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Index of peripheral for the xfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned peri:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Hook to attach to DMAC's list of reqs with due callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct list_head rqd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* For cyclic capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) bool cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) size_t num_periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #ifdef CONFIG_NO_GKI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* interlace size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) unsigned int src_interlace_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned int dst_interlace_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct _xfer_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct dma_pl330_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int pl330_config_write(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct dma_slave_config *slave_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) enum dma_transfer_direction direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static inline bool _queue_full(struct pl330_thread *thrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static inline bool is_manager(struct pl330_thread *thrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return thrd->dmac->manager == thrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* If manager of the thread is in Non-Secure mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static inline bool _manager_ns(struct pl330_thread *thrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static inline u32 get_revision(u32 periph_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) enum pl330_dst da, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return SZ_DMAADDH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) buf[0] = CMD_DMAADDH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) buf[0] |= (da << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *((__le16 *)&buf[1]) = cpu_to_le16(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) da == 1 ? "DA" : "SA", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return SZ_DMAADDH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static inline u32 _emit_END(unsigned dry_run, u8 buf[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return SZ_DMAEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) buf[0] = CMD_DMAEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return SZ_DMAEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return SZ_DMAFLUSHP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) buf[0] = CMD_DMAFLUSHP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) peri &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) peri <<= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) buf[1] = peri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return SZ_DMAFLUSHP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return SZ_DMALD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) buf[0] = CMD_DMALD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (cond == SINGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) buf[0] |= (0 << 1) | (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) else if (cond == BURST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) buf[0] |= (1 << 1) | (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return SZ_DMALD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) enum pl330_cond cond, u8 peri)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return SZ_DMALDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) buf[0] = CMD_DMALDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (cond == BURST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) buf[0] |= (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) peri &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) peri <<= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) buf[1] = peri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) cond == SINGLE ? 'S' : 'B', peri >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return SZ_DMALDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned loop, u8 cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return SZ_DMALP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) buf[0] = CMD_DMALP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (loop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) buf[0] |= (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) cnt--; /* DMAC increments by 1 internally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) buf[1] = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return SZ_DMALP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct _arg_LPEND {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) enum pl330_cond cond;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) bool forever;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) unsigned loop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u8 bjump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) const struct _arg_LPEND *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) enum pl330_cond cond = arg->cond;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) bool forever = arg->forever;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned loop = arg->loop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u8 bjump = arg->bjump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return SZ_DMALPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) buf[0] = CMD_DMALPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (loop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) buf[0] |= (1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (!forever)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) buf[0] |= (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (cond == SINGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) buf[0] |= (0 << 1) | (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) else if (cond == BURST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) buf[0] |= (1 << 1) | (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) buf[1] = bjump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) forever ? "FE" : "END",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) loop ? '1' : '0',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) bjump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return SZ_DMALPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return SZ_DMAKILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) buf[0] = CMD_DMAKILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return SZ_DMAKILL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) enum dmamov_dst dst, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return SZ_DMAMOV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) buf[0] = CMD_DMAMOV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) buf[1] = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) buf[2] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) buf[3] = val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) buf[4] = val >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) buf[5] = val >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return SZ_DMAMOV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return SZ_DMARMB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) buf[0] = CMD_DMARMB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return SZ_DMARMB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return SZ_DMASEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) buf[0] = CMD_DMASEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ev &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ev <<= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) buf[1] = ev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return SZ_DMASEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return SZ_DMAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) buf[0] = CMD_DMAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (cond == SINGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) buf[0] |= (0 << 1) | (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) else if (cond == BURST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) buf[0] |= (1 << 1) | (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return SZ_DMAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) enum pl330_cond cond, u8 peri)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return SZ_DMASTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) buf[0] = CMD_DMASTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (cond == BURST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) buf[0] |= (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) peri &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) peri <<= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) buf[1] = peri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) cond == SINGLE ? 'S' : 'B', peri >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return SZ_DMASTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) enum pl330_cond cond, u8 peri)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return SZ_DMAWFP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) buf[0] = CMD_DMAWFP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (cond == SINGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) buf[0] |= (0 << 1) | (0 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) else if (cond == BURST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) buf[0] |= (1 << 1) | (0 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) buf[0] |= (0 << 1) | (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) peri &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) peri <<= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) buf[1] = peri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return SZ_DMAWFP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return SZ_DMAWMB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) buf[0] = CMD_DMAWMB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return SZ_DMAWMB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct _arg_GO {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u8 chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) unsigned ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) const struct _arg_GO *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u8 chan = arg->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u32 addr = arg->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) unsigned ns = arg->ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (dry_run)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return SZ_DMAGO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) buf[0] = CMD_DMAGO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) buf[0] |= (ns << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) buf[1] = chan & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) buf[2] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) buf[3] = addr >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) buf[4] = addr >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) buf[5] = addr >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return SZ_DMAGO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* Returns Time-Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static bool _until_dmac_idle(struct pl330_thread *thrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) void __iomem *regs = thrd->dmac->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) unsigned long loops = msecs_to_loops(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* Until Manager is Idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) } while (--loops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (!loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static inline void _execute_DBGINSN(struct pl330_thread *thrd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) u8 insn[], bool as_manager)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) void __iomem *regs = thrd->dmac->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* If timed out due to halted state-machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (_until_dmac_idle(thrd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) val = (insn[0] << 16) | (insn[1] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (!as_manager) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) val |= (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) val |= (thrd->id << 8); /* Channel Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) writel(val, regs + DBGINST0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) val = le32_to_cpu(*((__le32 *)&insn[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) writel(val, regs + DBGINST1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Get going */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) writel(0, regs + DBGCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static inline u32 _state(struct pl330_thread *thrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) void __iomem *regs = thrd->dmac->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (is_manager(thrd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) val = readl(regs + DS) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) val = readl(regs + CS(thrd->id)) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) case DS_ST_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return PL330_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) case DS_ST_EXEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return PL330_STATE_EXECUTING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) case DS_ST_CMISS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return PL330_STATE_CACHEMISS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) case DS_ST_UPDTPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return PL330_STATE_UPDTPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) case DS_ST_WFE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return PL330_STATE_WFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) case DS_ST_FAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return PL330_STATE_FAULTING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) case DS_ST_ATBRR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (is_manager(thrd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return PL330_STATE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return PL330_STATE_ATBARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) case DS_ST_QBUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (is_manager(thrd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return PL330_STATE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return PL330_STATE_QUEUEBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) case DS_ST_WFP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (is_manager(thrd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return PL330_STATE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return PL330_STATE_WFP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) case DS_ST_KILL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (is_manager(thrd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return PL330_STATE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return PL330_STATE_KILLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) case DS_ST_CMPLT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (is_manager(thrd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return PL330_STATE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return PL330_STATE_COMPLETING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) case DS_ST_FLTCMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (is_manager(thrd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return PL330_STATE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return PL330_STATE_FAULT_COMPLETING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return PL330_STATE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static void _stop(struct pl330_thread *thrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) void __iomem *regs = thrd->dmac->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) u8 insn[6] = {0, 0, 0, 0, 0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) u32 inten = readl(regs + INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* Return if nothing needs to be done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (_state(thrd) == PL330_STATE_COMPLETING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) || _state(thrd) == PL330_STATE_KILLING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) || _state(thrd) == PL330_STATE_STOPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) _emit_KILL(0, insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) _execute_DBGINSN(thrd, insn, is_manager(thrd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* clear the event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (inten & (1 << thrd->ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) writel(1 << thrd->ev, regs + INTCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* Stop generating interrupts for SEV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) writel(inten & ~(1 << thrd->ev), regs + INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* Start doing req 'idx' of thread 'thrd' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static bool _trigger(struct pl330_thread *thrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) void __iomem *regs = thrd->dmac->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct _pl330_req *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct dma_pl330_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct _arg_GO go;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) unsigned ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) u8 insn[6] = {0, 0, 0, 0, 0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* Return if already ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (_state(thrd) != PL330_STATE_STOPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) idx = 1 - thrd->lstenq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (thrd->req[idx].desc != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) req = &thrd->req[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) idx = thrd->lstenq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (thrd->req[idx].desc != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) req = &thrd->req[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* Return if no request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* Return if req is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (idx == thrd->req_running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) desc = req->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ns = desc->rqcfg.nonsecure ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* See 'Abort Sources' point-4 at Page 2-25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (_manager_ns(thrd) && !ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) go.chan = thrd->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) go.addr = req->mc_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) go.ns = ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) _emit_GO(0, insn, &go);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* Set to generate interrupts for SEV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* Only manager can execute GO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) _execute_DBGINSN(thrd, insn, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) thrd->req_running = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static bool _start(struct pl330_thread *thrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) switch (_state(thrd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) case PL330_STATE_FAULT_COMPLETING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (_state(thrd) == PL330_STATE_KILLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) UNTIL(thrd, PL330_STATE_STOPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case PL330_STATE_FAULTING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) _stop(thrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) case PL330_STATE_KILLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) case PL330_STATE_COMPLETING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) UNTIL(thrd, PL330_STATE_STOPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) case PL330_STATE_STOPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return _trigger(thrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) case PL330_STATE_WFP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) case PL330_STATE_QUEUEBUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) case PL330_STATE_ATBARRIER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) case PL330_STATE_UPDTPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) case PL330_STATE_CACHEMISS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) case PL330_STATE_EXECUTING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) case PL330_STATE_WFE: /* For RESUME, nothing yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) const struct _xfer_spec *pxs, int cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* check lock-up free version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) while (cyc--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) off += _emit_LD(dry_run, &buf[off], ALWAYS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) off += _emit_ST(dry_run, &buf[off], ALWAYS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) while (cyc--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) off += _emit_LD(dry_run, &buf[off], ALWAYS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) off += _emit_RMB(dry_run, &buf[off]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) off += _emit_ST(dry_run, &buf[off], ALWAYS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) off += _emit_WMB(dry_run, &buf[off]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static u32 _emit_load(unsigned int dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) enum pl330_cond cond, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) u8 peri)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) case DMA_MEM_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) off += _emit_LD(dry_run, &buf[off], cond);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (cond == ALWAYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) off += _emit_LDP(dry_run, &buf[off], SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) peri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) off += _emit_LDP(dry_run, &buf[off], BURST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) peri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) off += _emit_LDP(dry_run, &buf[off], cond,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) peri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* this code should be unreachable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static inline u32 _emit_store(unsigned int dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) enum pl330_cond cond, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) u8 peri)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) case DMA_MEM_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) off += _emit_ST(dry_run, &buf[off], cond);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (cond == ALWAYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) off += _emit_STP(dry_run, &buf[off], SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) peri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) off += _emit_STP(dry_run, &buf[off], BURST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) peri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) off += _emit_STP(dry_run, &buf[off], cond,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) peri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /* this code should be unreachable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static inline int _ldst_peripheral(struct pl330_dmac *pl330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) const struct _xfer_spec *pxs, int cyc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) enum pl330_cond cond)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * do FLUSHP at beginning to clear any stale dma requests before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * first WFP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) while (cyc--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) pxs->desc->peri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) pxs->desc->peri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #ifdef CONFIG_NO_GKI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) switch (pxs->desc->rqtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (pxs->desc->dst_interlace_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) off += _emit_ADDH(dry_run, &buf[off], DST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) pxs->desc->dst_interlace_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (pxs->desc->src_interlace_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) off += _emit_ADDH(dry_run, &buf[off], SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) pxs->desc->src_interlace_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) const struct _xfer_spec *pxs, int cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (pl330->quirks & PL330_QUIRK_PERIPH_BURST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) cond = BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) switch (pxs->desc->rqtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) cond);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) case DMA_MEM_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* this code should be unreachable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * only the unaligned bursts transfers have the dregs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * transfer dregs with a reduced size burst to peripheral,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * or a reduced size burst for mem-to-mem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) const struct _xfer_spec *pxs, int transfer_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) int dregs_ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (transfer_length == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) switch (pxs->desc->rqtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * dregs_len = (total bytes - BURST_TO_BYTE(bursts, ccr)) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * BRST_SIZE(ccr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * the dregs len must be smaller than burst len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) * so, for higher efficiency, we can modify CCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * to use a reduced size burst len for the dregs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) dregs_ccr = pxs->ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) (0xf << CC_DSTBRSTLEN_SHFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) dregs_ccr |= (((transfer_length - 1) & 0xf) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) CC_SRCBRSTLEN_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dregs_ccr |= (((transfer_length - 1) & 0xf) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) CC_DSTBRSTLEN_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) BURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) case DMA_MEM_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) dregs_ccr = pxs->ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) (0xf << CC_DSTBRSTLEN_SHFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) dregs_ccr |= (((transfer_length - 1) & 0xf) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) CC_SRCBRSTLEN_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) dregs_ccr |= (((transfer_length - 1) & 0xf) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) CC_DSTBRSTLEN_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) off += _ldst_memtomem(dry_run, &buf[off], pxs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* this code should be unreachable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /* Returns bytes consumed and updates bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) unsigned long *bursts, const struct _xfer_spec *pxs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) int cyc, cycmax, szlp, szlpend, szbrst, off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) unsigned lcnt0, lcnt1, ljmp0, ljmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct _arg_LPEND lpend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (*bursts == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return _bursts(pl330, dry_run, buf, pxs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* Max iterations possible in DMALP is 256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (*bursts >= 256*256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) lcnt1 = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) lcnt0 = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) cyc = *bursts / lcnt1 / lcnt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) } else if (*bursts > 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) lcnt1 = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) lcnt0 = *bursts / lcnt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) cyc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) lcnt1 = *bursts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) lcnt0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) cyc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) szlp = _emit_LP(1, buf, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) szbrst = _bursts(pl330, 1, buf, pxs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) lpend.cond = ALWAYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) lpend.forever = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) lpend.loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) lpend.bjump = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) szlpend = _emit_LPEND(1, buf, &lpend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (lcnt0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) szlp *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) szlpend *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * Max bursts that we can unroll due to limit on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * size of backward jump that can be encoded in DMALPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * which is 8-bits and hence 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) cycmax = (255 - (szlp + szlpend)) / szbrst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) cyc = (cycmax < cyc) ? cycmax : cyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (lcnt0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ljmp0 = off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) ljmp1 = off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) lpend.cond = ALWAYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) lpend.forever = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) lpend.loop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) lpend.bjump = off - ljmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) off += _emit_LPEND(dry_run, &buf[off], &lpend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (lcnt0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) lpend.cond = ALWAYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) lpend.forever = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) lpend.loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) lpend.bjump = off - ljmp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) off += _emit_LPEND(dry_run, &buf[off], &lpend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) *bursts = lcnt1 * cyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (lcnt0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) *bursts *= lcnt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static int _period(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) unsigned long bursts, const struct _xfer_spec *pxs, int ev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) unsigned int lcnt1, ljmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) int cyc, off = 0, num_dregs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) struct _arg_LPEND lpend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) struct pl330_xfer *x = &pxs->desc->px;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (bursts > 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) lcnt1 = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) cyc = bursts / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) lcnt1 = bursts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) cyc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* loop1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) ljmp1 = off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) lpend.cond = ALWAYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) lpend.forever = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) lpend.loop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) lpend.bjump = off - ljmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) off += _emit_LPEND(dry_run, &buf[off], &lpend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* remainder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) lcnt1 = bursts - (lcnt1 * cyc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (lcnt1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) ljmp1 = off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) off += _bursts(pl330, dry_run, &buf[off], pxs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) lpend.cond = ALWAYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) lpend.forever = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) lpend.loop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) lpend.bjump = off - ljmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) off += _emit_LPEND(dry_run, &buf[off], &lpend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #ifdef CONFIG_NO_GKI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (!pxs->desc->src_interlace_size &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) !pxs->desc->dst_interlace_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) num_dregs = BYTE_MOD_BURST_LEN(x->bytes, pxs->ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (num_dregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) num_dregs = BYTE_MOD_BURST_LEN(x->bytes, pxs->ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (num_dregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) off += _emit_SEV(dry_run, &buf[off], ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static inline int _loop_cyclic(struct pl330_dmac *pl330, unsigned int dry_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) u8 buf[], unsigned long bursts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) const struct _xfer_spec *pxs, int ev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) int off, periods, residue, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) unsigned int lcnt0, ljmp0, ljmpfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) struct _arg_LPEND lpend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) struct pl330_xfer *x = &pxs->desc->px;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) ljmpfe = off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) lcnt0 = pxs->desc->num_periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) periods = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) while (lcnt0 > 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) periods++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) lcnt0 = pxs->desc->num_periods / periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) residue = pxs->desc->num_periods % periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* forever loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /* loop0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) ljmp0 = off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) for (i = 0; i < periods; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) off += _period(pl330, dry_run, &buf[off], bursts, pxs, ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) lpend.cond = ALWAYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) lpend.forever = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) lpend.loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) lpend.bjump = off - ljmp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) off += _emit_LPEND(dry_run, &buf[off], &lpend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) for (i = 0; i < residue; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) off += _period(pl330, dry_run, &buf[off], bursts, pxs, ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) lpend.cond = ALWAYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) lpend.forever = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) lpend.loop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) lpend.bjump = off - ljmpfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) off += _emit_LPEND(dry_run, &buf[off], &lpend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) static inline int _setup_loops(struct pl330_dmac *pl330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) const struct _xfer_spec *pxs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) struct pl330_xfer *x = &pxs->desc->px;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) u32 ccr = pxs->ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) BRST_SIZE(ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) #ifdef CONFIG_NO_GKI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) if (pxs->desc->rqtype == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) bursts = x->bytes / (BRST_SIZE(ccr) * BRST_LEN(ccr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) pxs->desc->dst_interlace_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) else if (pxs->desc->rqtype == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) bursts = x->bytes / (BRST_SIZE(ccr) * BRST_LEN(ccr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) pxs->desc->src_interlace_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) while (bursts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) c = bursts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) off += _loop(pl330, dry_run, &buf[off], &c, pxs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) bursts -= c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #ifdef CONFIG_NO_GKI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (!pxs->desc->src_interlace_size &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) !pxs->desc->dst_interlace_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static inline int _setup_xfer(struct pl330_dmac *pl330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) unsigned dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) const struct _xfer_spec *pxs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) struct pl330_xfer *x = &pxs->desc->px;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /* DMAMOV SAR, x->src_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /* DMAMOV DAR, x->dst_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* Setup Loop(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) off += _setup_loops(pl330, dry_run, &buf[off], pxs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static inline int _setup_xfer_cyclic(struct pl330_dmac *pl330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) unsigned int dry_run, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) const struct _xfer_spec *pxs, int ev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) struct pl330_xfer *x = &pxs->desc->px;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) u32 ccr = pxs->ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) unsigned long bursts = BYTE_TO_BURST(x->bytes, ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #ifdef CONFIG_NO_GKI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (pxs->desc->rqtype == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) bursts = x->bytes / (BRST_SIZE(ccr) * BRST_LEN(ccr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) + pxs->desc->dst_interlace_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) else if (pxs->desc->rqtype == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) bursts = x->bytes / (BRST_SIZE(ccr) * BRST_LEN(ccr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) + pxs->desc->src_interlace_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /* Setup Loop(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) off += _loop_cyclic(pl330, dry_run, &buf[off], bursts, pxs, ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) * A req is a sequence of one or more xfer units.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) * Returns the number of bytes taken to setup the MC for the req.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) struct pl330_thread *thrd, unsigned index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) struct _xfer_spec *pxs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) struct _pl330_req *req = &thrd->req[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) u8 *buf = req->mc_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) PL330_DBGMC_START(req->mc_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /* DMAMOV CCR, ccr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (!pxs->desc->cyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* DMASEV peripheral/event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) off += _emit_SEV(dry_run, &buf[off], thrd->ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /* DMAEND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) off += _emit_END(dry_run, &buf[off]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) off += _setup_xfer_cyclic(pl330, dry_run, &buf[off],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) pxs, thrd->ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) u32 ccr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (rqc->src_inc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ccr |= CC_SRCINC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (rqc->dst_inc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) ccr |= CC_DSTINC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) /* We set same protection levels for Src and DST for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (rqc->privileged)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) ccr |= CC_SRCPRI | CC_DSTPRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (rqc->nonsecure)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ccr |= CC_SRCNS | CC_DSTNS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (rqc->insnaccess)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ccr |= CC_SRCIA | CC_DSTIA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) ccr |= (rqc->swap << CC_SWAP_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) * Submit a list of xfers after which the client wants notification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) * Client is not notified after each xfer unit, just once after all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) * xfer units are done or some error occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static int pl330_submit_req(struct pl330_thread *thrd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) struct dma_pl330_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) struct pl330_dmac *pl330 = thrd->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) struct _xfer_spec xs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) unsigned idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) u32 ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) switch (desc->rqtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) case DMA_MEM_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (pl330->state == DYING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) /* If request for non-existing peripheral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (desc->rqtype != DMA_MEM_TO_MEM &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) desc->peri >= pl330->pcfg.num_peri) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) dev_info(thrd->dmac->ddma.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) "%s:%d Invalid peripheral(%u)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) __func__, __LINE__, desc->peri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) spin_lock_irqsave(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (_queue_full(thrd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) goto xfer_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /* Prefer Secure Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) if (!_manager_ns(thrd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) desc->rqcfg.nonsecure = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) desc->rqcfg.nonsecure = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) ccr = _prepare_ccr(&desc->rqcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) idx = thrd->req[0].desc == NULL ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) xs.ccr = ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) xs.desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) /* First dry run to check if req is acceptable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) ret = _setup_req(pl330, 1, thrd, idx, &xs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) goto xfer_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (ret > pl330->mcbufsz / 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) __func__, __LINE__, ret, pl330->mcbufsz / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) goto xfer_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /* Hook the request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) thrd->lstenq = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) thrd->req[idx].desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) _setup_req(pl330, 0, thrd, idx, &xs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) xfer_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) spin_unlock_irqrestore(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) struct dma_pl330_chan *pch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) pch = desc->pchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /* If desc aborted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (!pch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) spin_lock_irqsave(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) desc->status = DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) spin_unlock_irqrestore(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) tasklet_schedule(&pch->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) static void pl330_dotask(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) struct pl330_dmac *pl330 = from_tasklet(pl330, t, tasks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) spin_lock_irqsave(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) /* The DMAC itself gone nuts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (pl330->dmac_tbd.reset_dmac) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) pl330->state = DYING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) /* Reset the manager too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) pl330->dmac_tbd.reset_mngr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) /* Clear the reset flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) pl330->dmac_tbd.reset_dmac = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if (pl330->dmac_tbd.reset_mngr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) _stop(pl330->manager);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) /* Reset all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) /* Clear the reset flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) pl330->dmac_tbd.reset_mngr = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) for (i = 0; i < pl330->pcfg.num_chan; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (pl330->dmac_tbd.reset_chan & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct pl330_thread *thrd = &pl330->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) void __iomem *regs = pl330->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) enum pl330_op_err err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) _stop(thrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (readl(regs + FSC) & (1 << thrd->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) err = PL330_ERR_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) err = PL330_ERR_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) spin_unlock_irqrestore(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) spin_lock_irqsave(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) thrd->req[0].desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) thrd->req[1].desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) thrd->req_running = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) /* Clear the reset flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) pl330->dmac_tbd.reset_chan &= ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) spin_unlock_irqrestore(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /* Returns 1 if state was updated, 0 otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) static int pl330_update(struct pl330_dmac *pl330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) struct dma_pl330_desc *descdone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) int id, ev, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) regs = pl330->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) spin_lock_irqsave(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) val = readl(regs + FSM) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) pl330->dmac_tbd.reset_mngr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) pl330->dmac_tbd.reset_mngr = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) pl330->dmac_tbd.reset_chan |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) while (i < pl330->pcfg.num_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (val & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) dev_info(pl330->ddma.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) "Reset Channel-%d\t CS-%x FTC-%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) i, readl(regs + CS(i)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) readl(regs + FTC(i)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) _stop(&pl330->channels[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) /* Check which event happened i.e, thread notified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) val = readl(regs + ES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) if (pl330->pcfg.num_events < 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) && val & ~((1 << pl330->pcfg.num_events) - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) pl330->dmac_tbd.reset_dmac = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) goto updt_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) if (val & (1 << ev)) { /* Event occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) struct pl330_thread *thrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) u32 inten = readl(regs + INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) int active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) /* Clear the event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (inten & (1 << ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) writel(1 << ev, regs + INTCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) id = pl330->events[ev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) thrd = &pl330->channels[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) active = thrd->req_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (active == -1) /* Aborted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) /* Detach the req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) descdone = thrd->req[active].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) if (descdone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (!descdone->cyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) thrd->req[active].desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) thrd->req_running = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) /* Get going again ASAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) _start(thrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) /* For now, just make a list of callbacks to be done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) list_add_tail(&descdone->rqd, &pl330->req_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) /* Now that we are in no hurry, do the callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) while (!list_empty(&pl330->req_done)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) descdone = list_first_entry(&pl330->req_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) struct dma_pl330_desc, rqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) list_del(&descdone->rqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) spin_unlock_irqrestore(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) dma_pl330_rqcb(descdone, PL330_ERR_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) spin_lock_irqsave(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) updt_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) spin_unlock_irqrestore(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) if (pl330->dmac_tbd.reset_dmac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) || pl330->dmac_tbd.reset_mngr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) || pl330->dmac_tbd.reset_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) tasklet_schedule(&pl330->tasks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) /* Reserve an event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static inline int _alloc_event(struct pl330_thread *thrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) struct pl330_dmac *pl330 = thrd->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) int ev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) for (ev = 0; ev < pl330->pcfg.num_events; ev++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) if (pl330->events[ev] == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) pl330->events[ev] = thrd->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) return ev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) static bool _chan_ns(const struct pl330_dmac *pl330, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) return pl330->pcfg.irq_ns & (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* Upon success, returns IdentityToken for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) * allocated channel, NULL otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) struct pl330_thread *thrd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) int chans, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (pl330->state == DYING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) chans = pl330->pcfg.num_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) for (i = 0; i < chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) thrd = &pl330->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if ((thrd->free) && (!_manager_ns(thrd) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) _chan_ns(pl330, i))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) thrd->ev = _alloc_event(thrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if (thrd->ev >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) thrd->free = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) thrd->lstenq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) thrd->req[0].desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) thrd->req[1].desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) thrd->req_running = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) thrd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) return thrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) /* Release an event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) static inline void _free_event(struct pl330_thread *thrd, int ev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) struct pl330_dmac *pl330 = thrd->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) /* If the event is valid and was held by the thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (ev >= 0 && ev < pl330->pcfg.num_events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) && pl330->events[ev] == thrd->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) pl330->events[ev] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) static void pl330_release_channel(struct pl330_thread *thrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if (!thrd || thrd->free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) _stop(thrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) _free_event(thrd, thrd->ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) thrd->free = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /* Initialize the structure for PL330 configuration, that can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) * by the client driver the make best use of the DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) static void read_dmac_config(struct pl330_dmac *pl330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) void __iomem *regs = pl330->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) val &= CRD_DATA_WIDTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) pl330->pcfg.data_bus_width = 8 * (1 << val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) val &= CRD_DATA_BUFF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) pl330->pcfg.data_buf_dep = val + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) val &= CR0_NUM_CHANS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) val += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) pl330->pcfg.num_chan = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) val = readl(regs + CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) if (val & CR0_PERIPH_REQ_SET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) val += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) pl330->pcfg.num_peri = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) pl330->pcfg.peri_ns = readl(regs + CR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) pl330->pcfg.num_peri = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) val = readl(regs + CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) if (val & CR0_BOOT_MAN_NS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) pl330->pcfg.mode |= DMAC_MODE_NS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) pl330->pcfg.mode &= ~DMAC_MODE_NS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) val &= CR0_NUM_EVENTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) val += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) pl330->pcfg.num_events = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) pl330->pcfg.irq_ns = readl(regs + CR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) static inline void _reset_thread(struct pl330_thread *thrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) struct pl330_dmac *pl330 = thrd->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) thrd->req[0].mc_cpu = pl330->mcode_cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) + (thrd->id * pl330->mcbufsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) thrd->req[0].mc_bus = pl330->mcode_bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) + (thrd->id * pl330->mcbufsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) thrd->req[0].desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) + pl330->mcbufsz / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) thrd->req[1].mc_bus = thrd->req[0].mc_bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) + pl330->mcbufsz / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) thrd->req[1].desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) thrd->req_running = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) static int dmac_alloc_threads(struct pl330_dmac *pl330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) int chans = pl330->pcfg.num_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) struct pl330_thread *thrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) /* Allocate 1 Manager and 'chans' Channel threads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) pl330->channels = kcalloc(1 + chans, sizeof(*thrd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (!pl330->channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) /* Init Channel threads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) for (i = 0; i < chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) thrd = &pl330->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) thrd->id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) thrd->dmac = pl330;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) _reset_thread(thrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) thrd->free = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) /* MANAGER is indexed at the end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) thrd = &pl330->channels[chans];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) thrd->id = chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) thrd->dmac = pl330;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) thrd->free = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) pl330->manager = thrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) static int dmac_alloc_resources(struct pl330_dmac *pl330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) int chans = pl330->pcfg.num_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) * Alloc MicroCode buffer for 'chans' Channel threads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) chans * pl330->mcbufsz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) &pl330->mcode_bus, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) DMA_ATTR_PRIVILEGED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) if (!pl330->mcode_cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) ret = dmac_alloc_threads(pl330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) dma_free_attrs(pl330->ddma.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) chans * pl330->mcbufsz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) pl330->mcode_cpu, pl330->mcode_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) DMA_ATTR_PRIVILEGED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) static int pl330_add(struct pl330_dmac *pl330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) /* Check if we can handle this DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) pl330->pcfg.periph_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) /* Read the configuration of the DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) read_dmac_config(pl330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) if (pl330->pcfg.num_events == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) spin_lock_init(&pl330->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) INIT_LIST_HEAD(&pl330->req_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) /* Use default MC buffer size if not provided */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) if (!pl330->mcbufsz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) /* Mark all events as free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) for (i = 0; i < pl330->pcfg.num_events; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) pl330->events[i] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) /* Allocate resources needed by the DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) ret = dmac_alloc_resources(pl330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) tasklet_setup(&pl330->tasks, pl330_dotask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) pl330->state = INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) static int dmac_free_threads(struct pl330_dmac *pl330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) struct pl330_thread *thrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) /* Release Channel threads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) for (i = 0; i < pl330->pcfg.num_chan; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) thrd = &pl330->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) pl330_release_channel(thrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) /* Free memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) kfree(pl330->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) static void pl330_del(struct pl330_dmac *pl330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) pl330->state = UNINIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) tasklet_kill(&pl330->tasks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) /* Free DMAC resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) dmac_free_threads(pl330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) dma_free_attrs(pl330->ddma.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) pl330->mcode_bus, DMA_ATTR_PRIVILEGED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) /* forward declaration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) static struct amba_driver pl330_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) static inline struct dma_pl330_chan *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) to_pchan(struct dma_chan *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) if (!ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) return container_of(ch, struct dma_pl330_chan, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) static inline struct dma_pl330_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) to_desc(struct dma_async_tx_descriptor *tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) return container_of(tx, struct dma_pl330_desc, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static inline void fill_queue(struct dma_pl330_chan *pch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) struct dma_pl330_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) list_for_each_entry(desc, &pch->work_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) /* If already submitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) if (desc->status == BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) ret = pl330_submit_req(pch->thread, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) desc->status = BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) } else if (ret == -EAGAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) /* QFull or DMAC Dying */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) /* Unacceptable request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) desc->status = DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) __func__, __LINE__, desc->txd.cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) tasklet_schedule(&pch->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) static void pl330_tasklet(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) struct dma_pl330_chan *pch = from_tasklet(pch, t, task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) struct dma_pl330_desc *desc, *_dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) bool power_down = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) spin_lock_irqsave(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) /* Pick up ripe tomatoes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) list_for_each_entry_safe(desc, _dt, &pch->work_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) if (desc->status == DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (!desc->cyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) dma_cookie_complete(&desc->txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) list_move_tail(&desc->node, &pch->completed_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) struct dmaengine_desc_callback cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) desc->status = BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) dmaengine_desc_get_callback(&desc->txd, &cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) if (dmaengine_desc_callback_valid(&cb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) spin_unlock_irqrestore(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) dmaengine_desc_callback_invoke(&cb, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) spin_lock_irqsave(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) /* Try to submit a req imm. next to the last completed cookie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) fill_queue(pch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) if (list_empty(&pch->work_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) spin_lock(&pch->thread->dmac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) _stop(pch->thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) spin_unlock(&pch->thread->dmac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) power_down = pch->active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) pch->active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) /* Make sure the PL330 Channel thread is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) spin_lock(&pch->thread->dmac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) _start(pch->thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) spin_unlock(&pch->thread->dmac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) while (!list_empty(&pch->completed_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) struct dmaengine_desc_callback cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) desc = list_first_entry(&pch->completed_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) struct dma_pl330_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) dmaengine_desc_get_callback(&desc->txd, &cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) desc->status = FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) list_move_tail(&desc->node, &pch->dmac->desc_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) dma_descriptor_unmap(&desc->txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) if (dmaengine_desc_callback_valid(&cb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) spin_unlock_irqrestore(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) dmaengine_desc_callback_invoke(&cb, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) spin_lock_irqsave(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) spin_unlock_irqrestore(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) /* If work list empty, power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) if (power_down) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) int count = dma_spec->args_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) struct pl330_dmac *pl330 = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) unsigned int chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) if (!pl330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) if (count != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) chan_id = dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) if (chan_id >= pl330->num_peripherals)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) static int pl330_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) struct dma_pl330_chan *pch = to_pchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) struct pl330_dmac *pl330 = pch->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) spin_lock_irqsave(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) dma_cookie_init(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) pch->thread = pl330_request_channel(pl330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) if (!pch->thread) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) spin_unlock_irqrestore(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) tasklet_setup(&pch->task, pl330_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) spin_unlock_irqrestore(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) * We need the data direction between the DMAC (the dma-mapping "device") and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) static enum dma_data_direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) pl330_dma_slave_map_dir(enum dma_transfer_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) return DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) return DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) case DMA_DEV_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) return DMA_BIDIRECTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) return DMA_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) if (pch->dir != DMA_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) 1 << pch->burst_sz, pch->dir, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) pch->dir = DMA_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) enum dma_transfer_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) struct device *dev = pch->chan.device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) /* Already mapped for this config? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if (pch->dir == dma_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) pl330_unprep_slave_fifo(pch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) 1 << pch->burst_sz, dma_dir, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) if (dma_mapping_error(dev, pch->fifo_dma))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) pch->dir = dma_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) static int fixup_burst_len(int max_burst_len, int quirks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) if (max_burst_len > PL330_MAX_BURST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) return PL330_MAX_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) else if (max_burst_len < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) return max_burst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) static int pl330_config_write(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) struct dma_slave_config *slave_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) enum dma_transfer_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) struct dma_pl330_chan *pch = to_pchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) pl330_unprep_slave_fifo(pch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) if (direction == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) if (slave_config->dst_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) pch->fifo_addr = slave_config->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) if (slave_config->dst_addr_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) pch->burst_sz = __ffs(slave_config->dst_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) #ifdef CONFIG_NO_GKI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) if (slave_config->src_interlace_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) pch->slave_config.src_interlace_size = slave_config->src_interlace_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) pch->burst_len = fixup_burst_len(slave_config->dst_maxburst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) pch->dmac->quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) } else if (direction == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) if (slave_config->src_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) pch->fifo_addr = slave_config->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) if (slave_config->src_addr_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) pch->burst_sz = __ffs(slave_config->src_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) #ifdef CONFIG_NO_GKI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) if (slave_config->dst_interlace_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) pch->slave_config.dst_interlace_size = slave_config->dst_interlace_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) pch->burst_len = fixup_burst_len(slave_config->src_maxburst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) pch->dmac->quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) static int pl330_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) struct dma_slave_config *slave_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) struct dma_pl330_chan *pch = to_pchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) memcpy(&pch->slave_config, slave_config, sizeof(*slave_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) static int pl330_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) struct dma_pl330_chan *pch = to_pchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) struct dma_pl330_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) struct pl330_dmac *pl330 = pch->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) bool power_down = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) pm_runtime_get_sync(pl330->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) spin_lock_irqsave(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) spin_lock(&pl330->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) _stop(pch->thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) pch->thread->req[0].desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) pch->thread->req[1].desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) pch->thread->req_running = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) spin_unlock(&pl330->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) power_down = pch->active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) pch->active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) /* Mark all desc done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) list_for_each_entry(desc, &pch->submitted_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) desc->status = FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) dma_cookie_complete(&desc->txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) list_for_each_entry(desc, &pch->work_list , node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) desc->status = FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) dma_cookie_complete(&desc->txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) spin_unlock_irqrestore(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) pm_runtime_mark_last_busy(pl330->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) if (power_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) pm_runtime_put_autosuspend(pl330->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) pm_runtime_put_autosuspend(pl330->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) * We don't support DMA_RESUME command because of hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) * limitations, so after pausing the channel we cannot restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) * it to active state. We have to terminate channel and setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) * DMA transfer again. This pause feature was implemented to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) * allow safely read residue before channel termination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) static int pl330_pause(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) struct dma_pl330_chan *pch = to_pchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) struct pl330_dmac *pl330 = pch->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) pm_runtime_get_sync(pl330->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) spin_lock_irqsave(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) spin_lock(&pl330->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) _stop(pch->thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) spin_unlock(&pl330->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) spin_unlock_irqrestore(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) pm_runtime_mark_last_busy(pl330->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) pm_runtime_put_autosuspend(pl330->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) static void pl330_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) struct dma_pl330_chan *pch = to_pchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) struct pl330_dmac *pl330 = pch->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) tasklet_kill(&pch->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) pm_runtime_get_sync(pch->dmac->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) spin_lock_irqsave(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) pl330_release_channel(pch->thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) pch->thread = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) spin_unlock_irqrestore(&pl330->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) pl330_unprep_slave_fifo(pch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) struct dma_pl330_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) struct pl330_thread *thrd = pch->thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) struct pl330_dmac *pl330 = pch->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) void __iomem *regs = thrd->dmac->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) u32 val, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) pm_runtime_get_sync(pl330->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) val = addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) if (desc->rqcfg.src_inc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) val = readl(regs + SA(thrd->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) addr = desc->px.src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) val = readl(regs + DA(thrd->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) addr = desc->px.dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) pm_runtime_put_autosuspend(pl330->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) return val - addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) static enum dma_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) enum dma_status ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) struct dma_pl330_chan *pch = to_pchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) unsigned int transferred, residual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) ret = dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) if (!txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) if (ret == DMA_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) spin_lock_irqsave(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) spin_lock(&pch->thread->dmac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) if (pch->thread->req_running != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) running = pch->thread->req[pch->thread->req_running].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) last_enq = pch->thread->req[pch->thread->lstenq].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) /* Check in pending list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) list_for_each_entry(desc, &pch->work_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) if (desc->status == DONE && !desc->cyclic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) transferred = desc->bytes_requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) else if (running && desc == running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) transferred =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) pl330_get_current_xferred_count(pch, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) else if (desc->status == BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) * Busy but not running means either just enqueued,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) * or finished and not yet marked done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) if (desc == last_enq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) transferred = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) transferred = desc->bytes_requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) transferred = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) residual += desc->bytes_requested - transferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) if (desc->txd.cookie == cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) switch (desc->status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) case DONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) ret = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) case PREP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) case BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) ret = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) if (desc->last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) residual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) spin_unlock(&pch->thread->dmac->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) spin_unlock_irqrestore(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) dma_set_residue(txstate, residual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static void pl330_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) struct dma_pl330_chan *pch = to_pchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) spin_lock_irqsave(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) if (list_empty(&pch->work_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) * Warn on nothing pending. Empty submitted_list may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) * break our pm_runtime usage counter as it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) * updated on work_list emptiness status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) WARN_ON(list_empty(&pch->submitted_list));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) pch->active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) pm_runtime_get_sync(pch->dmac->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) list_splice_tail_init(&pch->submitted_list, &pch->work_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) spin_unlock_irqrestore(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) pl330_tasklet(&pch->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) * We returned the last one of the circular list of descriptor(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) * from prep_xxx, so the argument to submit corresponds to the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) * descriptor of the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) struct dma_pl330_desc *desc, *last = to_desc(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) struct dma_pl330_chan *pch = to_pchan(tx->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) spin_lock_irqsave(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) /* Assign cookies to all nodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) while (!list_empty(&last->node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) desc = list_entry(last->node.next, struct dma_pl330_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) desc->last = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) dma_cookie_assign(&desc->txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) list_move_tail(&desc->node, &pch->submitted_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) last->last = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) cookie = dma_cookie_assign(&last->txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) list_add_tail(&last->node, &pch->submitted_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) spin_unlock_irqrestore(&pch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) return cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) static inline void _init_desc(struct dma_pl330_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) desc->rqcfg.swap = SWAP_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) desc->rqcfg.scctl = CCTRL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) desc->rqcfg.dcctl = CCTRL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) desc->txd.tx_submit = pl330_tx_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) INIT_LIST_HEAD(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) /* Returns the number of descriptors added to the DMAC pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) static int add_desc(struct list_head *pool, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) gfp_t flg, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) struct dma_pl330_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) desc = kcalloc(count, sizeof(*desc), flg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) spin_lock_irqsave(lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) _init_desc(&desc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) list_add_tail(&desc[i].node, pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) spin_unlock_irqrestore(lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) static struct dma_pl330_desc *pluck_desc(struct list_head *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) struct dma_pl330_desc *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) spin_lock_irqsave(lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) if (!list_empty(pool)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) desc = list_entry(pool->next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) struct dma_pl330_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) list_del_init(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) desc->status = PREP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) desc->txd.callback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) spin_unlock_irqrestore(lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) struct pl330_dmac *pl330 = pch->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) u8 *peri_id = pch->chan.private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) struct dma_pl330_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) /* Pluck one desc from the pool of DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) /* If the DMAC pool is empty, alloc new */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) DEFINE_SPINLOCK(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) LIST_HEAD(pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) desc = pluck_desc(&pool, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) WARN_ON(!desc || !list_empty(&pool));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) /* Initialize the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) desc->pchan = pch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) desc->txd.cookie = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) async_tx_ack(&desc->txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) desc->peri = peri_id ? pch->chan.chan_id : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) desc->rqcfg.pcfg = &pch->dmac->pcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) desc->cyclic = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) desc->num_periods = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) static inline void fill_px(struct pl330_xfer *px,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) dma_addr_t dst, dma_addr_t src, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) px->bytes = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) px->dst_addr = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) px->src_addr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) static struct dma_pl330_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) dma_addr_t src, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) struct dma_pl330_desc *desc = pl330_get_desc(pch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) * Ideally we should lookout for reqs bigger than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) * those that can be programmed with 256 bytes of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) * MC buffer, but considering a req size is seldom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) * going to be word-unaligned and more than 200MB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) * we take it easy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) * Also, should the limit is reached we'd rather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) * have the platform increase MC buffer size than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) * complicating this API driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) fill_px(&desc->px, dst, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) /* Call after fixing burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) struct dma_pl330_chan *pch = desc->pchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) struct pl330_dmac *pl330 = pch->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) int burst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) burst_len = pl330->pcfg.data_bus_width / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) burst_len >>= desc->rqcfg.brst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) /* src/dst_burst_len can't be more than 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) if (burst_len > PL330_MAX_BURST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) burst_len = PL330_MAX_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) return burst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) size_t period_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) struct dma_pl330_desc *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) struct dma_pl330_chan *pch = to_pchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) dma_addr_t dst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) dma_addr_t src = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) if (len % period_len != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) if (!is_slave_direction(direction)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) pl330_config_write(chan, &pch->slave_config, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) if (!pl330_prep_slave_fifo(pch, direction))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) desc = pl330_get_desc(pch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) desc->rqcfg.src_inc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) desc->rqcfg.dst_inc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) src = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) dst = pch->fifo_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) desc->rqcfg.src_inc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) desc->rqcfg.dst_inc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) src = pch->fifo_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) dst = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) desc->rqtype = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) desc->rqcfg.brst_size = pch->burst_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) desc->rqcfg.brst_len = pch->burst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) desc->bytes_requested = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) fill_px(&desc->px, dst, src, period_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) desc->cyclic = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) desc->num_periods = len / period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) desc->txd.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) #ifdef CONFIG_NO_GKI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) desc->src_interlace_size = pch->slave_config.src_interlace_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) desc->dst_interlace_size = pch->slave_config.dst_interlace_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) return &desc->txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) dma_addr_t src, size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) struct dma_pl330_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) struct dma_pl330_chan *pch = to_pchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) struct pl330_dmac *pl330;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) int burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) if (unlikely(!pch || !len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) pl330 = pch->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) desc->rqcfg.src_inc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) desc->rqcfg.dst_inc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) desc->rqtype = DMA_MEM_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) /* Select max possible burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) burst = pl330->pcfg.data_bus_width / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) * Make sure we use a burst size that aligns with all the memcpy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) * parameters because our DMA programming algorithm doesn't cope with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) * transfers which straddle an entry in the DMA device's MFIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) while ((src | dst | len) & (burst - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) burst /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) desc->rqcfg.brst_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) while (burst != (1 << desc->rqcfg.brst_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) desc->rqcfg.brst_size++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) desc->rqcfg.brst_len = get_burst_len(desc, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) * If burst size is smaller than bus width then make sure we only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) * transfer one at a time to avoid a burst stradling an MFIFO entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) if (burst * 8 < pl330->pcfg.data_bus_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) desc->rqcfg.brst_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) desc->bytes_requested = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) desc->txd.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) return &desc->txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) static void __pl330_giveback_desc(struct pl330_dmac *pl330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) struct dma_pl330_desc *first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) struct dma_pl330_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) if (!first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) spin_lock_irqsave(&pl330->pool_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) while (!list_empty(&first->node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) desc = list_entry(first->node.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) struct dma_pl330_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) list_move_tail(&desc->node, &pl330->desc_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) list_move_tail(&first->node, &pl330->desc_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) spin_unlock_irqrestore(&pl330->pool_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) unsigned int sg_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) unsigned long flg, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) struct dma_pl330_desc *first, *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) struct dma_pl330_chan *pch = to_pchan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) if (unlikely(!pch || !sgl || !sg_len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) pl330_config_write(chan, &pch->slave_config, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) if (!pl330_prep_slave_fifo(pch, direction))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) first = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) for_each_sg(sgl, sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) desc = pl330_get_desc(pch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) struct pl330_dmac *pl330 = pch->dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) dev_err(pch->dmac->ddma.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) "%s:%d Unable to fetch desc\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) __pl330_giveback_desc(pl330, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) if (!first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) first = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) list_add_tail(&desc->node, &first->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) if (direction == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) desc->rqcfg.src_inc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) desc->rqcfg.dst_inc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) desc->rqcfg.src_inc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) desc->rqcfg.dst_inc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) desc->rqcfg.brst_size = pch->burst_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) desc->rqcfg.brst_len = pch->burst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) desc->rqtype = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) desc->bytes_requested = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) #ifdef CONFIG_NO_GKI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) desc->src_interlace_size = pch->slave_config.src_interlace_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) desc->dst_interlace_size = pch->slave_config.dst_interlace_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) /* Return the last desc in the chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) desc->txd.flags = flg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) return &desc->txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) static irqreturn_t pl330_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) if (pl330_update(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) #define PL330_DMA_BUSWIDTHS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) static int pl330_debugfs_show(struct seq_file *s, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) struct pl330_dmac *pl330 = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) int chans, pchs, ch, pr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) chans = pl330->pcfg.num_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) pchs = pl330->num_peripherals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) seq_puts(s, "PL330 physical channels:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) seq_puts(s, "THREAD:\t\tCHANNEL:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) seq_puts(s, "--------\t-----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) for (ch = 0; ch < chans; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) struct pl330_thread *thrd = &pl330->channels[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) int found = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) for (pr = 0; pr < pchs; pr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) struct dma_pl330_chan *pch = &pl330->peripherals[pr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) if (!pch->thread || thrd->id != pch->thread->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) found = pr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) seq_printf(s, "%d\t\t", thrd->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) if (found == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) seq_puts(s, "--\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) seq_printf(s, "%d\n", found);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) DEFINE_SHOW_ATTRIBUTE(pl330_debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) debugfs_create_file(dev_name(pl330->ddma.dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) S_IFREG | 0444, NULL, pl330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) &pl330_debugfs_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) * Runtime PM callbacks are provided by amba/bus.c driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) * bus driver will only disable/enable the clock in runtime PM callbacks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) static int __maybe_unused pl330_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) struct amba_device *pcdev = to_amba_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) amba_pclk_unprepare(pcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) static int __maybe_unused pl330_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) struct amba_device *pcdev = to_amba_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) ret = amba_pclk_prepare(pcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) static const struct dev_pm_ops pl330_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) SET_LATE_SYSTEM_SLEEP_PM_OPS(pl330_suspend, pl330_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) pl330_probe(struct amba_device *adev, const struct amba_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) struct pl330_config *pcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) struct pl330_dmac *pl330;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) struct dma_pl330_chan *pch, *_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) struct dma_device *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) int i, ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) int num_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) struct device_node *np = adev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) /* Allocate a new DMAC and its Channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) if (!pl330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) pd = &pl330->ddma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) pd->dev = &adev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) pl330->mcbufsz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) /* get quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) if (of_property_read_bool(np, of_quirks[i].quirk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) pl330->quirks |= of_quirks[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) res = &adev->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) pl330->base = devm_ioremap_resource(&adev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) if (IS_ERR(pl330->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) return PTR_ERR(pl330->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) amba_set_drvdata(adev, pl330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) pl330->rstc = devm_reset_control_get_optional(&adev->dev, "dma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) if (IS_ERR(pl330->rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc), "Failed to get reset!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) ret = reset_control_deassert(pl330->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) dev_err(&adev->dev, "Couldn't deassert the device from reset!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) pl330->rstc_ocp = devm_reset_control_get_optional(&adev->dev, "dma-ocp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) if (IS_ERR(pl330->rstc_ocp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc_ocp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) "Failed to get OCP reset!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) ret = reset_control_deassert(pl330->rstc_ocp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) dev_err(&adev->dev, "Couldn't deassert the device from OCP reset!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) for (i = 0; i < AMBA_NR_IRQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) irq = adev->irq[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) if (irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) ret = devm_request_irq(&adev->dev, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) pl330_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) dev_name(&adev->dev), pl330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) pcfg = &pl330->pcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) pcfg->periph_id = adev->periphid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) ret = pl330_add(pl330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) INIT_LIST_HEAD(&pl330->desc_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) spin_lock_init(&pl330->pool_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) /* Create a descriptor pool of default size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) if (!add_desc(&pl330->desc_pool, &pl330->pool_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) GFP_KERNEL, NR_DEFAULT_DESC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) dev_warn(&adev->dev, "unable to allocate desc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) INIT_LIST_HEAD(&pd->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) /* Initialize channel parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) pl330->num_peripherals = num_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) if (!pl330->peripherals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) goto probe_err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) for (i = 0; i < num_chan; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) pch = &pl330->peripherals[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) pch->chan.private = adev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) INIT_LIST_HEAD(&pch->submitted_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) INIT_LIST_HEAD(&pch->work_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) INIT_LIST_HEAD(&pch->completed_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) spin_lock_init(&pch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) pch->thread = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) pch->chan.device = pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) pch->dmac = pl330;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) pch->dir = DMA_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) /* Add the channel to the DMAC list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) list_add_tail(&pch->chan.device_node, &pd->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) dma_cap_set(DMA_MEMCPY, pd->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) if (pcfg->num_peri) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) dma_cap_set(DMA_SLAVE, pd->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) dma_cap_set(DMA_CYCLIC, pd->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) dma_cap_set(DMA_PRIVATE, pd->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) pd->device_free_chan_resources = pl330_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) pd->device_tx_status = pl330_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) pd->device_prep_slave_sg = pl330_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) pd->device_config = pl330_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) pd->device_pause = pl330_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) pd->device_terminate_all = pl330_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) pd->device_issue_pending = pl330_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) pd->max_burst = PL330_MAX_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) ret = dma_async_device_register(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) dev_err(&adev->dev, "unable to register DMAC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) goto probe_err3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) if (adev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) ret = of_dma_controller_register(adev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) of_dma_pl330_xlate, pl330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) dev_err(&adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) "unable to register DMA to the generic DT DMA helpers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) * This is the limit for transfers with a buswidth of 1, larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) * buswidths will have larger limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) ret = dma_set_max_seg_size(&adev->dev, 1900800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) dev_err(&adev->dev, "unable to set the seg size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) init_pl330_debugfs(pl330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) dev_info(&adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) dev_info(&adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) pcfg->num_peri, pcfg->num_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) pm_runtime_irq_safe(&adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) pm_runtime_use_autosuspend(&adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) pm_runtime_mark_last_busy(&adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) pm_runtime_put_autosuspend(&adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) probe_err3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) /* Idle the DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) chan.device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) /* Remove the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) list_del(&pch->chan.device_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) /* Flush the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) if (pch->thread) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) pl330_terminate_all(&pch->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) pl330_free_chan_resources(&pch->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) probe_err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) pl330_del(pl330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) if (pl330->rstc_ocp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) reset_control_assert(pl330->rstc_ocp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) if (pl330->rstc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) reset_control_assert(pl330->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) static void pl330_remove(struct amba_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) struct pl330_dmac *pl330 = amba_get_drvdata(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) struct dma_pl330_chan *pch, *_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) int i, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) pm_runtime_get_noresume(pl330->ddma.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) if (adev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) of_dma_controller_free(adev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) for (i = 0; i < AMBA_NR_IRQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) irq = adev->irq[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) if (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) devm_free_irq(&adev->dev, irq, pl330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) dma_async_device_unregister(&pl330->ddma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) /* Idle the DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) chan.device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) /* Remove the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) list_del(&pch->chan.device_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) /* Flush the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) if (pch->thread) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) pl330_terminate_all(&pch->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) pl330_free_chan_resources(&pch->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) pl330_del(pl330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) if (pl330->rstc_ocp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) reset_control_assert(pl330->rstc_ocp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) if (pl330->rstc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) reset_control_assert(pl330->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) static const struct amba_id pl330_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) .id = 0x00041330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) .mask = 0x000fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) MODULE_DEVICE_TABLE(amba, pl330_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) static struct amba_driver pl330_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) .drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) .name = "dma-pl330",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) .pm = &pl330_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) .id_table = pl330_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) .probe = pl330_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) .remove = pl330_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) module_amba_driver(pl330_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) MODULE_DESCRIPTION("API Driver for PL330 DMAC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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