^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Topcliff PCH DMA controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2010 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pch_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DRV_NAME "pch-dma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DMA_CTL0_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DMA_CTL0_SG 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DMA_CTL0_ONESHOT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DMA_CTL0_MODE_MASK_BITS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DMA_CTL0_DIR_SHIFT_BITS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DMA_CTL0_BITS_PER_CH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DMA_CTL2_START_SHIFT_BITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DMA_CTL2_IRQ_ENABLE_MASK ((1UL << DMA_CTL2_START_SHIFT_BITS) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DMA_STATUS_IDLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DMA_STATUS_DESC_READ 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DMA_STATUS_WAIT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DMA_STATUS_ACCESS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DMA_STATUS_BITS_PER_CH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DMA_STATUS_MASK_BITS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DMA_STATUS_SHIFT_BITS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DMA_STATUS_IRQ(x) (0x1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DMA_STATUS0_ERR(x) (0x1 << ((x) + 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DMA_STATUS2_ERR(x) (0x1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DMA_DESC_WIDTH_SHIFT_BITS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DMA_DESC_WIDTH_1_BYTE (0x3 << DMA_DESC_WIDTH_SHIFT_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DMA_DESC_WIDTH_2_BYTES (0x2 << DMA_DESC_WIDTH_SHIFT_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DMA_DESC_WIDTH_4_BYTES (0x0 << DMA_DESC_WIDTH_SHIFT_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DMA_DESC_MAX_COUNT_1_BYTE 0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DMA_DESC_MAX_COUNT_2_BYTES 0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DMA_DESC_MAX_COUNT_4_BYTES 0x7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DMA_DESC_END_WITHOUT_IRQ 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DMA_DESC_END_WITH_IRQ 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DMA_DESC_FOLLOW_WITHOUT_IRQ 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DMA_DESC_FOLLOW_WITH_IRQ 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MAX_CHAN_NR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DMA_MASK_CTL0_MODE 0x33333333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DMA_MASK_CTL2_MODE 0x00003333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static unsigned int init_nr_desc_per_channel = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) module_param(init_nr_desc_per_channel, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_PARM_DESC(init_nr_desc_per_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "initial descriptors per channel (default: 64)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct pch_dma_desc_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct pch_dma_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 dma_ctl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 dma_ctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 dma_ctl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 dma_ctl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 dma_sts0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 dma_sts1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 dma_sts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct pch_dma_desc_regs desc[MAX_CHAN_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct pch_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct pch_dma_desc_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct dma_async_tx_descriptor txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct list_head desc_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct list_head tx_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct pch_dma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct dma_chan chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enum dma_transfer_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct tasklet_struct tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long err_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct list_head active_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct list_head free_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int descs_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PDC_DEV_ADDR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PDC_MEM_ADDR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PDC_SIZE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PDC_NEXT 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define channel_readl(pdc, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) readl((pdc)->membase + PDC_##name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define channel_writel(pdc, name, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel((val), (pdc)->membase + PDC_##name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct pch_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct dma_device dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct dma_pool *pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct pch_dma_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct pch_dma_desc_regs ch_regs[MAX_CHAN_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct pch_dma_chan channels[MAX_CHAN_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCH_DMA_CTL0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCH_DMA_CTL1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PCH_DMA_CTL2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCH_DMA_CTL3 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PCH_DMA_STS0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PCH_DMA_STS1 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PCH_DMA_STS2 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define dma_readl(pd, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) readl((pd)->membase + PCH_DMA_##name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define dma_writel(pd, name, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel((val), (pd)->membase + PCH_DMA_##name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct pch_dma_desc *to_pd_desc(struct dma_async_tx_descriptor *txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return container_of(txd, struct pch_dma_desc, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline struct pch_dma_chan *to_pd_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return container_of(chan, struct pch_dma_chan, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static inline struct pch_dma *to_pd(struct dma_device *ddev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return container_of(ddev, struct pch_dma, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static inline struct device *chan2dev(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return &chan->dev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static inline struct device *chan2parent(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return chan->dev->device.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct pch_dma_desc *pdc_first_active(struct pch_dma_chan *pd_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return list_first_entry(&pd_chan->active_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct pch_dma_desc, desc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct pch_dma_desc *pdc_first_queued(struct pch_dma_chan *pd_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return list_first_entry(&pd_chan->queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct pch_dma_desc, desc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void pdc_enable_irq(struct dma_chan *chan, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct pch_dma *pd = to_pd(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (chan->chan_id < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pos = chan->chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pos = chan->chan_id + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val = dma_readl(pd, CTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val |= 0x1 << pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val &= ~(0x1 << pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dma_writel(pd, CTL2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev_dbg(chan2dev(chan), "pdc_enable_irq: chan %d -> %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) chan->chan_id, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void pdc_set_dir(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct pch_dma_chan *pd_chan = to_pd_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct pch_dma *pd = to_pd(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 mask_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 mask_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (chan->chan_id < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val = dma_readl(pd, CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mask_mode = DMA_CTL0_MODE_MASK_BITS <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) (DMA_CTL0_BITS_PER_CH * chan->chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) (DMA_CTL0_BITS_PER_CH * chan->chan_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) val &= mask_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (pd_chan->dir == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DMA_CTL0_DIR_SHIFT_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DMA_CTL0_DIR_SHIFT_BITS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) val |= mask_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dma_writel(pd, CTL0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val = dma_readl(pd, CTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mask_mode = DMA_CTL0_MODE_MASK_BITS <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) (DMA_CTL0_BITS_PER_CH * ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) (DMA_CTL0_BITS_PER_CH * ch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) val &= mask_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (pd_chan->dir == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) DMA_CTL0_DIR_SHIFT_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * ch +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) DMA_CTL0_DIR_SHIFT_BITS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) val |= mask_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dma_writel(pd, CTL3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_dbg(chan2dev(chan), "pdc_set_dir: chan %d -> %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) chan->chan_id, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void pdc_set_mode(struct dma_chan *chan, u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct pch_dma *pd = to_pd(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 mask_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 mask_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (chan->chan_id < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) (DMA_CTL0_BITS_PER_CH * chan->chan_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DMA_CTL0_DIR_SHIFT_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) val = dma_readl(pd, CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) val &= mask_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) val |= mode << (DMA_CTL0_BITS_PER_CH * chan->chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) val |= mask_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dma_writel(pd, CTL0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) (DMA_CTL0_BITS_PER_CH * ch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * ch +\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DMA_CTL0_DIR_SHIFT_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) val = dma_readl(pd, CTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) val &= mask_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) val |= mode << (DMA_CTL0_BITS_PER_CH * ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) val |= mask_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dma_writel(pd, CTL3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_dbg(chan2dev(chan), "pdc_set_mode: chan %d -> %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) chan->chan_id, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static u32 pdc_get_status0(struct pch_dma_chan *pd_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct pch_dma *pd = to_pd(pd_chan->chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) val = dma_readl(pd, STS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DMA_STATUS_BITS_PER_CH * pd_chan->chan.chan_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static u32 pdc_get_status2(struct pch_dma_chan *pd_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct pch_dma *pd = to_pd(pd_chan->chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) val = dma_readl(pd, STS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) DMA_STATUS_BITS_PER_CH * (pd_chan->chan.chan_id - 8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static bool pdc_is_idle(struct pch_dma_chan *pd_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (pd_chan->chan.chan_id < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) sts = pdc_get_status0(pd_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) sts = pdc_get_status2(pd_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (sts == DMA_STATUS_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void pdc_dostart(struct pch_dma_chan *pd_chan, struct pch_dma_desc* desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!pdc_is_idle(pd_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(chan2dev(&pd_chan->chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "BUG: Attempt to start non-idle channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> dev_addr: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pd_chan->chan.chan_id, desc->regs.dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> mem_addr: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pd_chan->chan.chan_id, desc->regs.mem_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> size: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pd_chan->chan.chan_id, desc->regs.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> next: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pd_chan->chan.chan_id, desc->regs.next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (list_empty(&desc->tx_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) channel_writel(pd_chan, SIZE, desc->regs.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) channel_writel(pd_chan, NEXT, desc->regs.next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pdc_set_mode(&pd_chan->chan, DMA_CTL0_ONESHOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) channel_writel(pd_chan, NEXT, desc->txd.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pdc_set_mode(&pd_chan->chan, DMA_CTL0_SG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void pdc_chain_complete(struct pch_dma_chan *pd_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct pch_dma_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct dma_async_tx_descriptor *txd = &desc->txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct dmaengine_desc_callback cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dmaengine_desc_get_callback(txd, &cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) list_splice_init(&desc->tx_list, &pd_chan->free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) list_move(&desc->desc_node, &pd_chan->free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dmaengine_desc_callback_invoke(&cb, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void pdc_complete_all(struct pch_dma_chan *pd_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct pch_dma_desc *desc, *_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) LIST_HEAD(list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) BUG_ON(!pdc_is_idle(pd_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!list_empty(&pd_chan->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pdc_dostart(pd_chan, pdc_first_queued(pd_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) list_splice_init(&pd_chan->active_list, &list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) list_splice_init(&pd_chan->queue, &pd_chan->active_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) list_for_each_entry_safe(desc, _d, &list, desc_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pdc_chain_complete(pd_chan, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static void pdc_handle_error(struct pch_dma_chan *pd_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct pch_dma_desc *bad_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) bad_desc = pdc_first_active(pd_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) list_del(&bad_desc->desc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) list_splice_init(&pd_chan->queue, pd_chan->active_list.prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!list_empty(&pd_chan->active_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pdc_dostart(pd_chan, pdc_first_active(pd_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_crit(chan2dev(&pd_chan->chan), "Bad descriptor submitted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_crit(chan2dev(&pd_chan->chan), "descriptor cookie: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) bad_desc->txd.cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pdc_chain_complete(pd_chan, bad_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static void pdc_advance_work(struct pch_dma_chan *pd_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (list_empty(&pd_chan->active_list) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) list_is_singular(&pd_chan->active_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pdc_complete_all(pd_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pdc_chain_complete(pd_chan, pdc_first_active(pd_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pdc_dostart(pd_chan, pdc_first_active(pd_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static dma_cookie_t pd_tx_submit(struct dma_async_tx_descriptor *txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct pch_dma_desc *desc = to_pd_desc(txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct pch_dma_chan *pd_chan = to_pd_chan(txd->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) spin_lock(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (list_empty(&pd_chan->active_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) list_add_tail(&desc->desc_node, &pd_chan->active_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pdc_dostart(pd_chan, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) list_add_tail(&desc->desc_node, &pd_chan->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) spin_unlock(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static struct pch_dma_desc *pdc_alloc_desc(struct dma_chan *chan, gfp_t flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct pch_dma_desc *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct pch_dma *pd = to_pd(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) desc = dma_pool_zalloc(pd->pool, flags, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) INIT_LIST_HEAD(&desc->tx_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dma_async_tx_descriptor_init(&desc->txd, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) desc->txd.tx_submit = pd_tx_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) desc->txd.flags = DMA_CTRL_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) desc->txd.phys = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static struct pch_dma_desc *pdc_desc_get(struct pch_dma_chan *pd_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct pch_dma_desc *desc, *_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct pch_dma_desc *ret = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) spin_lock(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) list_for_each_entry_safe(desc, _d, &pd_chan->free_list, desc_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (async_tx_test_ack(&desc->txd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) list_del(&desc->desc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_dbg(chan2dev(&pd_chan->chan), "desc %p not ACKed\n", desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) spin_unlock(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_dbg(chan2dev(&pd_chan->chan), "scanned %d descriptors\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = pdc_alloc_desc(&pd_chan->chan, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) spin_lock(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pd_chan->descs_allocated++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) spin_unlock(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_err(chan2dev(&pd_chan->chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "failed to alloc desc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static void pdc_desc_put(struct pch_dma_chan *pd_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct pch_dma_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) spin_lock(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) list_splice_init(&desc->tx_list, &pd_chan->free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) list_add(&desc->desc_node, &pd_chan->free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) spin_unlock(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int pd_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct pch_dma_chan *pd_chan = to_pd_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct pch_dma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) LIST_HEAD(tmp_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (!pdc_is_idle(pd_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!list_empty(&pd_chan->free_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return pd_chan->descs_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) for (i = 0; i < init_nr_desc_per_channel; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) desc = pdc_alloc_desc(chan, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_warn(chan2dev(chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "Only allocated %d initial descriptors\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) list_add_tail(&desc->desc_node, &tmp_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) spin_lock_irq(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) list_splice(&tmp_list, &pd_chan->free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pd_chan->descs_allocated = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dma_cookie_init(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) spin_unlock_irq(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) pdc_enable_irq(chan, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return pd_chan->descs_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void pd_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct pch_dma_chan *pd_chan = to_pd_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct pch_dma *pd = to_pd(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct pch_dma_desc *desc, *_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) LIST_HEAD(tmp_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) BUG_ON(!pdc_is_idle(pd_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) BUG_ON(!list_empty(&pd_chan->active_list));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) BUG_ON(!list_empty(&pd_chan->queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) spin_lock_irq(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) list_splice_init(&pd_chan->free_list, &tmp_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pd_chan->descs_allocated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) spin_unlock_irq(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) list_for_each_entry_safe(desc, _d, &tmp_list, desc_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dma_pool_free(pd->pool, desc, desc->txd.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pdc_enable_irq(chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static enum dma_status pd_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static void pd_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct pch_dma_chan *pd_chan = to_pd_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (pdc_is_idle(pd_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) spin_lock(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pdc_advance_work(pd_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) spin_unlock(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct scatterlist *sgl, unsigned int sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) enum dma_transfer_direction direction, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct pch_dma_chan *pd_chan = to_pd_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct pch_dma_slave *pd_slave = chan->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct pch_dma_desc *first = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct pch_dma_desc *prev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct pch_dma_desc *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dma_addr_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (unlikely(!sg_len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev_info(chan2dev(chan), "prep_slave_sg: length is zero!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (direction == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) reg = pd_slave->rx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) else if (direction == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) reg = pd_slave->tx_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pd_chan->dir = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pdc_set_dir(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) for_each_sg(sgl, sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) desc = pdc_desc_get(pd_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) goto err_desc_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) desc->regs.dev_addr = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) desc->regs.mem_addr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) desc->regs.size = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) desc->regs.next = DMA_DESC_FOLLOW_WITHOUT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) switch (pd_slave->width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) case PCH_DMA_WIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (desc->regs.size > DMA_DESC_MAX_COUNT_1_BYTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) goto err_desc_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) desc->regs.size |= DMA_DESC_WIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case PCH_DMA_WIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (desc->regs.size > DMA_DESC_MAX_COUNT_2_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) goto err_desc_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) desc->regs.size |= DMA_DESC_WIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case PCH_DMA_WIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (desc->regs.size > DMA_DESC_MAX_COUNT_4_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) goto err_desc_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) desc->regs.size |= DMA_DESC_WIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) goto err_desc_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) first = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) prev->regs.next |= desc->txd.phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) list_add_tail(&desc->desc_node, &first->tx_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) prev = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (flags & DMA_PREP_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) desc->regs.next = DMA_DESC_END_WITH_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) desc->regs.next = DMA_DESC_END_WITHOUT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) first->txd.cookie = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) desc->txd.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return &first->txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) err_desc_get:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev_err(chan2dev(chan), "failed to get desc or wrong parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pdc_desc_put(pd_chan, first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static int pd_device_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct pch_dma_chan *pd_chan = to_pd_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct pch_dma_desc *desc, *_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) LIST_HEAD(list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) spin_lock_irq(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) pdc_set_mode(&pd_chan->chan, DMA_CTL0_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) list_splice_init(&pd_chan->active_list, &list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) list_splice_init(&pd_chan->queue, &list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) list_for_each_entry_safe(desc, _d, &list, desc_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) pdc_chain_complete(pd_chan, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) spin_unlock_irq(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static void pdc_tasklet(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct pch_dma_chan *pd_chan = from_tasklet(pd_chan, t, tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!pdc_is_idle(pd_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_err(chan2dev(&pd_chan->chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) "BUG: handle non-idle channel in tasklet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) spin_lock_irqsave(&pd_chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (test_and_clear_bit(0, &pd_chan->err_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) pdc_handle_error(pd_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) pdc_advance_work(pd_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) spin_unlock_irqrestore(&pd_chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static irqreturn_t pd_irq(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct pch_dma *pd = (struct pch_dma *)devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct pch_dma_chan *pd_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u32 sts0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u32 sts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int ret0 = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int ret2 = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) sts0 = dma_readl(pd, STS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) sts2 = dma_readl(pd, STS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_dbg(pd->dma.dev, "pd_irq sts0: %x\n", sts0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) for (i = 0; i < pd->dma.chancnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) pd_chan = &pd->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (i < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (sts0 & DMA_STATUS_IRQ(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (sts0 & DMA_STATUS0_ERR(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) set_bit(0, &pd_chan->err_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) tasklet_schedule(&pd_chan->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret0 = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (sts2 & DMA_STATUS_IRQ(i - 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (sts2 & DMA_STATUS2_ERR(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) set_bit(0, &pd_chan->err_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) tasklet_schedule(&pd_chan->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret2 = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* clear interrupt bits in status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (ret0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dma_writel(pd, STS0, sts0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (ret2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dma_writel(pd, STS2, sts2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return ret0 | ret2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static void __maybe_unused pch_dma_save_regs(struct pch_dma *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct pch_dma_chan *pd_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct dma_chan *chan, *_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pd->regs.dma_ctl0 = dma_readl(pd, CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) pd->regs.dma_ctl1 = dma_readl(pd, CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pd->regs.dma_ctl2 = dma_readl(pd, CTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) pd->regs.dma_ctl3 = dma_readl(pd, CTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) pd_chan = to_pd_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) pd->ch_regs[i].size = channel_readl(pd_chan, SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) pd->ch_regs[i].next = channel_readl(pd_chan, NEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static void __maybe_unused pch_dma_restore_regs(struct pch_dma *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct pch_dma_chan *pd_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct dma_chan *chan, *_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dma_writel(pd, CTL0, pd->regs.dma_ctl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dma_writel(pd, CTL1, pd->regs.dma_ctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dma_writel(pd, CTL2, pd->regs.dma_ctl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dma_writel(pd, CTL3, pd->regs.dma_ctl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) pd_chan = to_pd_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) channel_writel(pd_chan, DEV_ADDR, pd->ch_regs[i].dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) channel_writel(pd_chan, MEM_ADDR, pd->ch_regs[i].mem_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) channel_writel(pd_chan, SIZE, pd->ch_regs[i].size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) channel_writel(pd_chan, NEXT, pd->ch_regs[i].next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int __maybe_unused pch_dma_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct pch_dma *pd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) pch_dma_save_regs(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int __maybe_unused pch_dma_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct pch_dma *pd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) pch_dma_restore_regs(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int pch_dma_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct pch_dma *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct pch_dma_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) unsigned int nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) nr_channels = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) pd = kzalloc(sizeof(*pd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (!pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) pci_set_drvdata(pdev, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dev_err(&pdev->dev, "Cannot enable PCI device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_err(&pdev->dev, "Cannot find proper base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) goto err_disable_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) err = pci_request_regions(pdev, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) goto err_disable_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_err(&pdev->dev, "Cannot set proper DMA config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) goto err_free_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) regs = pd->membase = pci_iomap(pdev, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (!pd->membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dev_err(&pdev->dev, "Cannot map MMIO registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) goto err_free_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) pd->dma.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) err = request_irq(pdev->irq, pd_irq, IRQF_SHARED, DRV_NAME, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_err(&pdev->dev, "Failed to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) pd->pool = dma_pool_create("pch_dma_desc_pool", &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) sizeof(struct pch_dma_desc), 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!pd->pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dev_err(&pdev->dev, "Failed to alloc DMA descriptors\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) INIT_LIST_HEAD(&pd->dma.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) for (i = 0; i < nr_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct pch_dma_chan *pd_chan = &pd->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) pd_chan->chan.device = &pd->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dma_cookie_init(&pd_chan->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) pd_chan->membase = ®s->desc[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) spin_lock_init(&pd_chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) INIT_LIST_HEAD(&pd_chan->active_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) INIT_LIST_HEAD(&pd_chan->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) INIT_LIST_HEAD(&pd_chan->free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) tasklet_setup(&pd_chan->tasklet, pdc_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) list_add_tail(&pd_chan->chan.device_node, &pd->dma.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dma_cap_zero(pd->dma.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dma_cap_set(DMA_PRIVATE, pd->dma.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dma_cap_set(DMA_SLAVE, pd->dma.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) pd->dma.device_alloc_chan_resources = pd_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) pd->dma.device_free_chan_resources = pd_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) pd->dma.device_tx_status = pd_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pd->dma.device_issue_pending = pd_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) pd->dma.device_prep_slave_sg = pd_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) pd->dma.device_terminate_all = pd_device_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) err = dma_async_device_register(&pd->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dev_err(&pdev->dev, "Failed to register DMA device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) goto err_free_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) err_free_pool:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dma_pool_destroy(pd->pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) free_irq(pdev->irq, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) err_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) pci_iounmap(pdev, pd->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) err_free_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) err_disable_pdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) err_free_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) kfree(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static void pch_dma_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct pch_dma *pd = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct pch_dma_chan *pd_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct dma_chan *chan, *_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (pd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) dma_async_device_unregister(&pd->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) free_irq(pdev->irq, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) list_for_each_entry_safe(chan, _c, &pd->dma.channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) pd_chan = to_pd_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) tasklet_kill(&pd_chan->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) dma_pool_destroy(pd->pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) pci_iounmap(pdev, pd->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) kfree(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* PCI Device ID of DMA device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define PCI_DEVICE_ID_EG20T_PCH_DMA_8CH 0x8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define PCI_DEVICE_ID_EG20T_PCH_DMA_4CH 0x8815
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define PCI_DEVICE_ID_ML7213_DMA1_8CH 0x8026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define PCI_DEVICE_ID_ML7213_DMA2_8CH 0x802B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define PCI_DEVICE_ID_ML7213_DMA3_4CH 0x8034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define PCI_DEVICE_ID_ML7213_DMA4_12CH 0x8032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define PCI_DEVICE_ID_ML7223_DMA1_4CH 0x800B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define PCI_DEVICE_ID_ML7223_DMA2_4CH 0x800E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define PCI_DEVICE_ID_ML7223_DMA3_4CH 0x8017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define PCI_DEVICE_ID_ML7223_DMA4_4CH 0x803B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define PCI_DEVICE_ID_ML7831_DMA1_8CH 0x8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define PCI_DEVICE_ID_ML7831_DMA2_4CH 0x8815
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static const struct pci_device_id pch_dma_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_8CH), 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_4CH), 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA1_8CH), 8}, /* UART Video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA2_8CH), 8}, /* PCMIF SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA3_4CH), 4}, /* FPGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA4_12CH), 12}, /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA1_4CH), 4}, /* UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA2_4CH), 4}, /* Video SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA3_4CH), 4}, /* Security */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA4_4CH), 4}, /* FPGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_DMA1_8CH), 8}, /* UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_DMA2_4CH), 4}, /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static SIMPLE_DEV_PM_OPS(pch_dma_pm_ops, pch_dma_suspend, pch_dma_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static struct pci_driver pch_dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .id_table = pch_dma_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .probe = pch_dma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .remove = pch_dma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .driver.pm = &pch_dma_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) module_pci_driver(pch_dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) MODULE_DESCRIPTION("Intel EG20T PCH / LAPIS Semicon ML7213/ML7223/ML7831 IOH "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) "DMA controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) MODULE_AUTHOR("Yong Wang <yong.y.wang@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) MODULE_DEVICE_TABLE(pci, pch_dma_id_table);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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