^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <dt-bindings/dma/nbpfaxi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NBPF_REG_CHAN_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NBPF_REG_CHAN_SIZE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Channel Current Transaction Byte register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NBPF_CHAN_CUR_TR_BYTE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Channel Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NBPF_CHAN_STAT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NBPF_CHAN_STAT_EN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NBPF_CHAN_STAT_TACT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NBPF_CHAN_STAT_ERR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NBPF_CHAN_STAT_END 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NBPF_CHAN_STAT_TC 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NBPF_CHAN_STAT_DER 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Channel Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NBPF_CHAN_CTRL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NBPF_CHAN_CTRL_SETEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NBPF_CHAN_CTRL_CLREN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NBPF_CHAN_CTRL_STG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NBPF_CHAN_CTRL_SWRST 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NBPF_CHAN_CTRL_CLRRQ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NBPF_CHAN_CTRL_CLREND 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NBPF_CHAN_CTRL_CLRTC 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NBPF_CHAN_CTRL_SETSUS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NBPF_CHAN_CTRL_CLRSUS 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Channel Configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NBPF_CHAN_CFG 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NBPF_CHAN_CFG_SEL 7 /* terminal SELect: 0..7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define NBPF_CHAN_CFG_REQD 8 /* REQuest Direction: DMAREQ is 0: input, 1: output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define NBPF_CHAN_CFG_LOEN 0x10 /* LOw ENable: low DMA request line is: 0: inactive, 1: active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define NBPF_CHAN_CFG_HIEN 0x20 /* HIgh ENable: high DMA request line is: 0: inactive, 1: active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define NBPF_CHAN_CFG_LVL 0x40 /* LeVeL: DMA request line is sensed as 0: edge, 1: level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define NBPF_CHAN_CFG_AM 0x700 /* ACK Mode: 0: Pulse mode, 1: Level mode, b'1x: Bus Cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define NBPF_CHAN_CFG_SDS 0xf000 /* Source Data Size: 0: 8 bits,... , 7: 1024 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define NBPF_CHAN_CFG_DDS 0xf0000 /* Destination Data Size: as above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define NBPF_CHAN_CFG_SAD 0x100000 /* Source ADdress counting: 0: increment, 1: fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define NBPF_CHAN_CFG_DAD 0x200000 /* Destination ADdress counting: 0: increment, 1: fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define NBPF_CHAN_CFG_TM 0x400000 /* Transfer Mode: 0: single, 1: block TM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define NBPF_CHAN_CFG_DEM 0x1000000 /* DMAEND interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define NBPF_CHAN_CFG_TCM 0x2000000 /* DMATCO interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define NBPF_CHAN_CFG_SBE 0x8000000 /* Sweep Buffer Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define NBPF_CHAN_CFG_RSEL 0x10000000 /* RM: Register Set sELect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define NBPF_CHAN_CFG_RSW 0x20000000 /* RM: Register Select sWitch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define NBPF_CHAN_CFG_REN 0x40000000 /* RM: Register Set Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define NBPF_CHAN_CFG_DMS 0x80000000 /* 0: register mode (RM), 1: link mode (LM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define NBPF_CHAN_NXLA 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define NBPF_CHAN_CRLA 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Link Header field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define NBPF_HEADER_LV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define NBPF_HEADER_LE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NBPF_HEADER_WBD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define NBPF_HEADER_DIM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define NBPF_CTRL 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define NBPF_CTRL_PR 1 /* 0: fixed priority, 1: round robin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define NBPF_CTRL_LVINT 2 /* DMAEND and DMAERR signalling: 0: pulse, 1: level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define NBPF_DSTAT_ER 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define NBPF_DSTAT_END 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define NBPF_DMA_BUSWIDTHS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct nbpf_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * We've got 3 types of objects, used to describe DMA transfers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * 1. high-level descriptor, containing a struct dma_async_tx_descriptor object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * in it, used to communicate with the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * 2. hardware DMA link descriptors, that we pass to DMAC for DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * queuing, these must be DMAable, using either the streaming DMA API or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * allocated from coherent memory - one per SG segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * 3. one per SG segment descriptors, used to manage HW link descriptors from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * (2). They do not have to be DMAable. They can either be (a) allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * together with link descriptors as mixed (DMA / CPU) objects, or (b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * separately. Even if allocated separately it would be best to link them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * to link descriptors once during channel resource allocation and always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * use them as a single object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Therefore for both cases (a) and (b) at run-time objects (2) and (3) shall be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * treated as a single SG segment descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct nbpf_link_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 transaction_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 extension;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct nbpf_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct nbpf_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct nbpf_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct nbpf_link_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct nbpf_link_reg *hwdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dma_addr_t hwdesc_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct nbpf_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * struct nbpf_desc - DMA transfer descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @async_tx: dmaengine object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @user_wait: waiting for a user ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @length: total transfer length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @chan: associated DMAC channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @sg: list of hardware descriptors, represented by struct nbpf_link_desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @node: member in channel descriptor lists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct nbpf_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct dma_async_tx_descriptor async_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bool user_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) size_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct nbpf_channel *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct list_head sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Take a wild guess: allocate 4 segments per descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define NBPF_SEGMENTS_PER_DESC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define NBPF_DESCS_PER_PAGE ((PAGE_SIZE - sizeof(struct list_head)) / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) (sizeof(struct nbpf_desc) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) NBPF_SEGMENTS_PER_DESC * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) (sizeof(struct nbpf_link_desc) + sizeof(struct nbpf_link_reg))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define NBPF_SEGMENTS_PER_PAGE (NBPF_SEGMENTS_PER_DESC * NBPF_DESCS_PER_PAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct nbpf_desc_page {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct nbpf_desc desc[NBPF_DESCS_PER_PAGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct nbpf_link_desc ldesc[NBPF_SEGMENTS_PER_PAGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct nbpf_link_reg hwdesc[NBPF_SEGMENTS_PER_PAGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * struct nbpf_channel - one DMAC channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @dma_chan: standard dmaengine channel object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @tasklet: channel specific tasklet used for callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @base: register address base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @nbpf: DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @name: IRQ name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @irq: IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @slave_src_addr: source address for slave DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @slave_src_width: source slave data size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @slave_src_burst: maximum source slave burst size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @slave_dst_addr: destination address for slave DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @slave_dst_width: destination slave data size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @slave_dst_burst: maximum destination slave burst size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @terminal: DMA terminal, assigned to this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @dmarq_cfg: DMA request line configuration - high / low, edge / level for NBPF_CHAN_CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @flags: configuration flags from DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @lock: protect descriptor lists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @free_links: list of free link descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @free: list of free descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @queued: list of queued descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @active: list of descriptors, scheduled for processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @done: list of completed descriptors, waiting post-processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @desc_page: list of additionally allocated descriptor pages - if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @running: linked descriptor of running transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @paused: are translations on this channel paused?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct nbpf_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct dma_chan dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct tasklet_struct tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct nbpf_device *nbpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) char name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dma_addr_t slave_src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) size_t slave_src_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) size_t slave_src_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dma_addr_t slave_dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) size_t slave_dst_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) size_t slave_dst_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int terminal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 dmarq_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct list_head free_links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct list_head free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct list_head queued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct list_head active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct list_head done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct list_head desc_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct nbpf_desc *running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) bool paused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct nbpf_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct dma_device dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 max_burst_mem_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 max_burst_mem_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) const struct nbpf_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned int eirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct nbpf_channel chan[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) enum nbpf_model {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) NBPF1B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) NBPF1B8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) NBPF1B16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) NBPF4B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) NBPF4B8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) NBPF4B16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) NBPF8B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) NBPF8B8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) NBPF8B16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static struct nbpf_config nbpf_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [NBPF1B4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .buffer_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [NBPF1B8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .buffer_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [NBPF1B16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .buffer_size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [NBPF4B4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .buffer_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [NBPF4B8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .buffer_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [NBPF4B16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .buffer_size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [NBPF8B4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .buffer_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [NBPF8B8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .buffer_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [NBPF8B16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .buffer_size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define nbpf_to_chan(d) container_of(d, struct nbpf_channel, dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * dmaengine drivers seem to have a lot in common and instead of sharing more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * code, they reimplement those common algorithms independently. In this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * we try to separate the hardware-specific part from the (largely) generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * part. This improves code readability and makes it possible in the future to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * reuse the generic code in form of a helper library. That generic code should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * be suitable for various DMA controllers, using transfer descriptors in RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * and pushing one SG list at a time to the DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Hardware-specific part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static inline u32 nbpf_chan_read(struct nbpf_channel *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 data = ioread32(chan->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_dbg(chan->dma_chan.device->dev, "%s(0x%p + 0x%x) = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) __func__, chan->base, offset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static inline void nbpf_chan_write(struct nbpf_channel *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int offset, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) iowrite32(data, chan->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev_dbg(chan->dma_chan.device->dev, "%s(0x%p + 0x%x) = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) __func__, chan->base, offset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static inline u32 nbpf_read(struct nbpf_device *nbpf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 data = ioread32(nbpf->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev_dbg(nbpf->dma_dev.dev, "%s(0x%p + 0x%x) = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) __func__, nbpf->base, offset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static inline void nbpf_write(struct nbpf_device *nbpf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int offset, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) iowrite32(data, nbpf->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_dbg(nbpf->dma_dev.dev, "%s(0x%p + 0x%x) = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) __func__, nbpf->base, offset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void nbpf_chan_halt(struct nbpf_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static bool nbpf_status_get(struct nbpf_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 status = nbpf_read(chan->nbpf, NBPF_DSTAT_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return status & BIT(chan - chan->nbpf->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void nbpf_status_ack(struct nbpf_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static u32 nbpf_error_get(struct nbpf_device *nbpf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return nbpf_read(nbpf, NBPF_DSTAT_ER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static struct nbpf_channel *nbpf_error_get_channel(struct nbpf_device *nbpf, u32 error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return nbpf->chan + __ffs(error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void nbpf_error_clear(struct nbpf_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Stop the channel, make sure DMA has been aborted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) nbpf_chan_halt(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) for (i = 1000; i; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) status = nbpf_chan_read(chan, NBPF_CHAN_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (!(status & NBPF_CHAN_STAT_TACT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(chan->dma_chan.device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "%s(): abort timeout, channel status 0x%x\n", __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int nbpf_start(struct nbpf_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct nbpf_channel *chan = desc->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct nbpf_link_desc *ldesc = list_first_entry(&desc->sg, struct nbpf_link_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) nbpf_chan_write(chan, NBPF_CHAN_NXLA, (u32)ldesc->hwdesc_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SETEN | NBPF_CHAN_CTRL_CLRSUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) chan->paused = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Software trigger MEMCPY - only MEMCPY uses the block mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (ldesc->hwdesc->config & NBPF_CHAN_CFG_TM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_STG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_dbg(chan->nbpf->dma_dev.dev, "%s(): next 0x%x, cur 0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) nbpf_chan_read(chan, NBPF_CHAN_NXLA), nbpf_chan_read(chan, NBPF_CHAN_CRLA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void nbpf_chan_prepare(struct nbpf_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) chan->dmarq_cfg = (chan->flags & NBPF_SLAVE_RQ_HIGH ? NBPF_CHAN_CFG_HIEN : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) (chan->flags & NBPF_SLAVE_RQ_LOW ? NBPF_CHAN_CFG_LOEN : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) (chan->flags & NBPF_SLAVE_RQ_LEVEL ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) NBPF_CHAN_CFG_LVL | (NBPF_CHAN_CFG_AM & 0x200) : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) chan->terminal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static void nbpf_chan_prepare_default(struct nbpf_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Don't output DMAACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) chan->dmarq_cfg = NBPF_CHAN_CFG_AM & 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) chan->terminal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) chan->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static void nbpf_chan_configure(struct nbpf_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * We assume, that only the link mode and DMA request line configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * have to be set in the configuration register manually. Dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * per-transfer configuration will be loaded from transfer descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) nbpf_chan_write(chan, NBPF_CHAN_CFG, NBPF_CHAN_CFG_DMS | chan->dmarq_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static u32 nbpf_xfer_ds(struct nbpf_device *nbpf, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) enum dma_transfer_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int max_burst = nbpf->config->buffer_size * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (nbpf->max_burst_mem_read || nbpf->max_burst_mem_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case DMA_MEM_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) max_burst = min_not_zero(nbpf->max_burst_mem_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) nbpf->max_burst_mem_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (nbpf->max_burst_mem_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) max_burst = nbpf->max_burst_mem_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (nbpf->max_burst_mem_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) max_burst = nbpf->max_burst_mem_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case DMA_DEV_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Maximum supported bursts depend on the buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return min_t(int, __ffs(size), ilog2(max_burst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static size_t nbpf_xfer_size(struct nbpf_device *nbpf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) enum dma_slave_buswidth width, u32 burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (!burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) burst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case DMA_SLAVE_BUSWIDTH_8_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) size = 8 * burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) size = 4 * burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) size = 2 * burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pr_warn("%s(): invalid bus width %u\n", __func__, width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) size = burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return nbpf_xfer_ds(nbpf, size, DMA_TRANS_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * We need a way to recognise slaves, whose data is sent "raw" over the bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * i.e. it isn't known in advance how many bytes will be received. Therefore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * the slave driver has to provide a "large enough" buffer and either read the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * buffer, when it is full, or detect, that some data has arrived, then wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * a timeout, if no more data arrives - receive what's already there. We want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * handle such slaves in a special way to allow an optimised mode for other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * users, for whom the amount of data is known in advance. So far there's no way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * to recognise such slaves. We use a data-width check to distinguish between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * the SD host and the PL011 UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int nbpf_prep_one(struct nbpf_link_desc *ldesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dma_addr_t src, dma_addr_t dst, size_t size, bool last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct nbpf_link_reg *hwdesc = ldesc->hwdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct nbpf_desc *desc = ldesc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct nbpf_channel *chan = desc->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct device *dev = chan->dma_chan.device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) size_t mem_xfer, slave_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) bool can_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) hwdesc->header = NBPF_HEADER_WBD | NBPF_HEADER_LV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) (last ? NBPF_HEADER_LE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) hwdesc->src_addr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) hwdesc->dst_addr = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) hwdesc->transaction_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * set config: SAD, DAD, DDS, SDS, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Note on transfer sizes: the DMAC can perform unaligned DMA transfers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * but it is important to have transaction size a multiple of both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * receiver and transmitter transfer sizes. It is also possible to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * different RAM and device transfer sizes, and it does work well with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * some devices, e.g. with V08R07S01E SD host controllers, which can use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * 128 byte transfers. But this doesn't work with other devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * especially when the transaction size is unknown. This is the case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * e.g. with serial drivers like amba-pl011.c. For reception it sets up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * the transaction size of 4K and if fewer bytes are received, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * pauses DMA and reads out data received via DMA as well as those left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * in the Rx FIFO. For this to work with the RAM side using burst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * transfers we enable the SBE bit and terminate the transfer in our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * .device_pause handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mem_xfer = nbpf_xfer_ds(chan->nbpf, size, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) can_burst = chan->slave_src_width >= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) slave_xfer = min(mem_xfer, can_burst ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) chan->slave_src_burst : chan->slave_src_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * Is the slave narrower than 64 bits, i.e. isn't using the full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * bus width and cannot use bursts?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (mem_xfer > chan->slave_src_burst && !can_burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mem_xfer = chan->slave_src_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Device-to-RAM DMA is unreliable without REQD set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) hwdesc->config = NBPF_CHAN_CFG_SAD | (NBPF_CHAN_CFG_DDS & (mem_xfer << 16)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) (NBPF_CHAN_CFG_SDS & (slave_xfer << 12)) | NBPF_CHAN_CFG_REQD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) NBPF_CHAN_CFG_SBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) slave_xfer = min(mem_xfer, chan->slave_dst_width >= 3 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) chan->slave_dst_burst : chan->slave_dst_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) hwdesc->config = NBPF_CHAN_CFG_DAD | (NBPF_CHAN_CFG_SDS & (mem_xfer << 12)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) (NBPF_CHAN_CFG_DDS & (slave_xfer << 16)) | NBPF_CHAN_CFG_REQD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case DMA_MEM_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) hwdesc->config = NBPF_CHAN_CFG_TCM | NBPF_CHAN_CFG_TM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) (NBPF_CHAN_CFG_SDS & (mem_xfer << 12)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) (NBPF_CHAN_CFG_DDS & (mem_xfer << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) hwdesc->config |= chan->dmarq_cfg | (last ? 0 : NBPF_CHAN_CFG_DEM) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) NBPF_CHAN_CFG_DMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_dbg(dev, "%s(): desc @ %pad: hdr 0x%x, cfg 0x%x, %zu @ %pad -> %pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) __func__, &ldesc->hwdesc_dma_addr, hwdesc->header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) hwdesc->config, size, &src, &dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dma_sync_single_for_device(dev, ldesc->hwdesc_dma_addr, sizeof(*hwdesc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static size_t nbpf_bytes_left(struct nbpf_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return nbpf_chan_read(chan, NBPF_CHAN_CUR_TR_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static void nbpf_configure(struct nbpf_device *nbpf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) nbpf_write(nbpf, NBPF_CTRL, NBPF_CTRL_LVINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Generic part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* DMA ENGINE functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static void nbpf_issue_pending(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct nbpf_channel *chan = nbpf_to_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (list_empty(&chan->queued))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) list_splice_tail_init(&chan->queued, &chan->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (!chan->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct nbpf_desc *desc = list_first_entry(&chan->active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct nbpf_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!nbpf_start(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) chan->running = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static enum dma_status nbpf_tx_status(struct dma_chan *dchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dma_cookie_t cookie, struct dma_tx_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct nbpf_channel *chan = nbpf_to_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) enum dma_status status = dma_cookie_status(dchan, cookie, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dma_cookie_t running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) running = chan->running ? chan->running->async_tx.cookie : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (cookie == running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) state->residue = nbpf_bytes_left(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev_dbg(dchan->device->dev, "%s(): residue %u\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) state->residue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) } else if (status == DMA_IN_PROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct nbpf_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) bool found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) list_for_each_entry(desc, &chan->active, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (desc->async_tx.cookie == cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (!found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) list_for_each_entry(desc, &chan->queued, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (desc->async_tx.cookie == cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) state->residue = found ? desc->length : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (chan->paused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) status = DMA_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static dma_cookie_t nbpf_tx_submit(struct dma_async_tx_descriptor *tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct nbpf_desc *desc = container_of(tx, struct nbpf_desc, async_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct nbpf_channel *chan = desc->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) cookie = dma_cookie_assign(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) list_add_tail(&desc->node, &chan->queued);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev_dbg(chan->dma_chan.device->dev, "Entry %s(%d)\n", __func__, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static int nbpf_desc_page_alloc(struct nbpf_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct dma_chan *dchan = &chan->dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct nbpf_desc_page *dpage = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct nbpf_link_desc *ldesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct nbpf_link_reg *hwdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct nbpf_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) LIST_HEAD(lhead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct device *dev = dchan->device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (!dpage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_dbg(dev, "%s(): alloc %lu descriptors, %lu segments, total alloc %zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) __func__, NBPF_DESCS_PER_PAGE, NBPF_SEGMENTS_PER_PAGE, sizeof(*dpage));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) for (i = 0, ldesc = dpage->ldesc, hwdesc = dpage->hwdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) i < ARRAY_SIZE(dpage->ldesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) i++, ldesc++, hwdesc++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ldesc->hwdesc = hwdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) list_add_tail(&ldesc->node, &lhead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ldesc->hwdesc_dma_addr = dma_map_single(dchan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) hwdesc, sizeof(*hwdesc), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_dbg(dev, "%s(): mapped 0x%p to %pad\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) hwdesc, &ldesc->hwdesc_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) for (i = 0, desc = dpage->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) i < ARRAY_SIZE(dpage->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) i++, desc++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dma_async_tx_descriptor_init(&desc->async_tx, dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) desc->async_tx.tx_submit = nbpf_tx_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) desc->chan = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) INIT_LIST_HEAD(&desc->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) list_add_tail(&desc->node, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * This function cannot be called from interrupt context, so, no need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * save flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) spin_lock_irq(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) list_splice_tail(&lhead, &chan->free_links);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) list_splice_tail(&head, &chan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) list_add(&dpage->node, &chan->desc_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) spin_unlock_irq(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return ARRAY_SIZE(dpage->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static void nbpf_desc_put(struct nbpf_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct nbpf_channel *chan = desc->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct nbpf_link_desc *ldesc, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) list_for_each_entry_safe(ldesc, tmp, &desc->sg, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) list_move(&ldesc->node, &chan->free_links);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) list_add(&desc->node, &chan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static void nbpf_scan_acked(struct nbpf_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct nbpf_desc *desc, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) list_for_each_entry_safe(desc, tmp, &chan->done, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (async_tx_test_ack(&desc->async_tx) && desc->user_wait) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) list_move(&desc->node, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) desc->user_wait = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) list_for_each_entry_safe(desc, tmp, &head, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) list_del(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) nbpf_desc_put(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * We have to allocate descriptors with the channel lock dropped. This means,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * before we re-acquire the lock buffers can be taken already, so we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * re-check after re-acquiring the lock and possibly retry, if buffers are gone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static struct nbpf_desc *nbpf_desc_get(struct nbpf_channel *chan, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct nbpf_desc *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct nbpf_link_desc *ldesc, *prev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) nbpf_scan_acked(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) spin_lock_irq(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) int i = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (list_empty(&chan->free)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* No more free descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) spin_unlock_irq(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ret = nbpf_desc_page_alloc(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) spin_lock_irq(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) desc = list_first_entry(&chan->free, struct nbpf_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) list_del(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (list_empty(&chan->free_links)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* No more free link descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) spin_unlock_irq(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = nbpf_desc_page_alloc(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) nbpf_desc_put(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) spin_lock_irq(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ldesc = list_first_entry(&chan->free_links,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct nbpf_link_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ldesc->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (prev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) prev->hwdesc->next = (u32)ldesc->hwdesc_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) prev = ldesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) list_move_tail(&ldesc->node, &desc->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) } while (i < len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) } while (!desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) prev->hwdesc->next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) spin_unlock_irq(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static void nbpf_chan_idle(struct nbpf_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct nbpf_desc *desc, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) spin_lock_irqsave(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) list_splice_init(&chan->done, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) list_splice_init(&chan->active, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) list_splice_init(&chan->queued, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) chan->running = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) spin_unlock_irqrestore(&chan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) list_for_each_entry_safe(desc, tmp, &head, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dev_dbg(chan->nbpf->dma_dev.dev, "%s(): force-free desc %p cookie %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) __func__, desc, desc->async_tx.cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) list_del(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) nbpf_desc_put(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int nbpf_pause(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct nbpf_channel *chan = nbpf_to_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) chan->paused = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SETSUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* See comment in nbpf_prep_one() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static int nbpf_terminate_all(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct nbpf_channel *chan = nbpf_to_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev_dbg(dchan->device->dev, "Terminating\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) nbpf_chan_halt(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) nbpf_chan_idle(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static int nbpf_config(struct dma_chan *dchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct dma_slave_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct nbpf_channel *chan = nbpf_to_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * We could check config->slave_id to match chan->terminal here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * but with DT they would be coming from the same source, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * such a check would be superflous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) chan->slave_dst_addr = config->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) chan->slave_dst_width = nbpf_xfer_size(chan->nbpf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) config->dst_addr_width, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) chan->slave_dst_burst = nbpf_xfer_size(chan->nbpf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) config->dst_addr_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) config->dst_maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) chan->slave_src_addr = config->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) chan->slave_src_width = nbpf_xfer_size(chan->nbpf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) config->src_addr_width, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) chan->slave_src_burst = nbpf_xfer_size(chan->nbpf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) config->src_addr_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) config->src_maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static struct dma_async_tx_descriptor *nbpf_prep_sg(struct nbpf_channel *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct scatterlist *src_sg, struct scatterlist *dst_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) size_t len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct nbpf_link_desc *ldesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct scatterlist *mem_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct nbpf_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) bool inc_src, inc_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) size_t data_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) mem_sg = dst_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) inc_src = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) inc_dst = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) mem_sg = src_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) inc_src = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) inc_dst = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) case DMA_MEM_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) mem_sg = src_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) inc_src = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) inc_dst = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) desc = nbpf_desc_get(chan, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) desc->async_tx.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) desc->async_tx.cookie = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) desc->user_wait = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * This is a private descriptor list, and we own the descriptor. No need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * to lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) list_for_each_entry(ldesc, &desc->sg, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) int ret = nbpf_prep_one(ldesc, direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) sg_dma_address(src_sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) sg_dma_address(dst_sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) sg_dma_len(mem_sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) i == len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) nbpf_desc_put(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) data_len += sg_dma_len(mem_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (inc_src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) src_sg = sg_next(src_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (inc_dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) dst_sg = sg_next(dst_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) mem_sg = direction == DMA_DEV_TO_MEM ? dst_sg : src_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) desc->length = data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* The user has to return the descriptor to us ASAP via .tx_submit() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return &desc->async_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static struct dma_async_tx_descriptor *nbpf_prep_memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct nbpf_channel *chan = nbpf_to_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct scatterlist dst_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct scatterlist src_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) sg_init_table(&dst_sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) sg_init_table(&src_sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) sg_dma_address(&dst_sg) = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) sg_dma_address(&src_sg) = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) sg_dma_len(&dst_sg) = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) sg_dma_len(&src_sg) = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dev_dbg(dchan->device->dev, "%s(): %zu @ %pad -> %pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) __func__, len, &src, &dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return nbpf_prep_sg(chan, &src_sg, &dst_sg, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) DMA_MEM_TO_MEM, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static struct dma_async_tx_descriptor *nbpf_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) enum dma_transfer_direction direction, unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct nbpf_channel *chan = nbpf_to_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct scatterlist slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) sg_init_table(&slave_sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case DMA_MEM_TO_DEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) sg_dma_address(&slave_sg) = chan->slave_dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return nbpf_prep_sg(chan, sgl, &slave_sg, sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) direction, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case DMA_DEV_TO_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) sg_dma_address(&slave_sg) = chan->slave_src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return nbpf_prep_sg(chan, &slave_sg, sgl, sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) direction, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static int nbpf_alloc_chan_resources(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct nbpf_channel *chan = nbpf_to_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) INIT_LIST_HEAD(&chan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) INIT_LIST_HEAD(&chan->free_links);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) INIT_LIST_HEAD(&chan->queued);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) INIT_LIST_HEAD(&chan->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) INIT_LIST_HEAD(&chan->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = nbpf_desc_page_alloc(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev_dbg(dchan->device->dev, "Entry %s(): terminal %u\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) chan->terminal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) nbpf_chan_configure(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static void nbpf_free_chan_resources(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct nbpf_channel *chan = nbpf_to_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct nbpf_desc_page *dpage, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) nbpf_chan_halt(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) nbpf_chan_idle(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* Clean up for if a channel is re-used for MEMCPY after slave DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) nbpf_chan_prepare_default(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) list_for_each_entry_safe(dpage, tmp, &chan->desc_page, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct nbpf_link_desc *ldesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) list_del(&dpage->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) for (i = 0, ldesc = dpage->ldesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) i < ARRAY_SIZE(dpage->ldesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) i++, ldesc++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dma_unmap_single(dchan->device->dev, ldesc->hwdesc_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) sizeof(*ldesc->hwdesc), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) free_page((unsigned long)dpage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static struct dma_chan *nbpf_of_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct nbpf_device *nbpf = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct dma_chan *dchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct nbpf_channel *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (dma_spec->args_count != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) dchan = dma_get_any_slave_channel(&nbpf->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (!dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) dev_dbg(dchan->device->dev, "Entry %s(%pOFn)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) dma_spec->np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) chan = nbpf_to_chan(dchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) chan->terminal = dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) chan->flags = dma_spec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) nbpf_chan_prepare(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) nbpf_chan_configure(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return dchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static void nbpf_chan_tasklet(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct nbpf_channel *chan = from_tasklet(chan, t, tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct nbpf_desc *desc, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct dmaengine_desc_callback cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) while (!list_empty(&chan->done)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) bool found = false, must_put, recycling = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) spin_lock_irq(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) list_for_each_entry_safe(desc, tmp, &chan->done, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (!desc->user_wait) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* Newly completed descriptor, have to process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) } else if (async_tx_test_ack(&desc->async_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * This descriptor was waiting for a user ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * it can be recycled now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) list_del(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) spin_unlock_irq(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) nbpf_desc_put(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) recycling = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (recycling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* This can happen if TERMINATE_ALL has been called */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) spin_unlock_irq(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dma_cookie_complete(&desc->async_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * With released lock we cannot dereference desc, maybe it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * still on the "done" list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (async_tx_test_ack(&desc->async_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) list_del(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) must_put = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) desc->user_wait = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) must_put = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) dmaengine_desc_get_callback(&desc->async_tx, &cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /* ack and callback completed descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) spin_unlock_irq(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) dmaengine_desc_callback_invoke(&cb, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (must_put)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) nbpf_desc_put(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static irqreturn_t nbpf_chan_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct nbpf_channel *chan = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) bool done = nbpf_status_get(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct nbpf_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) irqreturn_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) bool bh = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (!done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) nbpf_status_ack(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) dev_dbg(&chan->dma_chan.dev->device, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) spin_lock(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) desc = chan->running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (WARN_ON(!desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) bh = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) list_move_tail(&desc->node, &chan->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) chan->running = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (!list_empty(&chan->active)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) desc = list_first_entry(&chan->active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct nbpf_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (!nbpf_start(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) chan->running = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) spin_unlock(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (bh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) tasklet_schedule(&chan->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static irqreturn_t nbpf_err_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct nbpf_device *nbpf = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) u32 error = nbpf_error_get(nbpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) dev_warn(nbpf->dma_dev.dev, "DMA error IRQ %u\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (!error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct nbpf_channel *chan = nbpf_error_get_channel(nbpf, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /* On error: abort all queued transfers, no callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) nbpf_error_clear(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) nbpf_chan_idle(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) error = nbpf_error_get(nbpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) } while (error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static int nbpf_chan_probe(struct nbpf_device *nbpf, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct dma_device *dma_dev = &nbpf->dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct nbpf_channel *chan = nbpf->chan + n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) chan->nbpf = nbpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) chan->base = nbpf->base + NBPF_REG_CHAN_OFFSET + NBPF_REG_CHAN_SIZE * n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) INIT_LIST_HEAD(&chan->desc_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) spin_lock_init(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) chan->dma_chan.device = dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dma_cookie_init(&chan->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) nbpf_chan_prepare_default(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_dbg(dma_dev->dev, "%s(): channel %d: -> %p\n", __func__, n, chan->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) snprintf(chan->name, sizeof(chan->name), "nbpf %d", n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) tasklet_setup(&chan->tasklet, nbpf_chan_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ret = devm_request_irq(dma_dev->dev, chan->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) nbpf_chan_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) chan->name, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* Add the channel to DMA device channel list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) list_add_tail(&chan->dma_chan.device_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) &dma_dev->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static const struct of_device_id nbpf_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {.compatible = "renesas,nbpfaxi64dmac1b4", .data = &nbpf_cfg[NBPF1B4]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {.compatible = "renesas,nbpfaxi64dmac1b8", .data = &nbpf_cfg[NBPF1B8]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {.compatible = "renesas,nbpfaxi64dmac1b16", .data = &nbpf_cfg[NBPF1B16]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {.compatible = "renesas,nbpfaxi64dmac4b4", .data = &nbpf_cfg[NBPF4B4]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {.compatible = "renesas,nbpfaxi64dmac4b8", .data = &nbpf_cfg[NBPF4B8]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {.compatible = "renesas,nbpfaxi64dmac4b16", .data = &nbpf_cfg[NBPF4B16]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {.compatible = "renesas,nbpfaxi64dmac8b4", .data = &nbpf_cfg[NBPF8B4]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {.compatible = "renesas,nbpfaxi64dmac8b8", .data = &nbpf_cfg[NBPF8B8]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {.compatible = "renesas,nbpfaxi64dmac8b16", .data = &nbpf_cfg[NBPF8B16]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) MODULE_DEVICE_TABLE(of, nbpf_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static int nbpf_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct nbpf_device *nbpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct dma_device *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) struct resource *iomem, *irq_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) const struct nbpf_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) int ret, irq, eirq, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) int irqbuf[9] /* maximum 8 channels + error IRQ */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) unsigned int irqs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) BUILD_BUG_ON(sizeof(struct nbpf_desc_page) > PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /* DT only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) cfg = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) num_channels = cfg->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) nbpf = devm_kzalloc(dev, struct_size(nbpf, chan, num_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (!nbpf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) dma_dev = &nbpf->dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dma_dev->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) nbpf->base = devm_ioremap_resource(dev, iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (IS_ERR(nbpf->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return PTR_ERR(nbpf->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) nbpf->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (IS_ERR(nbpf->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return PTR_ERR(nbpf->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) of_property_read_u32(np, "max-burst-mem-read",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) &nbpf->max_burst_mem_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) of_property_read_u32(np, "max-burst-mem-write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) &nbpf->max_burst_mem_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) nbpf->config = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) for (i = 0; irqs < ARRAY_SIZE(irqbuf); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (!irq_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) for (irq = irq_res->start; irq <= irq_res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) irq++, irqs++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) irqbuf[irqs] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * 3 IRQ resource schemes are supported:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * 1. 1 shared IRQ for error and all channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * 2. 2 IRQs: one for error and one shared for all channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) * 3. 1 IRQ for error and an own IRQ for each channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (irqs != 1 && irqs != 2 && irqs != num_channels + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (irqs == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) eirq = irqbuf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) for (i = 0; i <= num_channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) nbpf->chan[i].irq = irqbuf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) eirq = platform_get_irq_byname(pdev, "error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (eirq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return eirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (irqs == num_channels + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct nbpf_channel *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) for (i = 0, chan = nbpf->chan; i <= num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) i++, chan++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* Skip the error IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (irqbuf[i] == eirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) chan->irq = irqbuf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (chan != nbpf->chan + num_channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* 2 IRQs and more than one channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (irqbuf[0] == eirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) irq = irqbuf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) irq = irqbuf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) for (i = 0; i <= num_channels; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) nbpf->chan[i].irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ret = devm_request_irq(dev, eirq, nbpf_err_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) IRQF_SHARED, "dma error", nbpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) nbpf->eirq = eirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) INIT_LIST_HEAD(&dma_dev->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /* Create DMA Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) for (i = 0; i < num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) ret = nbpf_chan_probe(nbpf, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* Common and MEMCPY operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) dma_dev->device_alloc_chan_resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) = nbpf_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) dma_dev->device_free_chan_resources = nbpf_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) dma_dev->device_prep_dma_memcpy = nbpf_prep_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) dma_dev->device_tx_status = nbpf_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) dma_dev->device_issue_pending = nbpf_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * If we drop support for unaligned MEMCPY buffer addresses and / or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * lengths by setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * dma_dev->copy_align = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * then we can set transfer length to 4 bytes in nbpf_prep_one() for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * DMA_MEM_TO_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* Compulsory for DMA_SLAVE fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) dma_dev->device_prep_slave_sg = nbpf_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) dma_dev->device_config = nbpf_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) dma_dev->device_pause = nbpf_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) dma_dev->device_terminate_all = nbpf_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) dma_dev->src_addr_widths = NBPF_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) dma_dev->dst_addr_widths = NBPF_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) dma_dev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) platform_set_drvdata(pdev, nbpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) ret = clk_prepare_enable(nbpf->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) nbpf_configure(nbpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) ret = dma_async_device_register(dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) goto e_clk_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) ret = of_dma_controller_register(np, nbpf_of_xlate, nbpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) goto e_dma_dev_unreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) e_dma_dev_unreg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) dma_async_device_unregister(dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) e_clk_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) clk_disable_unprepare(nbpf->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static int nbpf_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) struct nbpf_device *nbpf = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) devm_free_irq(&pdev->dev, nbpf->eirq, nbpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) for (i = 0; i < nbpf->config->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) struct nbpf_channel *chan = nbpf->chan + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) devm_free_irq(&pdev->dev, chan->irq, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) tasklet_kill(&chan->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) of_dma_controller_free(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) dma_async_device_unregister(&nbpf->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) clk_disable_unprepare(nbpf->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) static const struct platform_device_id nbpf_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) {"nbpfaxi64dmac1b4", (kernel_ulong_t)&nbpf_cfg[NBPF1B4]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) {"nbpfaxi64dmac1b8", (kernel_ulong_t)&nbpf_cfg[NBPF1B8]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) {"nbpfaxi64dmac1b16", (kernel_ulong_t)&nbpf_cfg[NBPF1B16]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) {"nbpfaxi64dmac4b4", (kernel_ulong_t)&nbpf_cfg[NBPF4B4]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {"nbpfaxi64dmac4b8", (kernel_ulong_t)&nbpf_cfg[NBPF4B8]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) {"nbpfaxi64dmac4b16", (kernel_ulong_t)&nbpf_cfg[NBPF4B16]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) {"nbpfaxi64dmac8b4", (kernel_ulong_t)&nbpf_cfg[NBPF8B4]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {"nbpfaxi64dmac8b8", (kernel_ulong_t)&nbpf_cfg[NBPF8B8]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) {"nbpfaxi64dmac8b16", (kernel_ulong_t)&nbpf_cfg[NBPF8B16]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) MODULE_DEVICE_TABLE(platform, nbpf_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static int nbpf_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) struct nbpf_device *nbpf = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) clk_disable_unprepare(nbpf->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static int nbpf_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) struct nbpf_device *nbpf = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return clk_prepare_enable(nbpf->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static const struct dev_pm_ops nbpf_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) SET_RUNTIME_PM_OPS(nbpf_runtime_suspend, nbpf_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static struct platform_driver nbpf_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .name = "dma-nbpf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .of_match_table = nbpf_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .pm = &nbpf_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .id_table = nbpf_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .probe = nbpf_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .remove = nbpf_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) module_platform_driver(nbpf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) MODULE_DESCRIPTION("dmaengine driver for NBPFAXI64* DMACs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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