^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Refer to drivers/dma/imx-sdma.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/semaphore.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/stmp_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/dma/mxs-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * NOTE: The term "PIO" throughout the mxs-dma implementation means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * dma can program the controller registers of peripheral devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HW_APBHX_CTRL0 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BP_APBH_CTRL0_RESET_CHANNEL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HW_APBHX_CTRL1 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HW_APBHX_CTRL2 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HW_APBHX_CHANNEL_CTRL 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * The offset of NXTCMDAR register is different per both dma type and version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * while stride for each channel is all the same 0x70.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HW_APBHX_CHn_NXTCMDAR(d, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HW_APBHX_CHn_SEMA(d, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HW_APBHX_CHn_BAR(d, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x070 : 0x130) + (n) * 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HW_APBX_CHn_DEBUG1(d, n) (0x150 + (n) * 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * ccw bits definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * COMMAND: 0..1 (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * CHAIN: 2 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * IRQ: 3 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * NAND_LOCK: 4 (1) - not implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * NAND_WAIT4READY: 5 (1) - not implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * DEC_SEM: 6 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * WAIT4END: 7 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * HALT_ON_TERMINATE: 8 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * TERMINATE_FLUSH: 9 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * RESERVED: 10..11 (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * PIO_NUM: 12..15 (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BP_CCW_COMMAND 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BM_CCW_COMMAND (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CCW_CHAIN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CCW_IRQ (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CCW_WAIT4RDY (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CCW_DEC_SEM (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CCW_WAIT4END (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CCW_HALT_ON_TERM (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CCW_TERM_FLUSH (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BP_CCW_PIO_NUM 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BM_CCW_PIO_NUM (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MXS_DMA_CMD_NO_XFER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MXS_DMA_CMD_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MXS_DMA_CMD_READ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct mxs_dma_ccw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u16 xfer_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MAX_XFER_BYTES 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 bufaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MXS_PIO_WORDS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 pio_words[MXS_PIO_WORDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CCW_BLOCK_SIZE (4 * PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct mxs_dma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct mxs_dma_engine *mxs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct dma_chan chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct dma_async_tx_descriptor desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct tasklet_struct tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int chan_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct mxs_dma_ccw *ccw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dma_addr_t ccw_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bool reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MXS_DMA_SG_LOOP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MXS_DMA_USE_SEMAPHORE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MXS_DMA_CHANNELS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MXS_DMA_CHANNELS_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) enum mxs_dma_devtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MXS_DMA_APBH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MXS_DMA_APBX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) enum mxs_dma_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) IMX23_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) IMX28_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct mxs_dma_engine {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) enum mxs_dma_id dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) enum mxs_dma_devtype type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct dma_device dma_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct mxs_dma_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) enum mxs_dma_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) enum mxs_dma_devtype type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct mxs_dma_type mxs_dma_types[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .id = IMX23_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .type = MXS_DMA_APBH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .id = IMX23_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .type = MXS_DMA_APBX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .id = IMX28_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .type = MXS_DMA_APBH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .id = IMX28_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .type = MXS_DMA_APBX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct platform_device_id mxs_dma_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .name = "imx23-dma-apbh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .driver_data = (kernel_ulong_t) &mxs_dma_types[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .name = "imx23-dma-apbx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .driver_data = (kernel_ulong_t) &mxs_dma_types[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = "imx28-dma-apbh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .driver_data = (kernel_ulong_t) &mxs_dma_types[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .name = "imx28-dma-apbx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .driver_data = (kernel_ulong_t) &mxs_dma_types[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* end of list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct of_device_id mxs_dma_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_ids[0], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return container_of(chan, struct mxs_dma_chan, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void mxs_dma_reset_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int chan_id = mxs_chan->chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * mxs dma channel resets can cause a channel stall. To recover from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * channel stall, we have to reset the whole DMA engine. To avoid this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * we use cyclic DMA with semaphores, that are enhanced in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * mxs_dma_int_handler. To reset the channel, we can simply stop writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * into the semaphore counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mxs_chan->flags & MXS_DMA_SG_LOOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mxs_chan->reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) } else if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long elapsed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) const unsigned long max_wait = 50000; /* 50ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void __iomem *reg_dbg1 = mxs_dma->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) HW_APBX_CHn_DEBUG1(mxs_dma, chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * On i.MX28 APBX, the DMA channel can stop working if we reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * the channel while it is in READ_FLUSH (0x08) state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * We wait here until we leave the state. Then we trigger the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * reset. Waiting a maximum of 50ms, the kernel shouldn't crash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * because of this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) while ((readl(reg_dbg1) & 0xf) == 0x8 && elapsed < max_wait) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) elapsed += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (elapsed >= max_wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(&mxs_chan->mxs_dma->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "Failed waiting for the DMA channel %d to leave state READ_FLUSH, trying to reset channel in READ_FLUSH state now\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mxs_chan->status = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void mxs_dma_enable_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int chan_id = mxs_chan->chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* set cmd_addr up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) writel(mxs_chan->ccw_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* write 1 to SEMA to kick off the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mxs_chan->flags & MXS_DMA_SG_LOOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* A cyclic DMA consists of at least 2 segments, so initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * the semaphore with 2 so we have enough time to add 1 to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * semaphore if we need to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) writel(2, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) mxs_chan->reset = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void mxs_dma_disable_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mxs_chan->status = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int mxs_dma_pause_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int chan_id = mxs_chan->chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* freeze the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) writel(1 << chan_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writel(1 << chan_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mxs_chan->status = DMA_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int mxs_dma_resume_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int chan_id = mxs_chan->chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* unfreeze the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) writel(1 << chan_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) writel(1 << chan_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mxs_chan->status = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return dma_cookie_assign(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void mxs_dma_tasklet(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct mxs_dma_chan *mxs_chan = from_tasklet(mxs_chan, t, tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dmaengine_desc_get_callback_invoke(&mxs_chan->desc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int mxs_dma_irq_to_chan(struct mxs_dma_engine *mxs_dma, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) for (i = 0; i != mxs_dma->nr_channels; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (mxs_dma->mxs_chans[i].chan_irq == irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct mxs_dma_engine *mxs_dma = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct mxs_dma_chan *mxs_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int chan = mxs_dma_irq_to_chan(mxs_dma, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (chan < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) completed = readl(mxs_dma->base + HW_APBHX_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) completed = (completed >> chan) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writel((1 << chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) err = readl(mxs_dma->base + HW_APBHX_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) err &= (1 << (MXS_DMA_CHANNELS + chan)) | (1 << chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * error status bit is in the upper 16 bits, error irq bit in the lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * 16 bits. We transform it into a simpler error code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * err: 0x00 = no error, 0x01 = TERMINATION, 0x02 = BUS_ERROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) err = (err >> (MXS_DMA_CHANNELS + chan)) + (err >> chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Clear error irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) writel((1 << chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * When both completion and error of termination bits set at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * same time, we do not take it as an error. IOW, it only becomes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * an error we need to handle here in case of either it's a bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * error or a termination error with no completion. 0x01 is termination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * error, so we can subtract err & completed to get the real error case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) err -= err & completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mxs_chan = &mxs_dma->mxs_chans[chan];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_dbg(mxs_dma->dma_device.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) "%s: error in channel %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mxs_chan->status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mxs_dma_reset_chan(&mxs_chan->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } else if (mxs_chan->status != DMA_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (mxs_chan->flags & MXS_DMA_SG_LOOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mxs_chan->status = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) writel(1, mxs_dma->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) HW_APBHX_CHn_SEMA(mxs_dma, chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) mxs_chan->status = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (mxs_chan->status == DMA_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (mxs_chan->reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dma_cookie_complete(&mxs_chan->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* schedule tasklet on this channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) tasklet_schedule(&mxs_chan->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) CCW_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) &mxs_chan->ccw_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!mxs_chan->ccw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0, "mxs-dma", mxs_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = clk_prepare_enable(mxs_dma->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mxs_dma_reset_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* the descriptor is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) async_tx_ack(&mxs_chan->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) free_irq(mxs_chan->chan_irq, mxs_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mxs_chan->ccw, mxs_chan->ccw_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) err_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void mxs_dma_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mxs_dma_disable_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) free_irq(mxs_chan->chan_irq, mxs_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mxs_chan->ccw, mxs_chan->ccw_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) clk_disable_unprepare(mxs_dma->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * How to use the flags for ->device_prep_slave_sg() :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * [1] If there is only one DMA command in the DMA chain, the code should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * ......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * ->device_prep_slave_sg(DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * ......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * [2] If there are two DMA commands in the DMA chain, the code should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * ......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * ->device_prep_slave_sg(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * ......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * ->device_prep_slave_sg(DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * ......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * [3] If there are more than two DMA commands in the DMA chain, the code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * ......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * ->device_prep_slave_sg(0); // First
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * ......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * ->device_prep_slave_sg(DMA_CTRL_ACK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * ......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * ->device_prep_slave_sg(DMA_CTRL_ACK); // Last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * ......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct dma_chan *chan, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned int sg_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct mxs_dma_ccw *ccw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 *pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (mxs_chan->status == DMA_IN_PROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) idx = mxs_chan->desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (sg_len + idx > NUM_CCW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_err(mxs_dma->dma_device.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) "maximum number of sg exceeded: %d > %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sg_len, NUM_CCW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mxs_chan->status = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) mxs_chan->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * If the sg is prepared with append flag set, the sg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * will be appended to the last prepared sg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) BUG_ON(idx < 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ccw = &mxs_chan->ccw[idx - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ccw->bits |= CCW_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ccw->bits &= ~CCW_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ccw->bits &= ~CCW_DEC_SEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (direction == DMA_TRANS_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ccw = &mxs_chan->ccw[idx++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pio = (u32 *) sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) for (j = 0; j < sg_len;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ccw->pio_words[j++] = *pio++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ccw->bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ccw->bits |= CCW_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ccw->bits |= CCW_DEC_SEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (flags & MXS_DMA_CTRL_WAIT4END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ccw->bits |= CCW_WAIT4END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ccw->bits |= CCW_HALT_ON_TERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ccw->bits |= CCW_TERM_FLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ccw->bits |= BF_CCW(sg_len, PIO_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (flags & MXS_DMA_CTRL_WAIT4RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ccw->bits |= CCW_WAIT4RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) for_each_sg(sgl, sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (sg_dma_len(sg) > MAX_XFER_BYTES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) sg_dma_len(sg), MAX_XFER_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ccw = &mxs_chan->ccw[idx++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ccw->bufaddr = sg->dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ccw->xfer_bytes = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ccw->bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ccw->bits |= CCW_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ccw->bits |= CCW_HALT_ON_TERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ccw->bits |= CCW_TERM_FLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (i + 1 == sg_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ccw->bits &= ~CCW_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ccw->bits |= CCW_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ccw->bits |= CCW_DEC_SEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (flags & MXS_DMA_CTRL_WAIT4END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ccw->bits |= CCW_WAIT4END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) mxs_chan->desc_count = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return &mxs_chan->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) mxs_chan->status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) size_t period_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u32 num_periods = buf_len / period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u32 i = 0, buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (mxs_chan->status == DMA_IN_PROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) mxs_chan->status = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mxs_chan->flags |= MXS_DMA_SG_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) mxs_chan->flags |= MXS_DMA_USE_SEMAPHORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (num_periods > NUM_CCW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_err(mxs_dma->dma_device.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) "maximum number of sg exceeded: %d > %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) num_periods, NUM_CCW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (period_len > MAX_XFER_BYTES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_err(mxs_dma->dma_device.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "maximum period size exceeded: %zu > %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) period_len, MAX_XFER_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) while (buf < buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (i + 1 == num_periods)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ccw->next = mxs_chan->ccw_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ccw->bufaddr = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ccw->xfer_bytes = period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ccw->bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ccw->bits |= CCW_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ccw->bits |= CCW_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ccw->bits |= CCW_HALT_ON_TERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ccw->bits |= CCW_TERM_FLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ccw->bits |= CCW_DEC_SEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dma_addr += period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) buf += period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) mxs_chan->desc_count = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return &mxs_chan->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) mxs_chan->status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int mxs_dma_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) mxs_dma_reset_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) mxs_dma_disable_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dma_cookie_t cookie, struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u32 residue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (mxs_chan->status == DMA_IN_PROGRESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mxs_chan->flags & MXS_DMA_SG_LOOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct mxs_dma_ccw *last_ccw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) last_ccw = &mxs_chan->ccw[mxs_chan->desc_count - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) residue = last_ccw->xfer_bytes + last_ccw->bufaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) bar = readl(mxs_dma->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) HW_APBHX_CHn_BAR(mxs_dma, chan->chan_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) residue -= bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) residue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return mxs_chan->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = clk_prepare_enable(mxs_dma->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = stmp_reset_block(mxs_dma->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* enable apbh burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (dma_is_apbh(mxs_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) writel(BM_APBH_CTRL0_APB_BURST_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) writel(BM_APBH_CTRL0_APB_BURST8_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* enable irq for all the channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) clk_disable_unprepare(mxs_dma->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct mxs_dma_filter_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) unsigned int chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct mxs_dma_filter_param *param = fn_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int chan_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (chan->chan_id != param->chan_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) chan_irq = platform_get_irq(mxs_dma->pdev, param->chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (chan_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) mxs_chan->chan_irq = chan_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct mxs_dma_engine *mxs_dma = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dma_cap_mask_t mask = mxs_dma->dma_device.cap_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct mxs_dma_filter_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (dma_spec->args_count != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) param.chan_id = dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (param.chan_id >= mxs_dma->nr_channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return __dma_request_channel(&mask, mxs_dma_filter_fn, ¶m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ofdma->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int __init mxs_dma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) const struct platform_device_id *id_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) const struct mxs_dma_type *dma_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct mxs_dma_engine *mxs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct resource *iores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (!mxs_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_err(&pdev->dev, "failed to read dma-channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) id_entry = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) id_entry = platform_get_device_id(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dma_type = (struct mxs_dma_type *)id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mxs_dma->type = dma_type->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) mxs_dma->dev_id = dma_type->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) mxs_dma->base = devm_ioremap_resource(&pdev->dev, iores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (IS_ERR(mxs_dma->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return PTR_ERR(mxs_dma->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) mxs_dma->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (IS_ERR(mxs_dma->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return PTR_ERR(mxs_dma->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* Initialize channel parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) for (i = 0; i < MXS_DMA_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) mxs_chan->mxs_dma = mxs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mxs_chan->chan.device = &mxs_dma->dma_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dma_cookie_init(&mxs_chan->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) tasklet_setup(&mxs_chan->tasklet, mxs_dma_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* Add the channel to mxs_chan list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) list_add_tail(&mxs_chan->chan.device_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) &mxs_dma->dma_device.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ret = mxs_dma_init(mxs_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mxs_dma->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) mxs_dma->dma_device.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* mxs_dma gets 65535 bytes maximum sg size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) mxs_dma->dma_device.device_pause = mxs_dma_pause_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) mxs_dma->dma_device.device_resume = mxs_dma_resume_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) mxs_dma->dma_device.device_terminate_all = mxs_dma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) mxs_dma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) mxs_dma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) mxs_dma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) mxs_dma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mxs_dma->dma_device.device_issue_pending = mxs_dma_enable_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ret = dmaenginem_async_device_register(&mxs_dma->dma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_err(mxs_dma->dma_device.dev, "unable to register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ret = of_dma_controller_register(np, mxs_dma_xlate, mxs_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dev_err(mxs_dma->dma_device.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) "failed to register controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_info(mxs_dma->dma_device.dev, "initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static struct platform_driver mxs_dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .name = "mxs-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .of_match_table = mxs_dma_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .id_table = mxs_dma_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int __init mxs_dma_module_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) subsys_initcall(mxs_dma_module_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags