^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) Semihalf 2009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) Ilya Yanok, Emcraft Systems 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) Alexander Popov, Promcontroller 2014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) Mario Six, Guntermann & Drunck GmbH, 2016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * (defines, structures and comments) was taken from MPC5121 DMA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * written by Hongjun Chen <hong-jun.chen@freescale.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Approved as OSADL project by a majority of OSADL members and funded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * by OSADL membership fees in 2009; for details see www.osadl.org.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * MPC512x and MPC8308 DMA driver. It supports memory to memory data transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * (tested using dmatest module) and data transfers between memory and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * peripheral I/O memory by means of slave scatter/gather with these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * limitations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * - chunked transfers (described by s/g lists with more than one item) are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * refused as long as proper support for scatter/gather is missing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * - transfers on MPC8308 always start from software as this SoC does not have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * external request lines for peripheral flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * - memory <-> I/O memory transfer chunks of sizes of 1, 2, 4, 16 (for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * MPC512x), and 32 bytes are supported, and, consequently, source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * addresses and destination addresses must be aligned accordingly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * furthermore, for MPC512x SoCs, the transfer size must be aligned on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * (chunk size * maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Number of DMA Transfer descriptors allocated per channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MPC_DMA_DESCRIPTORS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Macro definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MPC_DMA_TCD_OFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Maximum channel counts for individual hardware variants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * and the maximum channel count over all supported controllers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * used for data structure size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MPC8308_DMACHAN_MAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MPC512x_DMACHAN_MAX 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MPC_DMA_CHANNELS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Arbitration mode of group and channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MPC_DMA_DMACR_EDCG (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MPC_DMA_DMACR_ERGA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MPC_DMA_DMACR_ERCA (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Error codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MPC_DMA_DMAES_VLD (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MPC_DMA_DMAES_GPE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MPC_DMA_DMAES_CPE (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MPC_DMA_DMAES_ERRCHN(err) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (((err) >> 8) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MPC_DMA_DMAES_SAE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MPC_DMA_DMAES_SOE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MPC_DMA_DMAES_DAE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MPC_DMA_DMAES_DOE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MPC_DMA_DMAES_NCE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MPC_DMA_DMAES_SGE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MPC_DMA_DMAES_SBE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MPC_DMA_DMAES_DBE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MPC_DMA_DMAGPOR_SNOOP_ENABLE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MPC_DMA_TSIZE_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MPC_DMA_TSIZE_2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MPC_DMA_TSIZE_4 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MPC_DMA_TSIZE_16 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MPC_DMA_TSIZE_32 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* MPC5121 DMA engine registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct __attribute__ ((__packed__)) mpc_dma_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 dmacr; /* DMA control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 dmaes; /* DMA error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 dmaerqh; /* DMA enable request high(channels 63~32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 dmaerql; /* DMA enable request low(channels 31~0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 dmaeeih; /* DMA enable error interrupt high(ch63~32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 dmaeeil; /* DMA enable error interrupt low(ch31~0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 dmaserq; /* DMA set enable request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 dmacerq; /* DMA clear enable request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 dmaseei; /* DMA set enable error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 dmaceei; /* DMA clear enable error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* 0x1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 dmacint; /* DMA clear interrupt request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 dmacerr; /* DMA clear error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 dmassrt; /* DMA set start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 dmacdne; /* DMA clear DONE status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 dmainth; /* DMA interrupt request high(ch63~32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 dmaintl; /* DMA interrupt request low(ch31~0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 dmaerrh; /* DMA error high(ch63~32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 dmaerrl; /* DMA error low(ch31~0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 dmahrsh; /* DMA hw request status high(ch63~32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 dmahrsl; /* DMA hardware request status low(ch31~0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 dmaihsa; /* DMA interrupt high select AXE(ch63~32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 dmagpor; /* (General purpose register on MPC8308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 dmailsa; /* DMA interrupt low select AXE(ch31~0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* 0x40 ~ 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 reserve0[48]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* 0x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 dchpri[MPC_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* DMA channels(0~63) priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct __attribute__ ((__packed__)) mpc_dma_tcd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 saddr; /* Source address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 smod:5; /* Source address modulo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 ssize:3; /* Source data transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 dmod:5; /* Destination address modulo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 dsize:3; /* Destination data transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 soff:16; /* Signed source address offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 nbytes; /* Inner "minor" byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 slast; /* Last source address adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 daddr; /* Destination address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 citer_elink:1; /* Enable channel-to-channel linking on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * minor loop complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 citer_linkch:6; /* Link channel for minor loop complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 citer:9; /* Current "major" iteration count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 doff:16; /* Signed destination address offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 dlast_sga; /* Last Destination address adjustment/scatter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * gather address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* 0x1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 biter_elink:1; /* Enable channel-to-channel linking on major
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * loop complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 biter_linkch:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 biter:9; /* Beginning "major" iteration count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 bwc:2; /* Bandwidth control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 major_linkch:6; /* Link channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 done:1; /* Channel done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 active:1; /* Channel active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 major_elink:1; /* Enable channel-to-channel linking on major
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * loop complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 e_sg:1; /* Enable scatter/gather processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 d_req:1; /* Disable request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 int_half:1; /* Enable an interrupt when major counter is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * half complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 int_maj:1; /* Enable an interrupt when major iteration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * count completes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 start:1; /* Channel start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct mpc_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct dma_async_tx_descriptor desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct mpc_dma_tcd *tcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dma_addr_t tcd_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int will_access_peripheral;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct mpc_dma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct dma_chan chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct list_head free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct list_head prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct list_head queued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct list_head active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct list_head completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct mpc_dma_tcd *tcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dma_addr_t tcd_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Settings for access to peripheral FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dma_addr_t src_per_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 src_tcd_nunits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 swidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dma_addr_t dst_per_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 dst_tcd_nunits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 dwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Lock for this structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct mpc_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct dma_device dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct tasklet_struct tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct mpc_dma_chan channels[MPC_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct mpc_dma_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct mpc_dma_tcd __iomem *tcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int irq2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) uint error_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int is_mpc8308;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Lock for error_status field in this structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) spinlock_t error_status_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define DRV_NAME "mpc512x_dma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Convert struct dma_chan to struct mpc_dma_chan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static inline struct mpc_dma_chan *dma_chan_to_mpc_dma_chan(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return container_of(c, struct mpc_dma_chan, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Convert struct dma_chan to struct mpc_dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static inline struct mpc_dma *dma_chan_to_mpc_dma(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return container_of(mchan, struct mpc_dma, channels[c->chan_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * Execute all queued DMA descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Following requirements must be met while calling mpc_dma_execute():
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * a) mchan->lock is acquired,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * b) mchan->active list is empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * c) mchan->queued list contains at least one entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void mpc_dma_execute(struct mpc_dma_chan *mchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct mpc_dma_desc *first = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct mpc_dma_desc *prev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct mpc_dma_desc *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int cid = mchan->chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) while (!list_empty(&mchan->queued)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mdesc = list_first_entry(&mchan->queued,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct mpc_dma_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * Grab either several mem-to-mem transfer descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * or one peripheral transfer descriptor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * don't mix mem-to-mem and peripheral transfer descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * within the same 'active' list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (mdesc->will_access_peripheral) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (list_empty(&mchan->active))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) list_move_tail(&mdesc->node, &mchan->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) list_move_tail(&mdesc->node, &mchan->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Chain descriptors into one transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) list_for_each_entry(mdesc, &mchan->active, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (!first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) first = mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!prev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) prev = mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) prev->tcd->dlast_sga = mdesc->tcd_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) prev->tcd->e_sg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mdesc->tcd->start = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) prev = mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) prev->tcd->int_maj = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Send first descriptor in chain into hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) memcpy_toio(&mdma->tcd[cid], first->tcd, sizeof(struct mpc_dma_tcd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (first != prev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mdma->tcd[cid].e_sg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (mdma->is_mpc8308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* MPC8308, no request lines, software initiated start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) out_8(&mdma->regs->dmassrt, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) } else if (first->will_access_peripheral) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Peripherals involved, start by external request signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) out_8(&mdma->regs->dmaserq, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Memory to memory transfer, software initiated start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) out_8(&mdma->regs->dmassrt, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Handle interrupt on one half of DMA controller (32 channels) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void mpc_dma_irq_process(struct mpc_dma *mdma, u32 is, u32 es, int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct mpc_dma_chan *mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct mpc_dma_desc *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 status = is | es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) while ((ch = fls(status) - 1) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) status &= ~(1 << ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mchan = &mdma->channels[ch + off];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) spin_lock(&mchan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) out_8(&mdma->regs->dmacint, ch + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) out_8(&mdma->regs->dmacerr, ch + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Check error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (es & (1 << ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) list_for_each_entry(mdesc, &mchan->active, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mdesc->error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Execute queued descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) list_splice_tail_init(&mchan->active, &mchan->completed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!list_empty(&mchan->queued))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mpc_dma_execute(mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) spin_unlock(&mchan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static irqreturn_t mpc_dma_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct mpc_dma *mdma = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) uint es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Save error status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) es = in_be32(&mdma->regs->dmaes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) spin_lock(&mdma->error_status_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if ((es & MPC_DMA_DMAES_VLD) && mdma->error_status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mdma->error_status = es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) spin_unlock(&mdma->error_status_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Handle interrupt on each channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (mdma->dma.chancnt > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmainth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) in_be32(&mdma->regs->dmaerrh), 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmaintl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) in_be32(&mdma->regs->dmaerrl), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Schedule tasklet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) tasklet_schedule(&mdma->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* process completed descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static void mpc_dma_process_completed(struct mpc_dma *mdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dma_cookie_t last_cookie = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct mpc_dma_chan *mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct mpc_dma_desc *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) LIST_HEAD(list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) for (i = 0; i < mdma->dma.chancnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mchan = &mdma->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Get all completed descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) spin_lock_irqsave(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!list_empty(&mchan->completed))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) list_splice_tail_init(&mchan->completed, &list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) spin_unlock_irqrestore(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (list_empty(&list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Execute callbacks and run dependencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) list_for_each_entry(mdesc, &list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) desc = &mdesc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dmaengine_desc_get_callback_invoke(desc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) last_cookie = desc->cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dma_run_dependencies(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Free descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) spin_lock_irqsave(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) list_splice_tail_init(&list, &mchan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mchan->chan.completed_cookie = last_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) spin_unlock_irqrestore(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* DMA Tasklet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static void mpc_dma_tasklet(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct mpc_dma *mdma = from_tasklet(mdma, t, tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) uint es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) spin_lock_irqsave(&mdma->error_status_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) es = mdma->error_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) mdma->error_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) spin_unlock_irqrestore(&mdma->error_status_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Print nice error report */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (es) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(mdma->dma.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "Hardware reported following error(s) on channel %u:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MPC_DMA_DMAES_ERRCHN(es));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (es & MPC_DMA_DMAES_GPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_err(mdma->dma.dev, "- Group Priority Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (es & MPC_DMA_DMAES_CPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_err(mdma->dma.dev, "- Channel Priority Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (es & MPC_DMA_DMAES_SAE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_err(mdma->dma.dev, "- Source Address Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (es & MPC_DMA_DMAES_SOE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_err(mdma->dma.dev, "- Source Offset Configuration Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (es & MPC_DMA_DMAES_DAE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_err(mdma->dma.dev, "- Destination Address Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (es & MPC_DMA_DMAES_DOE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dev_err(mdma->dma.dev, "- Destination Offset Configuration Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (es & MPC_DMA_DMAES_NCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_err(mdma->dma.dev, "- NBytes/Citter Configuration Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (es & MPC_DMA_DMAES_SGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_err(mdma->dma.dev, "- Scatter/Gather Configuration Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (es & MPC_DMA_DMAES_SBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_err(mdma->dma.dev, "- Source Bus Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (es & MPC_DMA_DMAES_DBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_err(mdma->dma.dev, "- Destination Bus Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mpc_dma_process_completed(mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Submit descriptor to hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static dma_cookie_t mpc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(txd->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct mpc_dma_desc *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mdesc = container_of(txd, struct mpc_dma_desc, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) spin_lock_irqsave(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Move descriptor to queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) list_move_tail(&mdesc->node, &mchan->queued);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* If channel is idle, execute all queued descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (list_empty(&mchan->active))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mpc_dma_execute(mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Update cookie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) cookie = dma_cookie_assign(txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) spin_unlock_irqrestore(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Alloc channel resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int mpc_dma_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct mpc_dma_desc *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct mpc_dma_tcd *tcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dma_addr_t tcd_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) LIST_HEAD(descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Alloc DMA memory for Transfer Control Descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) tcd = dma_alloc_coherent(mdma->dma.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) &tcd_paddr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!tcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Alloc descriptors for this channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) for (i = 0; i < MPC_DMA_DESCRIPTORS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mdesc = kzalloc(sizeof(struct mpc_dma_desc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (!mdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_notice(mdma->dma.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "Memory allocation error. Allocated only %u descriptors\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dma_async_tx_descriptor_init(&mdesc->desc, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) mdesc->desc.flags = DMA_CTRL_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mdesc->desc.tx_submit = mpc_dma_tx_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) mdesc->tcd = &tcd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mdesc->tcd_paddr = tcd_paddr + (i * sizeof(struct mpc_dma_tcd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) list_add_tail(&mdesc->node, &descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Return error only if no descriptors were allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dma_free_coherent(mdma->dma.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) tcd, tcd_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) spin_lock_irqsave(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mchan->tcd = tcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) mchan->tcd_paddr = tcd_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) list_splice_tail_init(&descs, &mchan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) spin_unlock_irqrestore(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Enable Error Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) out_8(&mdma->regs->dmaseei, chan->chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Free channel resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void mpc_dma_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct mpc_dma_desc *mdesc, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct mpc_dma_tcd *tcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dma_addr_t tcd_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) LIST_HEAD(descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) spin_lock_irqsave(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Channel must be idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) BUG_ON(!list_empty(&mchan->prepared));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) BUG_ON(!list_empty(&mchan->queued));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) BUG_ON(!list_empty(&mchan->active));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) BUG_ON(!list_empty(&mchan->completed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Move data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) list_splice_tail_init(&mchan->free, &descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) tcd = mchan->tcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) tcd_paddr = mchan->tcd_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) spin_unlock_irqrestore(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Free DMA memory used by descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dma_free_coherent(mdma->dma.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) tcd, tcd_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Free descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) list_for_each_entry_safe(mdesc, tmp, &descs, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) kfree(mdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* Disable Error Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) out_8(&mdma->regs->dmaceei, chan->chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Send all pending descriptor to hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static void mpc_dma_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * We are posting descriptors to the hardware as soon as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * they are ready, so this function does nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Check request completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static enum dma_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) mpc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Prepare descriptor for memory to memory copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct mpc_dma_desc *mdesc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct mpc_dma_tcd *tcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned long iflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Get free descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) spin_lock_irqsave(&mchan->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (!list_empty(&mchan->free)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) mdesc = list_first_entry(&mchan->free, struct mpc_dma_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) list_del(&mdesc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) spin_unlock_irqrestore(&mchan->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (!mdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* try to free completed descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mpc_dma_process_completed(mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mdesc->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) mdesc->will_access_peripheral = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) tcd = mdesc->tcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Prepare Transfer Control Descriptor for this transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) memset(tcd, 0, sizeof(struct mpc_dma_tcd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (IS_ALIGNED(src | dst | len, 32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) tcd->ssize = MPC_DMA_TSIZE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) tcd->dsize = MPC_DMA_TSIZE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) tcd->soff = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) tcd->doff = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) } else if (!mdma->is_mpc8308 && IS_ALIGNED(src | dst | len, 16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* MPC8308 doesn't support 16 byte transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) tcd->ssize = MPC_DMA_TSIZE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) tcd->dsize = MPC_DMA_TSIZE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) tcd->soff = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) tcd->doff = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) } else if (IS_ALIGNED(src | dst | len, 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) tcd->ssize = MPC_DMA_TSIZE_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) tcd->dsize = MPC_DMA_TSIZE_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) tcd->soff = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) tcd->doff = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) } else if (IS_ALIGNED(src | dst | len, 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) tcd->ssize = MPC_DMA_TSIZE_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) tcd->dsize = MPC_DMA_TSIZE_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) tcd->soff = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) tcd->doff = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) tcd->ssize = MPC_DMA_TSIZE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) tcd->dsize = MPC_DMA_TSIZE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) tcd->soff = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) tcd->doff = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) tcd->saddr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) tcd->daddr = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) tcd->nbytes = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) tcd->biter = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) tcd->citer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Place descriptor in prepared list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) spin_lock_irqsave(&mchan->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) list_add_tail(&mdesc->node, &mchan->prepared);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) spin_unlock_irqrestore(&mchan->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return &mdesc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) inline u8 buswidth_to_dmatsize(u8 buswidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u8 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) for (res = 0; buswidth > 1; buswidth /= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) res++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) mpc_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) unsigned int sg_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct mpc_dma_desc *mdesc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dma_addr_t per_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u32 tcd_nunits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct mpc_dma_tcd *tcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned long iflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int iter, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Currently there is no proper support for scatter/gather */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (sg_len != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (!is_slave_direction(direction))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) for_each_sg(sgl, sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) spin_lock_irqsave(&mchan->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) mdesc = list_first_entry(&mchan->free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct mpc_dma_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (!mdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) spin_unlock_irqrestore(&mchan->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* Try to free completed descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) mpc_dma_process_completed(mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) list_del(&mdesc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (direction == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) per_paddr = mchan->src_per_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) tcd_nunits = mchan->src_tcd_nunits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) per_paddr = mchan->dst_per_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) tcd_nunits = mchan->dst_tcd_nunits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) spin_unlock_irqrestore(&mchan->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (per_paddr == 0 || tcd_nunits == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) goto err_prep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) mdesc->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) mdesc->will_access_peripheral = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* Prepare Transfer Control Descriptor for this transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) tcd = mdesc->tcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) memset(tcd, 0, sizeof(struct mpc_dma_tcd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (direction == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) tcd->saddr = per_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) tcd->daddr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (!IS_ALIGNED(sg_dma_address(sg), mchan->dwidth))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) goto err_prep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) tcd->soff = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) tcd->doff = mchan->dwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) tcd->saddr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) tcd->daddr = per_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (!IS_ALIGNED(sg_dma_address(sg), mchan->swidth))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) goto err_prep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) tcd->soff = mchan->swidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) tcd->doff = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) tcd->ssize = buswidth_to_dmatsize(mchan->swidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) tcd->dsize = buswidth_to_dmatsize(mchan->dwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (mdma->is_mpc8308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) tcd->nbytes = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (!IS_ALIGNED(tcd->nbytes, mchan->swidth))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) goto err_prep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* No major loops for MPC8303 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) tcd->biter = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) tcd->citer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) tcd->nbytes = tcd_nunits * tcd->ssize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (!IS_ALIGNED(len, tcd->nbytes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) goto err_prep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) iter = len / tcd->nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (iter >= 1 << 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* len is too big */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) goto err_prep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* citer_linkch contains the high bits of iter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) tcd->biter = iter & 0x1ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) tcd->biter_linkch = iter >> 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) tcd->citer = tcd->biter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) tcd->citer_linkch = tcd->biter_linkch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) tcd->e_sg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) tcd->d_req = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* Place descriptor in prepared list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) spin_lock_irqsave(&mchan->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) list_add_tail(&mdesc->node, &mchan->prepared);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) spin_unlock_irqrestore(&mchan->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return &mdesc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) err_prep:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Put the descriptor back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) spin_lock_irqsave(&mchan->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) list_add_tail(&mdesc->node, &mchan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) spin_unlock_irqrestore(&mchan->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) inline bool is_buswidth_valid(u8 buswidth, bool is_mpc8308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) switch (buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (is_mpc8308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int mpc_dma_device_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct dma_slave_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * Software constraints:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * - only transfers between a peripheral device and memory are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * - transfer chunk sizes of 1, 2, 4, 16 (for MPC512x), and 32 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * are supported, and, consequently, source addresses and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * destination addresses; must be aligned accordingly; furthermore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * for MPC512x SoCs, the transfer size must be aligned on (chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * size * maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * - during the transfer, the RAM address is incremented by the size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * of transfer chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * - the peripheral port's address is constant during the transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (!IS_ALIGNED(cfg->src_addr, cfg->src_addr_width) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) !IS_ALIGNED(cfg->dst_addr, cfg->dst_addr_width)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (!is_buswidth_valid(cfg->src_addr_width, mdma->is_mpc8308) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) !is_buswidth_valid(cfg->dst_addr_width, mdma->is_mpc8308))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) spin_lock_irqsave(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) mchan->src_per_paddr = cfg->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) mchan->src_tcd_nunits = cfg->src_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) mchan->swidth = cfg->src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) mchan->dst_per_paddr = cfg->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) mchan->dst_tcd_nunits = cfg->dst_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) mchan->dwidth = cfg->dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* Apply defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (mchan->src_tcd_nunits == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) mchan->src_tcd_nunits = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (mchan->dst_tcd_nunits == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) mchan->dst_tcd_nunits = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) spin_unlock_irqrestore(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static int mpc_dma_device_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Disable channel requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) spin_lock_irqsave(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) out_8(&mdma->regs->dmacerq, chan->chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) list_splice_tail_init(&mchan->prepared, &mchan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) list_splice_tail_init(&mchan->queued, &mchan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) list_splice_tail_init(&mchan->active, &mchan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) spin_unlock_irqrestore(&mchan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int mpc_dma_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct device_node *dn = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct device *dev = &op->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct dma_device *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct mpc_dma *mdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct mpc_dma_chan *mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) ulong regs_start, regs_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) int retval, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) u8 chancnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) mdma = devm_kzalloc(dev, sizeof(struct mpc_dma), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (!mdma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) mdma->irq = irq_of_parse_and_map(dn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (!mdma->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_err(dev, "Error mapping IRQ!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (of_device_is_compatible(dn, "fsl,mpc8308-dma")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) mdma->is_mpc8308 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) mdma->irq2 = irq_of_parse_and_map(dn, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!mdma->irq2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dev_err(dev, "Error mapping IRQ!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) goto err_dispose1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) retval = of_address_to_resource(dn, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) dev_err(dev, "Error parsing memory region!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) goto err_dispose2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) regs_start = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) regs_size = resource_size(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (!devm_request_mem_region(dev, regs_start, regs_size, DRV_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) dev_err(dev, "Error requesting memory region!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) retval = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) goto err_dispose2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) mdma->regs = devm_ioremap(dev, regs_start, regs_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (!mdma->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_err(dev, "Error mapping memory region!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) goto err_dispose2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) mdma->tcd = (struct mpc_dma_tcd *)((u8 *)(mdma->regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) + MPC_DMA_TCD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) retval = request_irq(mdma->irq, &mpc_dma_irq, 0, DRV_NAME, mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dev_err(dev, "Error requesting IRQ!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) goto err_dispose2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (mdma->is_mpc8308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) retval = request_irq(mdma->irq2, &mpc_dma_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) DRV_NAME, mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) dev_err(dev, "Error requesting IRQ2!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) goto err_free1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) spin_lock_init(&mdma->error_status_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dma = &mdma->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dma->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) dma->device_alloc_chan_resources = mpc_dma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) dma->device_free_chan_resources = mpc_dma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dma->device_issue_pending = mpc_dma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) dma->device_tx_status = mpc_dma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) dma->device_prep_dma_memcpy = mpc_dma_prep_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) dma->device_prep_slave_sg = mpc_dma_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dma->device_config = mpc_dma_device_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dma->device_terminate_all = mpc_dma_device_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) INIT_LIST_HEAD(&dma->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) dma_cap_set(DMA_MEMCPY, dma->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) dma_cap_set(DMA_SLAVE, dma->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (mdma->is_mpc8308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) chancnt = MPC8308_DMACHAN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) chancnt = MPC512x_DMACHAN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) for (i = 0; i < chancnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) mchan = &mdma->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) mchan->chan.device = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dma_cookie_init(&mchan->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) INIT_LIST_HEAD(&mchan->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) INIT_LIST_HEAD(&mchan->prepared);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) INIT_LIST_HEAD(&mchan->queued);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) INIT_LIST_HEAD(&mchan->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) INIT_LIST_HEAD(&mchan->completed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) spin_lock_init(&mchan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) list_add_tail(&mchan->chan.device_node, &dma->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) tasklet_setup(&mdma->tasklet, mpc_dma_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * Configure DMA Engine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * - Dynamic clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * - Round-robin group arbitration,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * - Round-robin channel arbitration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (mdma->is_mpc8308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* MPC8308 has 16 channels and lacks some registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_ERCA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* enable snooping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) out_be32(&mdma->regs->dmagpor, MPC_DMA_DMAGPOR_SNOOP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* Disable error interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) out_be32(&mdma->regs->dmaeeil, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* Clear interrupts status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) out_be32(&mdma->regs->dmaintl, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) out_be32(&mdma->regs->dmaerrl, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) MPC_DMA_DMACR_ERGA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) MPC_DMA_DMACR_ERCA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* Disable hardware DMA requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) out_be32(&mdma->regs->dmaerqh, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) out_be32(&mdma->regs->dmaerql, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* Disable error interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) out_be32(&mdma->regs->dmaeeih, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) out_be32(&mdma->regs->dmaeeil, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* Clear interrupts status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) out_be32(&mdma->regs->dmainth, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Route interrupts to IPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) out_be32(&mdma->regs->dmaihsa, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) out_be32(&mdma->regs->dmailsa, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Register DMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dev_set_drvdata(dev, mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) retval = dma_async_device_register(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) goto err_free2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* Register with OF helpers for DMA lookups (nonfatal) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) retval = of_dma_controller_register(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) of_dma_xlate_by_chan_id, mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) dev_warn(dev, "Could not register for OF lookup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) err_free2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (mdma->is_mpc8308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) free_irq(mdma->irq2, mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) err_free1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) free_irq(mdma->irq, mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) err_dispose2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (mdma->is_mpc8308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) irq_dispose_mapping(mdma->irq2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) err_dispose1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) irq_dispose_mapping(mdma->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static int mpc_dma_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct device *dev = &op->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct mpc_dma *mdma = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) of_dma_controller_free(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) dma_async_device_unregister(&mdma->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (mdma->is_mpc8308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) free_irq(mdma->irq2, mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) irq_dispose_mapping(mdma->irq2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) free_irq(mdma->irq, mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) irq_dispose_mapping(mdma->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) tasklet_kill(&mdma->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static const struct of_device_id mpc_dma_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) { .compatible = "fsl,mpc5121-dma", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) { .compatible = "fsl,mpc8308-dma", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) MODULE_DEVICE_TABLE(of, mpc_dma_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static struct platform_driver mpc_dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .probe = mpc_dma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .remove = mpc_dma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .of_match_table = mpc_dma_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) module_platform_driver(mpc_dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) MODULE_AUTHOR("Piotr Ziecik <kosmo@semihalf.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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