^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * MOXA ART SoCs DMA Engine support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Jonas Jensen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Jonas Jensen <jonas.jensen@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define APB_DMA_MAX_CHANNEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_OFF_ADDRESS_SOURCE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_OFF_ADDRESS_DEST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_OFF_CYCLES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_OFF_CTRL 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_OFF_CHAN_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define APB_DMA_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define APB_DMA_FIN_INT_STS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define APB_DMA_FIN_INT_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define APB_DMA_BURST_MODE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define APB_DMA_ERR_INT_STS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define APB_DMA_ERR_INT_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Unset: APB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Set: AHB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define APB_DMA_SOURCE_SELECT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define APB_DMA_DEST_SELECT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define APB_DMA_SOURCE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define APB_DMA_DEST 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define APB_DMA_SOURCE_MASK 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define APB_DMA_DEST_MASK 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * 000: No increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * 001: +1 (Burst=0), +4 (Burst=1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 010: +2 (Burst=0), +8 (Burst=1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 011: +4 (Burst=0), +16 (Burst=1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * 101: -1 (Burst=0), -4 (Burst=1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 110: -2 (Burst=0), -8 (Burst=1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * 111: -4 (Burst=0), -16 (Burst=1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define APB_DMA_SOURCE_INC_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define APB_DMA_SOURCE_INC_1_4 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define APB_DMA_SOURCE_INC_2_8 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define APB_DMA_SOURCE_INC_4_16 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define APB_DMA_SOURCE_DEC_1_4 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define APB_DMA_SOURCE_DEC_2_8 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define APB_DMA_SOURCE_DEC_4_16 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define APB_DMA_DEST_INC_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define APB_DMA_DEST_INC_1_4 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define APB_DMA_DEST_INC_2_8 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define APB_DMA_DEST_INC_4_16 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define APB_DMA_DEST_DEC_1_4 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define APB_DMA_DEST_DEC_2_8 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define APB_DMA_DEST_DEC_4_16 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Request signal select source/destination address for DMA hardware handshake.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * The request line number is a property of the DMA controller itself,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * e.g. MMC must always request channels where dma_slave_config->slave_id is 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * 0: No request / Grant signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * 1-15: Request / Grant signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define APB_DMA_SOURCE_REQ_NO 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define APB_DMA_SOURCE_REQ_NO_MASK 0xf000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define APB_DMA_DEST_REQ_NO 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define APB_DMA_DEST_REQ_NO_MASK 0xf0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define APB_DMA_DATA_WIDTH 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define APB_DMA_DATA_WIDTH_MASK 0x300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Data width of transfer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * 00: Word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * 01: Half
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * 10: Byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define APB_DMA_DATA_WIDTH_4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define APB_DMA_DATA_WIDTH_2 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define APB_DMA_DATA_WIDTH_1 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define APB_DMA_CYCLES_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MOXART_DMA_DATA_TYPE_S8 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MOXART_DMA_DATA_TYPE_S16 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MOXART_DMA_DATA_TYPE_S32 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct moxart_sg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) uint32_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct moxart_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enum dma_transfer_direction dma_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dma_addr_t dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int sglen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int dma_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct virt_dma_desc vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uint8_t es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct moxart_sg sg[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct moxart_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct virt_dma_chan vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct moxart_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int ch_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int line_reqno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int sgidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct moxart_dmadev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct dma_device dma_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct moxart_chan slave_chans[APB_DMA_MAX_CHANNEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct moxart_filter_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct moxart_dmadev *mdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct of_phandle_args *dma_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const unsigned int es_bytes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [MOXART_DMA_DATA_TYPE_S8] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [MOXART_DMA_DATA_TYPE_S16] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [MOXART_DMA_DATA_TYPE_S32] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct device *chan2dev(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return &chan->dev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline struct moxart_chan *to_moxart_dma_chan(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return container_of(c, struct moxart_chan, vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline struct moxart_desc *to_moxart_dma_desc(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct dma_async_tx_descriptor *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return container_of(t, struct moxart_desc, vd.tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void moxart_dma_desc_free(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) kfree(container_of(vd, struct moxart_desc, vd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int moxart_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct moxart_chan *ch = to_moxart_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dev_dbg(chan2dev(chan), "%s: ch=%p\n", __func__, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) spin_lock_irqsave(&ch->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ch->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) moxart_dma_desc_free(&ch->desc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ch->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ctrl = readl(ch->base + REG_OFF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ctrl &= ~(APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel(ctrl, ch->base + REG_OFF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) vchan_get_all_descriptors(&ch->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) spin_unlock_irqrestore(&ch->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) vchan_dma_desc_free_list(&ch->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int moxart_slave_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct dma_slave_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct moxart_chan *ch = to_moxart_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ch->cfg = *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ctrl = readl(ch->base + REG_OFF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ctrl |= APB_DMA_BURST_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ctrl &= ~(APB_DMA_DEST_MASK | APB_DMA_SOURCE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ctrl &= ~(APB_DMA_DEST_REQ_NO_MASK | APB_DMA_SOURCE_REQ_NO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) switch (ch->cfg.src_addr_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ctrl |= APB_DMA_DATA_WIDTH_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ch->cfg.direction != DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ctrl |= APB_DMA_DEST_INC_1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ctrl |= APB_DMA_SOURCE_INC_1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ctrl |= APB_DMA_DATA_WIDTH_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ch->cfg.direction != DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ctrl |= APB_DMA_DEST_INC_2_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ctrl |= APB_DMA_SOURCE_INC_2_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ctrl &= ~APB_DMA_DATA_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ch->cfg.direction != DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ctrl |= APB_DMA_DEST_INC_4_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ctrl |= APB_DMA_SOURCE_INC_4_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ch->cfg.direction == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ctrl &= ~APB_DMA_DEST_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ctrl |= APB_DMA_SOURCE_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ctrl |= (ch->line_reqno << 16 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) APB_DMA_DEST_REQ_NO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ctrl |= APB_DMA_DEST_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ctrl &= ~APB_DMA_SOURCE_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ctrl |= (ch->line_reqno << 24 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) APB_DMA_SOURCE_REQ_NO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) writel(ctrl, ch->base + REG_OFF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static struct dma_async_tx_descriptor *moxart_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct dma_chan *chan, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int sg_len, enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned long tx_flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct moxart_chan *ch = to_moxart_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct moxart_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) enum dma_slave_buswidth dev_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dma_addr_t dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct scatterlist *sgent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned int es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (!is_slave_direction(dir)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(chan2dev(chan), "%s: invalid DMA direction\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (dir == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_addr = ch->cfg.src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_width = ch->cfg.src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_addr = ch->cfg.dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_width = ch->cfg.dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) switch (dev_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) es = MOXART_DMA_DATA_TYPE_S8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) es = MOXART_DMA_DATA_TYPE_S16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) es = MOXART_DMA_DATA_TYPE_S32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_err(chan2dev(chan), "%s: unsupported data width (%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) __func__, dev_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) d = kzalloc(struct_size(d, sg, sg_len), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) d->dma_dir = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) d->dev_addr = dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) d->es = es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) for_each_sg(sgl, sgent, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) d->sg[i].addr = sg_dma_address(sgent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) d->sg[i].len = sg_dma_len(sgent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) d->sglen = sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ch->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return vchan_tx_prep(&ch->vc, &d->vd, tx_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct dma_chan *moxart_of_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct moxart_dmadev *mdc = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct moxart_chan *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) chan = dma_get_any_slave_channel(&mdc->dma_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ch = to_moxart_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ch->line_reqno = dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int moxart_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct moxart_chan *ch = to_moxart_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_dbg(chan2dev(chan), "%s: allocating channel #%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) __func__, ch->ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ch->allocated = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static void moxart_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct moxart_chan *ch = to_moxart_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) vchan_free_chan_resources(&ch->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_dbg(chan2dev(chan), "%s: freeing channel #%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) __func__, ch->ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ch->allocated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static void moxart_dma_set_params(struct moxart_chan *ch, dma_addr_t src_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dma_addr_t dst_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static void moxart_set_transfer_params(struct moxart_chan *ch, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct moxart_desc *d = ch->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned int sglen_div = es_bytes[d->es];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) d->dma_cycles = len >> sglen_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * There are 4 cycles on 64 bytes copied, i.e. one cycle copies 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * bytes ( when width is APB_DMAB_DATA_WIDTH_4 ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) writel(d->dma_cycles, ch->base + REG_OFF_CYCLES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_dbg(chan2dev(&ch->vc.chan), "%s: set %u DMA cycles (len=%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) __func__, d->dma_cycles, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static void moxart_start_dma(struct moxart_chan *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ctrl = readl(ch->base + REG_OFF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ctrl |= (APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) writel(ctrl, ch->base + REG_OFF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void moxart_dma_start_sg(struct moxart_chan *ch, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct moxart_desc *d = ch->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct moxart_sg *sg = ch->desc->sg + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ch->desc->dma_dir == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) moxart_dma_set_params(ch, sg->addr, d->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) else if (ch->desc->dma_dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) moxart_dma_set_params(ch, d->dev_addr, sg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) moxart_set_transfer_params(ch, sg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) moxart_start_dma(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void moxart_dma_start_desc(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct moxart_chan *ch = to_moxart_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct virt_dma_desc *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) vd = vchan_next_desc(&ch->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!vd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ch->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) list_del(&vd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ch->desc = to_moxart_dma_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ch->sgidx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) moxart_dma_start_sg(ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static void moxart_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct moxart_chan *ch = to_moxart_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) spin_lock_irqsave(&ch->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (vchan_issue_pending(&ch->vc) && !ch->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) moxart_dma_start_desc(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) spin_unlock_irqrestore(&ch->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static size_t moxart_dma_desc_size(struct moxart_desc *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned int completed_sgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) for (size = i = completed_sgs; i < d->sglen; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) size += d->sg[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static size_t moxart_dma_desc_size_in_flight(struct moxart_chan *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned int completed_cycles, cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) size = moxart_dma_desc_size(ch->desc, ch->sgidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) cycles = readl(ch->base + REG_OFF_CYCLES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) completed_cycles = (ch->desc->dma_cycles - cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) size -= completed_cycles << es_bytes[ch->desc->es];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_dbg(chan2dev(&ch->vc.chan), "%s: size=%zu\n", __func__, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static enum dma_status moxart_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct moxart_chan *ch = to_moxart_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct virt_dma_desc *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct moxart_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) enum dma_status ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * dma_cookie_status() assigns initial residue value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) spin_lock_irqsave(&ch->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) vd = vchan_find_desc(&ch->vc, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (vd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) d = to_moxart_dma_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) txstate->residue = moxart_dma_desc_size(d, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } else if (ch->desc && ch->desc->vd.tx.cookie == cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) txstate->residue = moxart_dma_desc_size_in_flight(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) spin_unlock_irqrestore(&ch->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (ch->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static void moxart_dma_init(struct dma_device *dma, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dma->device_prep_slave_sg = moxart_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dma->device_alloc_chan_resources = moxart_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dma->device_free_chan_resources = moxart_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dma->device_issue_pending = moxart_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dma->device_tx_status = moxart_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dma->device_config = moxart_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dma->device_terminate_all = moxart_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dma->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) INIT_LIST_HEAD(&dma->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static irqreturn_t moxart_dma_interrupt(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct moxart_dmadev *mc = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct moxart_chan *ch = &mc->slave_chans[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_dbg(chan2dev(&ch->vc.chan), "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!ch->allocated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ctrl = readl(ch->base + REG_OFF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) __func__, ch, ch->base, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (ctrl & APB_DMA_FIN_INT_STS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ctrl &= ~APB_DMA_FIN_INT_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ch->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) spin_lock_irqsave(&ch->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (++ch->sgidx < ch->desc->sglen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) moxart_dma_start_sg(ch, ch->sgidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) vchan_cookie_complete(&ch->desc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) moxart_dma_start_desc(&ch->vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) spin_unlock_irqrestore(&ch->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (ctrl & APB_DMA_ERR_INT_STS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ctrl &= ~APB_DMA_ERR_INT_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ch->error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) writel(ctrl, ch->base + REG_OFF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int moxart_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) void __iomem *dma_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct moxart_chan *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct moxart_dmadev *mdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mdc = devm_kzalloc(dev, sizeof(*mdc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (!mdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_err(dev, "no IRQ resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dma_base_addr = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (IS_ERR(dma_base_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return PTR_ERR(dma_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dma_cap_zero(mdc->dma_slave.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dma_cap_set(DMA_SLAVE, mdc->dma_slave.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dma_cap_set(DMA_PRIVATE, mdc->dma_slave.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) moxart_dma_init(&mdc->dma_slave, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ch = &mdc->slave_chans[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ch->ch_num = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ch->allocated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ch->vc.desc_free = moxart_dma_desc_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) vchan_init(&ch->vc, &mdc->dma_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_dbg(dev, "%s: chs[%d]: ch->ch_num=%u ch->base=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) __func__, i, ch->ch_num, ch->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) platform_set_drvdata(pdev, mdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = devm_request_irq(dev, irq, moxart_dma_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) "moxart-dma-engine", mdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_err(dev, "devm_request_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mdc->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = dma_async_device_register(&mdc->dma_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_err(dev, "dma_async_device_register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ret = of_dma_controller_register(node, moxart_of_xlate, mdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev_err(dev, "of_dma_controller_register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dma_async_device_unregister(&mdc->dma_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_dbg(dev, "%s: IRQ=%u\n", __func__, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static int moxart_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct moxart_dmadev *m = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) devm_free_irq(&pdev->dev, m->irq, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dma_async_device_unregister(&m->dma_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) of_dma_controller_free(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static const struct of_device_id moxart_dma_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) { .compatible = "moxa,moxart-dma" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) MODULE_DEVICE_TABLE(of, moxart_dma_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static struct platform_driver moxart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .probe = moxart_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .remove = moxart_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .name = "moxart-dma-engine",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .of_match_table = moxart_dma_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static int moxart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return platform_driver_register(&moxart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) subsys_initcall(moxart_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static void __exit moxart_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) platform_driver_unregister(&moxart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) module_exit(moxart_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) MODULE_DESCRIPTION("MOXART DMA engine driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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