^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver For Marvell Two-channel DMA Engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright: Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_data/dma-mmp_tdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Two-Channel DMA registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TDBCR 0x00 /* Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TDSAR 0x10 /* Src Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TDDAR 0x20 /* Dst Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TDNDPR 0x30 /* Next Desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TDCR 0x40 /* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TDCP 0x60 /* Priority*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TDCDPR 0x70 /* Current Desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TDIMR 0x80 /* Int Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TDISR 0xa0 /* Int Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Two-Channel DMA Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TDCR_SSZ_12_BITS (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TDCR_SSZ_16_BITS (0x2 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TDCR_SSZ_20_BITS (0x3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TDCR_SSZ_24_BITS (0x4 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TDCR_SSZ_32_BITS (0x5 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TDCR_SSZ_SHIFT (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TDCR_SSZ_MASK (0x7 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TDCR_ABR (0x1 << 20) /* Channel Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TDCR_CDE (0x1 << 17) /* Close Desc Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TDCR_CHANACT (0x1 << 14) /* Channel Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TDCR_CHANEN (0x1 << 12) /* Channel Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TDCR_BURSTSZ_4B (0x0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TDCR_BURSTSZ_8B (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TDCR_BURSTSZ_16B (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TDCR_BURSTSZ_32B (0x6 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TDCR_BURSTSZ_64B (0x7 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TDCR_BURSTSZ_SQU_1B (0x5 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TDCR_BURSTSZ_SQU_2B (0x6 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TDCR_BURSTSZ_SQU_4B (0x0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TDCR_BURSTSZ_SQU_8B (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TDCR_BURSTSZ_SQU_16B (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TDCR_BURSTSZ_SQU_32B (0x7 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TDCR_BURSTSZ_128B (0x5 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TDCR_DSTDESCCONT (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TDCR_SRCDESTCONT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Two-Channel DMA Int Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TDIMR_COMP (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Two-Channel DMA Int Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TDISR_COMP (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Two-Channel DMA Descriptor Struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * NOTE: desc's buf must be aligned to 16 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct mmp_tdma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 byte_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 nxt_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum mmp_tdma_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MMP_AUD_TDMA = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PXA910_SQU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TDMA_MAX_XFER_BYTES SZ_64K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct mmp_tdma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct dma_chan chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct dma_async_tx_descriptor desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct tasklet_struct tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct mmp_tdma_desc *desc_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dma_addr_t desc_arr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int desc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) enum dma_transfer_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dma_addr_t dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 burst_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum dma_slave_buswidth buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct dma_slave_config slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) enum mmp_tdma_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) size_t buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) size_t period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) size_t pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct gen_pool *pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TDMA_CHANNEL_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct mmp_tdma_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct dma_device device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int mmp_tdma_config_write(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct dma_slave_config *dmaengine_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel(phys, tdmac->reg_base + TDNDPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) tdmac->reg_base + TDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void mmp_tdma_enable_irq(struct mmp_tdma_chan *tdmac, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) writel(0, tdmac->reg_base + TDIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* enable dma chan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tdmac->reg_base + TDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tdmac->status = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int mmp_tdma_disable_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 tdcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) tdcr = readl(tdmac->reg_base + TDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) tdcr |= TDCR_ABR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) tdcr &= ~TDCR_CHANEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) writel(tdcr, tdmac->reg_base + TDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tdmac->status = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int mmp_tdma_resume_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) tdmac->reg_base + TDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tdmac->status = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int mmp_tdma_pause_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) tdmac->reg_base + TDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tdmac->status = DMA_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int mmp_tdma_config_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int tdcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) mmp_tdma_disable_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (tdmac->dir == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) else if (tdmac->dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (tdmac->type == MMP_AUD_TDMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) tdcr |= TDCR_PACKMOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) switch (tdmac->burst_sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tdcr |= TDCR_BURSTSZ_4B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tdcr |= TDCR_BURSTSZ_8B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tdcr |= TDCR_BURSTSZ_16B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) tdcr |= TDCR_BURSTSZ_32B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) tdcr |= TDCR_BURSTSZ_64B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case 128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tdcr |= TDCR_BURSTSZ_128B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(tdmac->dev, "unknown burst size.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) switch (tdmac->buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) tdcr |= TDCR_SSZ_8_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tdcr |= TDCR_SSZ_16_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) tdcr |= TDCR_SSZ_32_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_err(tdmac->dev, "unknown bus size.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } else if (tdmac->type == PXA910_SQU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) tdcr |= TDCR_SSPMOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) switch (tdmac->burst_sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) tdcr |= TDCR_BURSTSZ_SQU_1B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) tdcr |= TDCR_BURSTSZ_SQU_2B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) tdcr |= TDCR_BURSTSZ_SQU_4B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) tdcr |= TDCR_BURSTSZ_SQU_8B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) tdcr |= TDCR_BURSTSZ_SQU_16B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) tdcr |= TDCR_BURSTSZ_SQU_32B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_err(tdmac->dev, "unknown burst size.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) writel(tdcr, tdmac->reg_base + TDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 reg = readl(tdmac->reg_base + TDISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (reg & TDISR_COMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* clear irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) reg &= ~TDISR_COMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) writel(reg, tdmac->reg_base + TDISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static size_t mmp_tdma_get_pos(struct mmp_tdma_chan *tdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) size_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (tdmac->idx == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) reg = __raw_readl(tdmac->reg_base + TDSAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) reg -= tdmac->desc_arr[0].src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) } else if (tdmac->idx == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) reg = __raw_readl(tdmac->reg_base + TDDAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) reg -= tdmac->desc_arr[0].dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct mmp_tdma_chan *tdmac = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (mmp_tdma_clear_chan_irq(tdmac) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) tasklet_schedule(&tdmac->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct mmp_tdma_device *tdev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int irq_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) for (i = 0; i < TDMA_CHANNEL_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct mmp_tdma_chan *tdmac = tdev->tdmac[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = mmp_tdma_chan_handler(irq, tdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (ret == IRQ_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) irq_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (irq_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void dma_do_tasklet(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct mmp_tdma_chan *tdmac = from_tasklet(tdmac, t, tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dmaengine_desc_get_callback_invoke(&tdmac->desc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct gen_pool *gpool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) gpool = tdmac->pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (gpool && tdmac->desc_arr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) tdmac->desc_arr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (tdmac->status == DMA_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) tdmac->status = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dma_async_tx_descriptor_init(&tdmac->desc, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) tdmac->desc.tx_submit = mmp_tdma_tx_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (tdmac->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = devm_request_irq(tdmac->dev, tdmac->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mmp_tdma_chan_handler, 0, "tdma", tdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static void mmp_tdma_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (tdmac->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) devm_free_irq(tdmac->dev, tdmac->irq, tdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mmp_tdma_free_descriptor(tdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct gen_pool *gpool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) gpool = tdmac->pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!gpool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return tdmac->desc_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) size_t period_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct mmp_tdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int num_periods = buf_len / period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int i = 0, buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!is_slave_direction(direction)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_err(tdmac->dev, "unsupported transfer direction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (tdmac->status != DMA_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev_err(tdmac->dev, "controller busy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (period_len > TDMA_MAX_XFER_BYTES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_err(tdmac->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "maximum period size exceeded: %zu > %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) period_len, TDMA_MAX_XFER_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) tdmac->status = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) tdmac->desc_num = num_periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) desc = mmp_tdma_alloc_descriptor(tdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (mmp_tdma_config_write(chan, direction, &tdmac->slave_config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) while (buf < buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) desc = &tdmac->desc_arr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (i + 1 == num_periods)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) desc->nxt_desc = tdmac->desc_arr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) desc->nxt_desc = tdmac->desc_arr_phys +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) sizeof(*desc) * (i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (direction == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) desc->src_addr = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) desc->dst_addr = tdmac->dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) desc->src_addr = tdmac->dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) desc->dst_addr = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) desc->byte_cnt = period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dma_addr += period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) buf += period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (flags & DMA_PREP_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mmp_tdma_enable_irq(tdmac, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) tdmac->buf_len = buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) tdmac->period_len = period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) tdmac->pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return &tdmac->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) tdmac->status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int mmp_tdma_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) mmp_tdma_disable_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) mmp_tdma_enable_irq(tdmac, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int mmp_tdma_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct dma_slave_config *dmaengine_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) memcpy(&tdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int mmp_tdma_config_write(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct dma_slave_config *dmaengine_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (dir == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) tdmac->dev_addr = dmaengine_cfg->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) tdmac->burst_sz = dmaengine_cfg->src_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) tdmac->buswidth = dmaengine_cfg->src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) tdmac->dev_addr = dmaengine_cfg->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) tdmac->buswidth = dmaengine_cfg->dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) tdmac->dir = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return mmp_tdma_config_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dma_cookie_t cookie, struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) tdmac->pos = mmp_tdma_get_pos(tdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) tdmac->buf_len - tdmac->pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return tdmac->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static void mmp_tdma_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mmp_tdma_enable_chan(tdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int mmp_tdma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) of_dma_controller_free(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int idx, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int type, struct gen_pool *pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct mmp_tdma_chan *tdmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (idx >= TDMA_CHANNEL_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dev_err(tdev->dev, "too many channels for device!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* alloc channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (!tdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) tdmac->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) tdmac->dev = tdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) tdmac->chan.device = &tdev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) tdmac->idx = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) tdmac->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) tdmac->reg_base = tdev->base + idx * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) tdmac->pool = pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) tdmac->status = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) tdev->tdmac[tdmac->idx] = tdmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) tasklet_setup(&tdmac->tasklet, dma_do_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* add the channel to tdma_chan list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) list_add_tail(&tdmac->chan.device_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) &tdev->device.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct mmp_tdma_filter_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) unsigned int chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static bool mmp_tdma_filter_fn(struct dma_chan *chan, void *fn_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct mmp_tdma_filter_param *param = fn_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (chan->chan_id != param->chan_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static struct dma_chan *mmp_tdma_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct mmp_tdma_device *tdev = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dma_cap_mask_t mask = tdev->device.cap_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct mmp_tdma_filter_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (dma_spec->args_count != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) param.chan_id = dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (param.chan_id >= TDMA_CHANNEL_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return __dma_request_channel(&mask, mmp_tdma_filter_fn, ¶m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ofdma->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const struct of_device_id mmp_tdma_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int mmp_tdma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) enum mmp_tdma_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct mmp_tdma_device *tdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct resource *iores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int irq = 0, irq_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int chan_num = TDMA_CHANNEL_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct gen_pool *pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) type = (enum mmp_tdma_type) of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) type = platform_get_device_id(pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* always have couple channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (!tdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) tdev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) for (i = 0; i < chan_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (platform_get_irq(pdev, i) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) irq_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) tdev->base = devm_ioremap_resource(&pdev->dev, iores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (IS_ERR(tdev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return PTR_ERR(tdev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) INIT_LIST_HEAD(&tdev->device.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pool = of_gen_pool_get(pdev->dev.of_node, "asram", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pool = sram_get_gpool("asram");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (!pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_err(&pdev->dev, "asram pool not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (irq_num != chan_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = devm_request_irq(&pdev->dev, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) mmp_tdma_int_handler, IRQF_SHARED, "tdma", tdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* initialize channel parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) for (i = 0; i < chan_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret = mmp_tdma_chan_init(tdev, i, irq, type, pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) tdev->device.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) tdev->device.device_alloc_chan_resources =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) mmp_tdma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) tdev->device.device_free_chan_resources =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) mmp_tdma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) tdev->device.device_tx_status = mmp_tdma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) tdev->device.device_issue_pending = mmp_tdma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) tdev->device.device_config = mmp_tdma_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) tdev->device.device_pause = mmp_tdma_pause_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) tdev->device.device_resume = mmp_tdma_resume_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) tdev->device.device_terminate_all = mmp_tdma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) tdev->device.copy_align = DMAENGINE_ALIGN_8_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) tdev->device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (type == MMP_AUD_TDMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) tdev->device.max_burst = SZ_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) tdev->device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) tdev->device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) } else if (type == PXA910_SQU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) tdev->device.max_burst = SZ_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) tdev->device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) tdev->device.descriptor_reuse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) platform_set_drvdata(pdev, tdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = dmaenginem_async_device_register(&tdev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_err(tdev->device.dev, "unable to register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ret = of_dma_controller_register(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mmp_tdma_xlate, tdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev_err(tdev->device.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) "failed to register controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dev_info(tdev->device.dev, "initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const struct platform_device_id mmp_tdma_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) { "mmp-adma", MMP_AUD_TDMA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) { "pxa910-squ", PXA910_SQU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static struct platform_driver mmp_tdma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .name = "mmp-tdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .of_match_table = mmp_tdma_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .id_table = mmp_tdma_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .probe = mmp_tdma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .remove = mmp_tdma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) module_platform_driver(mmp_tdma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) MODULE_DESCRIPTION("MMP Two-Channel DMA Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) MODULE_ALIAS("platform:mmp-tdma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags