Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (C) 2019 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Copyright (C) 2019 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* global register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define M10V_XDACS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* channel local register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define M10V_XDTBC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define M10V_XDSSA 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define M10V_XDDSA 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define M10V_XDSAC 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define M10V_XDDAC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define M10V_XDDCC 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define M10V_XDDES 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define M10V_XDDPC 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define M10V_XDDSD 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define M10V_XDACS_XE BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define M10V_DEFBS	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define M10V_DEFBL	0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define M10V_XDSAC_SBS	GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define M10V_XDSAC_SBL	GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define M10V_XDDAC_DBS	GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define M10V_XDDAC_DBL	GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define M10V_XDDES_CE	BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define M10V_XDDES_SE	BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define M10V_XDDES_SA	BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define M10V_XDDES_TF	GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define M10V_XDDES_EI	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define M10V_XDDES_TI	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define M10V_XDDSD_IS_MASK	GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define M10V_XDDSD_IS_NORMAL	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MLB_XDMAC_BUSWIDTHS	(BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 				 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 				 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 				 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) struct milbeaut_xdmac_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct virt_dma_desc vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	dma_addr_t src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	dma_addr_t dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) struct milbeaut_xdmac_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct virt_dma_chan vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct milbeaut_xdmac_desc *md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	void __iomem *reg_ch_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) struct milbeaut_xdmac_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct dma_device ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct milbeaut_xdmac_chan channels[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static struct milbeaut_xdmac_chan *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) to_milbeaut_xdmac_chan(struct virt_dma_chan *vc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return container_of(vc, struct milbeaut_xdmac_chan, vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static struct milbeaut_xdmac_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) to_milbeaut_xdmac_desc(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return container_of(vd, struct milbeaut_xdmac_desc, vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* mc->vc.lock must be held by caller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static struct milbeaut_xdmac_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) milbeaut_xdmac_next_desc(struct milbeaut_xdmac_chan *mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct virt_dma_desc *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	vd = vchan_next_desc(&mc->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (!vd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		mc->md = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	list_del(&vd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	mc->md = to_milbeaut_xdmac_desc(vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return mc->md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* mc->vc.lock must be held by caller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void milbeaut_chan_start(struct milbeaut_xdmac_chan *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				struct milbeaut_xdmac_desc *md)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* Setup the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	val = md->len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	writel_relaxed(val, mc->reg_ch_base + M10V_XDTBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	val = md->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	writel_relaxed(val, mc->reg_ch_base + M10V_XDSSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	val = md->dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	writel_relaxed(val, mc->reg_ch_base + M10V_XDDSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	val = readl_relaxed(mc->reg_ch_base + M10V_XDSAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	val &= ~(M10V_XDSAC_SBS | M10V_XDSAC_SBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	val |= FIELD_PREP(M10V_XDSAC_SBS, M10V_DEFBS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		FIELD_PREP(M10V_XDSAC_SBL, M10V_DEFBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	writel_relaxed(val, mc->reg_ch_base + M10V_XDSAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	val = readl_relaxed(mc->reg_ch_base + M10V_XDDAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	val &= ~(M10V_XDDAC_DBS | M10V_XDDAC_DBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	val |= FIELD_PREP(M10V_XDDAC_DBS, M10V_DEFBS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		FIELD_PREP(M10V_XDDAC_DBL, M10V_DEFBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	writel_relaxed(val, mc->reg_ch_base + M10V_XDDAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/* Start the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	val = readl_relaxed(mc->reg_ch_base + M10V_XDDES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	val &= ~(M10V_XDDES_CE | M10V_XDDES_SE | M10V_XDDES_TF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		 M10V_XDDES_EI | M10V_XDDES_TI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	val |= FIELD_PREP(M10V_XDDES_CE, 1) | FIELD_PREP(M10V_XDDES_SE, 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		FIELD_PREP(M10V_XDDES_TF, 1) | FIELD_PREP(M10V_XDDES_EI, 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		FIELD_PREP(M10V_XDDES_TI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	writel_relaxed(val, mc->reg_ch_base + M10V_XDDES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* mc->vc.lock must be held by caller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void milbeaut_xdmac_start(struct milbeaut_xdmac_chan *mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct milbeaut_xdmac_desc *md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	md = milbeaut_xdmac_next_desc(mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (md)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		milbeaut_chan_start(mc, md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static irqreturn_t milbeaut_xdmac_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct milbeaut_xdmac_chan *mc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct milbeaut_xdmac_desc *md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	spin_lock_irqsave(&mc->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* Ack and Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	val = FIELD_PREP(M10V_XDDSD_IS_MASK, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	writel_relaxed(val, mc->reg_ch_base + M10V_XDDSD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	md = mc->md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (!md)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	vchan_cookie_complete(&md->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	milbeaut_xdmac_start(mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	spin_unlock_irqrestore(&mc->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void milbeaut_xdmac_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	vchan_free_chan_resources(to_virt_chan(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) milbeaut_xdmac_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			   dma_addr_t src, size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct virt_dma_chan *vc = to_virt_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct milbeaut_xdmac_desc *md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	md = kzalloc(sizeof(*md), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (!md)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	md->len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	md->src = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	md->dst = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return vchan_tx_prep(vc, &md->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int milbeaut_xdmac_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct virt_dma_chan *vc = to_virt_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct milbeaut_xdmac_chan *mc = to_milbeaut_xdmac_chan(vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	spin_lock_irqsave(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/* Halt the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	val = readl(mc->reg_ch_base + M10V_XDDES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	val &= ~M10V_XDDES_CE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	val |= FIELD_PREP(M10V_XDDES_CE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	writel(val, mc->reg_ch_base + M10V_XDDES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (mc->md) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		vchan_terminate_vdesc(&mc->md->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		mc->md = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	vchan_get_all_descriptors(vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	spin_unlock_irqrestore(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	vchan_dma_desc_free_list(vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void milbeaut_xdmac_synchronize(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	vchan_synchronize(to_virt_chan(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void milbeaut_xdmac_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct virt_dma_chan *vc = to_virt_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct milbeaut_xdmac_chan *mc = to_milbeaut_xdmac_chan(vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	spin_lock_irqsave(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (vchan_issue_pending(vc) && !mc->md)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		milbeaut_xdmac_start(mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	spin_unlock_irqrestore(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void milbeaut_xdmac_desc_free(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	kfree(to_milbeaut_xdmac_desc(vd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int milbeaut_xdmac_chan_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				    struct milbeaut_xdmac_device *mdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				    int chan_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct milbeaut_xdmac_chan *mc = &mdev->channels[chan_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	char *irq_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	irq = platform_get_irq(pdev, chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	irq_name = devm_kasprintf(dev, GFP_KERNEL, "milbeaut-xdmac-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				  chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (!irq_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	ret = devm_request_irq(dev, irq, milbeaut_xdmac_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			       IRQF_SHARED, irq_name, mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	mc->reg_ch_base = mdev->reg_base + chan_id * 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	mc->vc.desc_free = milbeaut_xdmac_desc_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	vchan_init(&mc->vc, &mdev->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void enable_xdmac(struct milbeaut_xdmac_device *mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	val = readl(mdev->reg_base + M10V_XDACS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	val |= M10V_XDACS_XE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	writel(val, mdev->reg_base + M10V_XDACS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void disable_xdmac(struct milbeaut_xdmac_device *mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	val = readl(mdev->reg_base + M10V_XDACS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	val &= ~M10V_XDACS_XE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	writel(val, mdev->reg_base + M10V_XDACS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int milbeaut_xdmac_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct milbeaut_xdmac_device *mdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct dma_device *ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	int nr_chans, ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	nr_chans = platform_irq_count(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (nr_chans < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		return nr_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	mdev = devm_kzalloc(dev, struct_size(mdev, channels, nr_chans),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			    GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (!mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	mdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (IS_ERR(mdev->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		return PTR_ERR(mdev->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	ddev = &mdev->ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	ddev->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	dma_cap_set(DMA_MEMCPY, ddev->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	ddev->src_addr_widths = MLB_XDMAC_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	ddev->dst_addr_widths = MLB_XDMAC_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	ddev->device_free_chan_resources = milbeaut_xdmac_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ddev->device_prep_dma_memcpy = milbeaut_xdmac_prep_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ddev->device_terminate_all = milbeaut_xdmac_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	ddev->device_synchronize = milbeaut_xdmac_synchronize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	ddev->device_tx_status = dma_cookie_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	ddev->device_issue_pending = milbeaut_xdmac_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	INIT_LIST_HEAD(&ddev->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	for (i = 0; i < nr_chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		ret = milbeaut_xdmac_chan_init(pdev, mdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	enable_xdmac(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	ret = dma_async_device_register(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		goto disable_xdmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	ret = of_dma_controller_register(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 					 of_dma_simple_xlate, mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		goto unregister_dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	platform_set_drvdata(pdev, mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unregister_dmac:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	dma_async_device_unregister(ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) disable_xdmac:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	disable_xdmac(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int milbeaut_xdmac_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	struct milbeaut_xdmac_device *mdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	 * Before reaching here, almost all descriptors have been freed by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	 * ->device_free_chan_resources() hook. However, each channel might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	 * be still holding one descriptor that was on-flight at that moment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	 * Terminate it to make sure this hardware is no longer running. Then,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	 * free the channel resources once again to avoid memory leak.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	list_for_each_entry(chan, &mdev->ddev.channels, device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		ret = dmaengine_terminate_sync(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		milbeaut_xdmac_free_chan_resources(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	of_dma_controller_free(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	dma_async_device_unregister(&mdev->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	disable_xdmac(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct of_device_id milbeaut_xdmac_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	{ .compatible = "socionext,milbeaut-m10v-xdmac" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_DEVICE_TABLE(of, milbeaut_xdmac_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static struct platform_driver milbeaut_xdmac_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	.probe = milbeaut_xdmac_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	.remove = milbeaut_xdmac_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		.name = "milbeaut-m10v-xdmac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		.of_match_table = milbeaut_xdmac_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) module_platform_driver(milbeaut_xdmac_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MODULE_DESCRIPTION("Milbeaut XDMAC DmaEngine driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MODULE_LICENSE("GPL v2");