Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Copyright (c) 2017 Sysam, Angelo Dureghello  <angelo@sysam.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_data/dma-mcf-edma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "fsl-edma-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define EDMA_CHANNELS		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define EDMA_MASK_CH(x)		((x) & GENMASK(5, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	struct fsl_edma_engine *mcf_edma = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	struct edma_regs *regs = &mcf_edma->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	unsigned int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct fsl_edma_chan *mcf_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u64 intmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	intmap = ioread32(regs->inth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	intmap <<= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	intmap |= ioread32(regs->intl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	if (!intmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	for (ch = 0; ch < mcf_edma->n_chans; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		if (intmap & BIT(ch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 			iowrite8(EDMA_MASK_CH(ch), regs->cint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 			mcf_chan = &mcf_edma->chans[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 			spin_lock(&mcf_chan->vchan.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 			if (!mcf_chan->edesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 				/* terminate_all called before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 				spin_unlock(&mcf_chan->vchan.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			if (!mcf_chan->edesc->iscyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 				list_del(&mcf_chan->edesc->vdesc.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 				vchan_cookie_complete(&mcf_chan->edesc->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 				mcf_chan->edesc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 				mcf_chan->status = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 				mcf_chan->idle = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 				vchan_cyclic_callback(&mcf_chan->edesc->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			if (!mcf_chan->edesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 				fsl_edma_xfer_desc(mcf_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			spin_unlock(&mcf_chan->vchan.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct fsl_edma_engine *mcf_edma = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct edma_regs *regs = &mcf_edma->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned int err, ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	err = ioread32(regs->errl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		if (err & BIT(ch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			fsl_edma_disable_request(&mcf_edma->chans[ch]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			mcf_edma->chans[ch].status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			mcf_edma->chans[ch].idle = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	err = ioread32(regs->errh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	for (ch = (EDMA_CHANNELS / 2); ch < EDMA_CHANNELS; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		if (err & (BIT(ch - (EDMA_CHANNELS / 2)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			fsl_edma_disable_request(&mcf_edma->chans[ch]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			mcf_edma->chans[ch].status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			mcf_edma->chans[ch].idle = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int mcf_edma_irq_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				struct fsl_edma_engine *mcf_edma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	int ret = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	res = platform_get_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				IORESOURCE_IRQ, "edma-tx-00-15");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	for (ret = 0, i = res->start; i <= res->end; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	res = platform_get_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			IORESOURCE_IRQ, "edma-tx-16-55");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	for (ret = 0, i = res->start; i <= res->end; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ret = platform_get_irq_byname(pdev, "edma-tx-56-63");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (ret != -ENXIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		ret = request_irq(ret, mcf_edma_tx_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				  0, "eDMA", mcf_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	ret = platform_get_irq_byname(pdev, "edma-err");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (ret != -ENXIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		ret = request_irq(ret, mcf_edma_err_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				  0, "eDMA", mcf_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void mcf_edma_irq_free(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				struct fsl_edma_engine *mcf_edma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	res = platform_get_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			IORESOURCE_IRQ, "edma-tx-00-15");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		for (irq = res->start; irq <= res->end; irq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			free_irq(irq, mcf_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	res = platform_get_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			IORESOURCE_IRQ, "edma-tx-16-55");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		for (irq = res->start; irq <= res->end; irq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			free_irq(irq, mcf_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	irq = platform_get_irq_byname(pdev, "edma-tx-56-63");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (irq != -ENXIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		free_irq(irq, mcf_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	irq = platform_get_irq_byname(pdev, "edma-err");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (irq != -ENXIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		free_irq(irq, mcf_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct fsl_edma_drvdata mcf_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.version = v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.setup_irq = mcf_edma_irq_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int mcf_edma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct mcf_edma_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct fsl_edma_engine *mcf_edma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct fsl_edma_chan *mcf_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct edma_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	int ret, i, len, chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		dev_err(&pdev->dev, "no platform data supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	chans = pdata->dma_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	len = sizeof(*mcf_edma) + sizeof(*mcf_chan) * chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	mcf_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (!mcf_edma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	mcf_edma->n_chans = chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* Set up drvdata for ColdFire edma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	mcf_edma->drvdata = &mcf_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	mcf_edma->big_endian = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (!mcf_edma->n_chans) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		dev_info(&pdev->dev, "setting default channel number to 64");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		mcf_edma->n_chans = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	mutex_init(&mcf_edma->fsl_edma_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	mcf_edma->membase = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (IS_ERR(mcf_edma->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return PTR_ERR(mcf_edma->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	fsl_edma_setup_regs(mcf_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	regs = &mcf_edma->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	INIT_LIST_HEAD(&mcf_edma->dma_dev.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	for (i = 0; i < mcf_edma->n_chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		struct fsl_edma_chan *mcf_chan = &mcf_edma->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		mcf_chan->edma = mcf_edma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		mcf_chan->slave_id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		mcf_chan->idle = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		mcf_chan->dma_dir = DMA_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		mcf_chan->vchan.desc_free = fsl_edma_free_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		iowrite32(0x0, &regs->tcd[i].csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	iowrite32(~0, regs->inth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	iowrite32(~0, regs->intl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ret = mcf_edma->drvdata->setup_irq(pdev, mcf_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	dma_cap_set(DMA_PRIVATE, mcf_edma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	dma_cap_set(DMA_SLAVE, mcf_edma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	dma_cap_set(DMA_CYCLIC, mcf_edma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	mcf_edma->dma_dev.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	mcf_edma->dma_dev.device_alloc_chan_resources =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			fsl_edma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	mcf_edma->dma_dev.device_free_chan_resources =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			fsl_edma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	mcf_edma->dma_dev.device_config = fsl_edma_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	mcf_edma->dma_dev.device_prep_dma_cyclic =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			fsl_edma_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	mcf_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	mcf_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	mcf_edma->dma_dev.device_pause = fsl_edma_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	mcf_edma->dma_dev.device_resume = fsl_edma_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	mcf_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	mcf_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	mcf_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	mcf_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	mcf_edma->dma_dev.directions =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	mcf_edma->dma_dev.filter.fn = mcf_edma_filter_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	mcf_edma->dma_dev.filter.map = pdata->slave_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	mcf_edma->dma_dev.filter.mapcnt = pdata->slavecnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	platform_set_drvdata(pdev, mcf_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	ret = dma_async_device_register(&mcf_edma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			"Can't register Freescale eDMA engine. (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* Enable round robin arbitration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	iowrite32(EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int mcf_edma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct fsl_edma_engine *mcf_edma = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	mcf_edma_irq_free(pdev, mcf_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	fsl_edma_cleanup_vchan(&mcf_edma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	dma_async_device_unregister(&mcf_edma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct platform_driver mcf_edma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.name	= "mcf-edma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.probe		= mcf_edma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.remove		= mcf_edma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) bool mcf_edma_filter_fn(struct dma_chan *chan, void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (chan->device->dev->driver == &mcf_edma_driver.driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		struct fsl_edma_chan *mcf_chan = to_fsl_edma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return (mcf_chan->slave_id == (uintptr_t)param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) EXPORT_SYMBOL(mcf_edma_filter_fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int __init mcf_edma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return platform_driver_register(&mcf_edma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) subsys_initcall(mcf_edma_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void __exit mcf_edma_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	platform_driver_unregister(&mcf_edma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) module_exit(mcf_edma_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MODULE_ALIAS("platform:mcf-edma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MODULE_DESCRIPTION("Freescale eDMA engine driver, ColdFire family");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MODULE_LICENSE("GPL v2");