^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _IPU_INTERN_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _IPU_INTERN_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* IPU Common registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IPU_CONF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IPU_CHA_BUF0_RDY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IPU_CHA_BUF1_RDY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IPU_CHA_DB_MODE_SEL 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IPU_CHA_CUR_BUF 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IPU_FS_PROC_FLOW 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IPU_FS_DISP_FLOW 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IPU_TASKS_STAT 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IPU_IMA_ADDR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IPU_IMA_DATA 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IPU_INT_CTRL_1 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IPU_INT_CTRL_2 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IPU_INT_CTRL_3 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IPU_INT_CTRL_4 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IPU_INT_CTRL_5 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IPU_INT_STAT_1 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IPU_INT_STAT_2 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IPU_INT_STAT_3 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IPU_INT_STAT_4 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IPU_INT_STAT_5 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IPU_BRK_CTRL_1 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IPU_BRK_CTRL_2 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IPU_BRK_STAT 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IPU_DIAGB_CTRL 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* IPU_CONF Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IPU_CONF_CSI_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IPU_CONF_IC_EN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IPU_CONF_ROT_EN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IPU_CONF_PF_EN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IPU_CONF_SDC_EN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IPU_CONF_ADC_EN 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IPU_CONF_DI_EN 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IPU_CONF_DU_EN 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IPU_CONF_PXL_ENDIAN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Image Converter Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IC_CONF 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IC_PRP_ENC_RSC 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IC_PRP_VF_RSC 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IC_PP_RSC 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IC_CMBP_1 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IC_CMBP_2 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PF_CONF 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IDMAC_CONF 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IDMAC_CHA_EN 0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IDMAC_CHA_PRI 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IDMAC_CHA_BUSY 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Image Converter Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IC_CONF_PRPENC_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IC_CONF_PRPENC_CSC1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IC_CONF_PRPENC_ROT_EN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IC_CONF_PRPVF_EN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IC_CONF_PRPVF_CSC1 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IC_CONF_PRPVF_CSC2 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IC_CONF_PRPVF_CMB 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IC_CONF_PRPVF_ROT_EN 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IC_CONF_PP_EN 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IC_CONF_PP_CSC1 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IC_CONF_PP_CSC2 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IC_CONF_PP_CMB 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IC_CONF_PP_ROT_EN 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IC_CONF_IC_GLB_LOC_A 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IC_CONF_KEY_COLOR_EN 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IC_CONF_RWS_EN 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IC_CONF_CSI_MEM_WR_EN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IDMA_CHAN_INVALID 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IDMA_IC_0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IDMA_IC_1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IDMA_IC_2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IDMA_IC_3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IDMA_IC_4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IDMA_IC_5 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IDMA_IC_6 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IDMA_IC_7 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IDMA_IC_8 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IDMA_IC_9 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IDMA_IC_10 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IDMA_IC_11 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IDMA_IC_12 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IDMA_IC_13 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IDMA_SDC_BG 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IDMA_SDC_FG 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IDMA_SDC_MASK 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IDMA_SDC_PARTIAL 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IDMA_ADC_SYS1_WR 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IDMA_ADC_SYS2_WR 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IDMA_ADC_SYS1_CMD 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IDMA_ADC_SYS2_CMD 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IDMA_ADC_SYS1_RD 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IDMA_ADC_SYS2_RD 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IDMA_PF_QP 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IDMA_PF_BSP 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IDMA_PF_Y_IN 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IDMA_PF_U_IN 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IDMA_PF_V_IN 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IDMA_PF_Y_OUT 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IDMA_PF_U_OUT 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IDMA_PF_V_OUT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TSTAT_PF_H264_PAUSE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TSTAT_CSI2MEM_MASK 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TSTAT_CSI2MEM_OFFSET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TSTAT_VF_MASK 0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TSTAT_VF_OFFSET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TSTAT_VF_ROT_MASK 0x000C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TSTAT_VF_ROT_OFFSET 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TSTAT_ENC_MASK 0x00000180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TSTAT_ENC_OFFSET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TSTAT_ENC_ROT_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TSTAT_ENC_ROT_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TSTAT_PP_MASK 0x00001800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TSTAT_PP_OFFSET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TSTAT_PP_ROT_MASK 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TSTAT_PP_ROT_OFFSET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TSTAT_PF_MASK 0x00C00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TSTAT_PF_OFFSET 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TSTAT_ADCSYS1_MASK 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TSTAT_ADCSYS1_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TSTAT_ADCSYS2_MASK 0x0C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TSTAT_ADCSYS2_OFFSET 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TASK_STAT_IDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TASK_STAT_ACTIVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TASK_STAT_WAIT4READY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct idmac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct dma_device dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct ipu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void __iomem *reg_ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void __iomem *reg_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int irq_fn; /* IPU Function IRQ to the CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int irq_err; /* IPU Error IRQ to the CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int irq_base; /* Beginning of the IPU IRQ range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long channel_init_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct clk *ipu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct idmac idmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct idmac_channel channel[IPU_CHANNELS_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct tasklet_struct tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define to_idmac(d) container_of(d, struct idmac, dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) extern int ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) extern void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) extern bool ipu_irq_status(uint32_t irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) extern int ipu_irq_map(unsigned int source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) extern int ipu_irq_unmap(unsigned int source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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