^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dma/ipu-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "../dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "ipu_intern.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FS_VF_IN_VALID 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FS_ENC_IN_VALID 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) bool wait_for_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * There can be only one, we could allocate it dynamically, but then we'd have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * to add an extra parameter to some functions, and use something as ugly as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * struct ipu *ipu = to_ipu(to_idmac(ichan->dma_chan.device));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * in the ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct ipu ipu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define to_ipu(id) container_of(id, struct ipu, idmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static u32 __idmac_read_icreg(struct ipu *ipu, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return __raw_readl(ipu->reg_ic + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define idmac_read_icreg(ipu, reg) __idmac_read_icreg(ipu, reg - IC_CONF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void __idmac_write_icreg(struct ipu *ipu, u32 value, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) __raw_writel(value, ipu->reg_ic + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define idmac_write_icreg(ipu, v, reg) __idmac_write_icreg(ipu, v, reg - IC_CONF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static u32 idmac_read_ipureg(struct ipu *ipu, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return __raw_readl(ipu->reg_ipu + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void idmac_write_ipureg(struct ipu *ipu, u32 value, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __raw_writel(value, ipu->reg_ipu + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * IPU / IC common functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void dump_idmac_reg(struct ipu *ipu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_dbg(ipu->dev, "IDMAC_CONF 0x%x, IC_CONF 0x%x, IDMAC_CHA_EN 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "IDMAC_CHA_PRI 0x%x, IDMAC_CHA_BUSY 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) idmac_read_icreg(ipu, IDMAC_CONF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) idmac_read_icreg(ipu, IC_CONF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) idmac_read_icreg(ipu, IDMAC_CHA_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) idmac_read_icreg(ipu, IDMAC_CHA_PRI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) idmac_read_icreg(ipu, IDMAC_CHA_BUSY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dev_dbg(ipu->dev, "BUF0_RDY 0x%x, BUF1_RDY 0x%x, CUR_BUF 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "DB_MODE 0x%x, TASKS_STAT 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) idmac_read_ipureg(ipu, IPU_CHA_CUR_BUF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) idmac_read_ipureg(ipu, IPU_TASKS_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static uint32_t bytes_per_pixel(enum pixel_fmt fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case IPU_PIX_FMT_GENERIC: /* generic data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case IPU_PIX_FMT_RGB332:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case IPU_PIX_FMT_YUV420P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case IPU_PIX_FMT_YUV422P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case IPU_PIX_FMT_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case IPU_PIX_FMT_YUYV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case IPU_PIX_FMT_UYVY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case IPU_PIX_FMT_BGR24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case IPU_PIX_FMT_RGB24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case IPU_PIX_FMT_GENERIC_32: /* generic data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case IPU_PIX_FMT_BGR32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case IPU_PIX_FMT_RGB32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case IPU_PIX_FMT_ABGR32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Enable direct write to memory by the Camera Sensor Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) uint32_t ic_conf, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case IDMAC_IC_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mask = IC_CONF_PRPENC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case IDMAC_IC_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ic_conf = idmac_read_icreg(ipu, IC_CONF) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) idmac_write_icreg(ipu, ic_conf, IC_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Called under spin_lock_irqsave(&ipu_data.lock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) uint32_t ic_conf, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case IDMAC_IC_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mask = IC_CONF_PRPENC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case IDMAC_IC_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ic_conf = idmac_read_icreg(ipu, IC_CONF) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) idmac_write_icreg(ipu, ic_conf, IC_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static uint32_t ipu_channel_status(struct ipu *ipu, enum ipu_channel channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) uint32_t stat = TASK_STAT_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) uint32_t task_stat_reg = idmac_read_ipureg(ipu, IPU_TASKS_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case IDMAC_IC_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) stat = (task_stat_reg & TSTAT_CSI2MEM_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) TSTAT_CSI2MEM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case IDMAC_IC_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case IDMAC_SDC_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case IDMAC_SDC_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct chan_param_mem_planar {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Word 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 xv:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 yv:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 xb:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 yb:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 res1:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 nsb:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 lnpb:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 ubo_l:11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 ubo_h:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 vbo_l:17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 vbo_h:9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 res2:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 fw:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 fh_l:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 fh_h:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 res3:28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Word 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 eba0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 eba1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 bpp:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 sl:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 pfs:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 bam:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 res4:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 npb:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 res5:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 sat:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 res6:30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct chan_param_mem_interleaved {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Word 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 xv:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 yv:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 xb:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 yb:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 sce:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 res1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 nsb:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 lnpb:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 sx:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 sy_l:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 sy_h:9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 ns:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 sm:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 sdx_l:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 sdx_h:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 sdy:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 sdrx:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 sdry:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 sdr1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 res2:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 fw:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 fh_l:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 fh_h:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 res3:28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Word 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 eba0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 eba1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 bpp:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 sl:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 pfs:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 bam:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 res4:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 npb:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 res5:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 sat:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 scc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 ofs0:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 ofs1:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 ofs2:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 ofs3:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 wid0:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 wid1:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 wid2:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 wid3:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 dec_sel:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 res6:28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) union chan_param_mem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct chan_param_mem_planar pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct chan_param_mem_interleaved ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void ipu_ch_param_set_plane_offset(union chan_param_mem *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 u_offset, u32 v_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) params->pp.ubo_l = u_offset & 0x7ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) params->pp.ubo_h = u_offset >> 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) params->pp.vbo_l = v_offset & 0x1ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) params->pp.vbo_h = v_offset >> 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static void ipu_ch_param_set_size(union chan_param_mem *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) uint32_t pixel_fmt, uint16_t width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) uint16_t height, uint16_t stride)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 u_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 v_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) params->pp.fw = width - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) params->pp.fh_l = height - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) params->pp.fh_h = (height - 1) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) params->pp.sl = stride - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) switch (pixel_fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case IPU_PIX_FMT_GENERIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*Represents 8-bit Generic data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) params->pp.bpp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) params->pp.pfs = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) params->pp.npb = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) params->pp.sat = 2; /* SAT = use 32-bit access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case IPU_PIX_FMT_GENERIC_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*Represents 32-bit Generic data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) params->pp.bpp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) params->pp.pfs = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) params->pp.npb = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) params->pp.sat = 2; /* SAT = use 32-bit access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case IPU_PIX_FMT_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) params->ip.bpp = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) params->ip.pfs = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) params->ip.npb = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) params->ip.sat = 2; /* SAT = 32-bit access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) params->ip.ofs0 = 0; /* Red bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) params->ip.ofs1 = 5; /* Green bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) params->ip.ofs2 = 11; /* Blue bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) params->ip.ofs3 = 16; /* Alpha bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) params->ip.wid0 = 4; /* Red bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) params->ip.wid1 = 5; /* Green bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) params->ip.wid2 = 4; /* Blue bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case IPU_PIX_FMT_BGR24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) params->ip.bpp = 1; /* 24 BPP & RGB PFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) params->ip.pfs = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) params->ip.npb = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) params->ip.sat = 2; /* SAT = 32-bit access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) params->ip.ofs0 = 0; /* Red bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) params->ip.ofs1 = 8; /* Green bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) params->ip.ofs2 = 16; /* Blue bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) params->ip.ofs3 = 24; /* Alpha bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) params->ip.wid0 = 7; /* Red bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) params->ip.wid1 = 7; /* Green bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) params->ip.wid2 = 7; /* Blue bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case IPU_PIX_FMT_RGB24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) params->ip.bpp = 1; /* 24 BPP & RGB PFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) params->ip.pfs = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) params->ip.npb = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) params->ip.sat = 2; /* SAT = 32-bit access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) params->ip.ofs0 = 16; /* Red bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) params->ip.ofs1 = 8; /* Green bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) params->ip.ofs2 = 0; /* Blue bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) params->ip.ofs3 = 24; /* Alpha bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) params->ip.wid0 = 7; /* Red bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) params->ip.wid1 = 7; /* Green bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) params->ip.wid2 = 7; /* Blue bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case IPU_PIX_FMT_BGRA32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case IPU_PIX_FMT_BGR32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case IPU_PIX_FMT_ABGR32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) params->ip.bpp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) params->ip.pfs = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) params->ip.npb = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) params->ip.sat = 2; /* SAT = 32-bit access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) params->ip.ofs0 = 8; /* Red bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) params->ip.ofs1 = 16; /* Green bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) params->ip.ofs2 = 24; /* Blue bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) params->ip.ofs3 = 0; /* Alpha bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) params->ip.wid0 = 7; /* Red bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) params->ip.wid1 = 7; /* Green bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) params->ip.wid2 = 7; /* Blue bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) params->ip.wid3 = 7; /* Alpha bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case IPU_PIX_FMT_RGBA32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case IPU_PIX_FMT_RGB32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) params->ip.bpp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) params->ip.pfs = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) params->ip.npb = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) params->ip.sat = 2; /* SAT = 32-bit access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) params->ip.ofs0 = 24; /* Red bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) params->ip.ofs1 = 16; /* Green bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) params->ip.ofs2 = 8; /* Blue bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) params->ip.ofs3 = 0; /* Alpha bit offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) params->ip.wid0 = 7; /* Red bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) params->ip.wid1 = 7; /* Green bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) params->ip.wid2 = 7; /* Blue bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) params->ip.wid3 = 7; /* Alpha bit width - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case IPU_PIX_FMT_UYVY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) params->ip.bpp = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) params->ip.pfs = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) params->ip.npb = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) params->ip.sat = 2; /* SAT = 32-bit access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case IPU_PIX_FMT_YUV420P2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case IPU_PIX_FMT_YUV420P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) params->ip.bpp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) params->ip.pfs = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) params->ip.npb = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) params->ip.sat = 2; /* SAT = 32-bit access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u_offset = stride * height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) v_offset = u_offset + u_offset / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case IPU_PIX_FMT_YVU422P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) params->ip.bpp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) params->ip.pfs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) params->ip.npb = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) params->ip.sat = 2; /* SAT = 32-bit access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) v_offset = stride * height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u_offset = v_offset + v_offset / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case IPU_PIX_FMT_YUV422P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) params->ip.bpp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) params->ip.pfs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) params->ip.npb = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) params->ip.sat = 2; /* SAT = 32-bit access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u_offset = stride * height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) v_offset = u_offset + u_offset / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(ipu_data.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "mx3 ipu: unimplemented pixel format %d\n", pixel_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) params->pp.nsb = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static void ipu_ch_param_set_buffer(union chan_param_mem *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dma_addr_t buf0, dma_addr_t buf1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) params->pp.eba0 = buf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) params->pp.eba1 = buf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static void ipu_ch_param_set_rotation(union chan_param_mem *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) enum ipu_rotate_mode rotate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) params->pp.bam = rotate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) uint32_t num_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) for (; num_words > 0; num_words--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_dbg(ipu_data.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "write param mem - addr = 0x%08X, data = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) addr, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) idmac_write_ipureg(&ipu_data, addr, IPU_IMA_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) idmac_write_ipureg(&ipu_data, *data++, IPU_IMA_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) addr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if ((addr & 0x7) == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) addr &= ~0x7; /* set to word 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) addr += 8; /* increment to next row */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int calc_resize_coeffs(uint32_t in_size, uint32_t out_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) uint32_t *resize_coeff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) uint32_t *downsize_coeff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) uint32_t temp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) uint32_t temp_downsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) *resize_coeff = 1 << 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) *downsize_coeff = 1 << 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Cannot downsize more than 8:1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (out_size << 3 < in_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* compute downsizing coefficient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) temp_downsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) temp_size = in_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) while (temp_size >= out_size * 2 && temp_downsize < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) temp_size >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) temp_downsize++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) *downsize_coeff = temp_downsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * compute resizing coefficient using the following formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * resize_coeff = M*(SI -1)/(SO - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * where M = 2^13, SI - input size, SO - output size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) *resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (*resize_coeff >= 16384L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_err(ipu_data.dev, "Warning! Overflow on resize coeff.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) *resize_coeff = 0x3FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dev_dbg(ipu_data.dev, "resizing from %u -> %u pixels, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "downsize=%u, resize=%u.%lu (reg=%u)\n", in_size, out_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) *downsize_coeff, *resize_coeff >= 8192L ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ((*resize_coeff & 0x1FFF) * 10000L) / 8192L, *resize_coeff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static enum ipu_color_space format_to_colorspace(enum pixel_fmt fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) case IPU_PIX_FMT_RGB565:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case IPU_PIX_FMT_BGR24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) case IPU_PIX_FMT_RGB24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case IPU_PIX_FMT_BGR32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case IPU_PIX_FMT_RGB32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return IPU_COLORSPACE_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return IPU_COLORSPACE_YCBCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int ipu_ic_init_prpenc(struct ipu *ipu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) union ipu_channel_param *params, bool src_is_csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) uint32_t reg, ic_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) uint32_t downsize_coeff, resize_coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) enum ipu_color_space in_fmt, out_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Setup vertical resizing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) calc_resize_coeffs(params->video.in_height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) params->video.out_height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) &resize_coeff, &downsize_coeff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) reg = (downsize_coeff << 30) | (resize_coeff << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Setup horizontal resizing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) calc_resize_coeffs(params->video.in_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) params->video.out_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) &resize_coeff, &downsize_coeff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) reg |= (downsize_coeff << 14) | resize_coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Setup color space conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) in_fmt = format_to_colorspace(params->video.in_pixel_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) out_fmt = format_to_colorspace(params->video.out_pixel_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * Colourspace conversion unsupported yet - see _init_csc() in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * Freescale sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (in_fmt != out_fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dev_err(ipu->dev, "Colourspace conversion unsupported!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) idmac_write_icreg(ipu, reg, IC_PRP_ENC_RSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ic_conf = idmac_read_icreg(ipu, IC_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (src_is_csi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ic_conf &= ~IC_CONF_RWS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ic_conf |= IC_CONF_RWS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) idmac_write_icreg(ipu, ic_conf, IC_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static uint32_t dma_param_addr(uint32_t dma_ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Channel Parameter Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return 0x10000 | (dma_ch << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) bool prio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u32 reg = idmac_read_icreg(ipu, IDMAC_CHA_PRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (prio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) reg |= 1UL << channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) reg &= ~(1UL << channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) idmac_write_icreg(ipu, reg, IDMAC_CHA_PRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dump_idmac_reg(ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static uint32_t ipu_channel_conf_mask(enum ipu_channel channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case IDMAC_IC_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case IDMAC_IC_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) mask = IPU_CONF_CSI_EN | IPU_CONF_IC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case IDMAC_SDC_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case IDMAC_SDC_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) mask = IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * ipu_enable_channel() - enable an IPU channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * @idmac: IPU DMAC context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * @ichan: IDMAC channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * @return: 0 on success or negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct ipu *ipu = to_ipu(idmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) enum ipu_channel channel = ichan->dma_chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) uint32_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) spin_lock_irqsave(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Reset to buffer 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) idmac_write_ipureg(ipu, 1UL << channel, IPU_CHA_CUR_BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ichan->active_buffer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ichan->status = IPU_CHANNEL_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case IDMAC_SDC_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case IDMAC_SDC_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case IDMAC_IC_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ipu_channel_set_priority(ipu, channel, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) idmac_write_icreg(ipu, reg | (1UL << channel), IDMAC_CHA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ipu_ic_enable_task(ipu, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) spin_unlock_irqrestore(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * ipu_init_channel_buffer() - initialize a buffer for logical IPU channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * @ichan: IDMAC channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * @pixel_fmt: pixel format of buffer. Pixel format is a FOURCC ASCII code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * @width: width of buffer in pixels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * @height: height of buffer in pixels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * @stride: stride length of buffer in pixels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * @rot_mode: rotation mode of buffer. A rotation setting other than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * IPU_ROTATE_VERT_FLIP should only be used for input buffers of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * rotation channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * @phyaddr_0: buffer 0 physical address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * @phyaddr_1: buffer 1 physical address. Setting this to a value other than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * NULL enables double buffering mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * @return: 0 on success or negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int ipu_init_channel_buffer(struct idmac_channel *ichan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) enum pixel_fmt pixel_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) uint16_t width, uint16_t height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) uint32_t stride,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) enum ipu_rotate_mode rot_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dma_addr_t phyaddr_0, dma_addr_t phyaddr_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) enum ipu_channel channel = ichan->dma_chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct idmac *idmac = to_idmac(ichan->dma_chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct ipu *ipu = to_ipu(idmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) union chan_param_mem params = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) uint32_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) uint32_t stride_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) stride_bytes = stride * bytes_per_pixel(pixel_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (stride_bytes % 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_err(ipu->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) "Stride length must be 32-bit aligned, stride = %d, bytes = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) stride, stride_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* IC channel's stride must be a multiple of 8 pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if ((channel <= IDMAC_IC_13) && (stride % 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dev_err(ipu->dev, "Stride must be 8 pixel multiple\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Build parameter memory data for DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ipu_ch_param_set_size(¶ms, pixel_fmt, width, height, stride_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ipu_ch_param_set_buffer(¶ms, phyaddr_0, phyaddr_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ipu_ch_param_set_rotation(¶ms, rot_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) spin_lock_irqsave(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (phyaddr_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) reg |= 1UL << channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) reg &= ~(1UL << channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) idmac_write_ipureg(ipu, reg, IPU_CHA_DB_MODE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ichan->status = IPU_CHANNEL_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) spin_unlock_irqrestore(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * ipu_select_buffer() - mark a channel's buffer as ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * @channel: channel ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * @buffer_n: buffer number to mark ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static void ipu_select_buffer(enum ipu_channel channel, int buffer_n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* No locking - this is a write-one-to-set register, cleared by IPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (buffer_n == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* Mark buffer 0 as ready. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF0_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* Mark buffer 1 as ready. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF1_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * ipu_update_channel_buffer() - update physical address of a channel buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * @ichan: IDMAC channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * @buffer_n: buffer number to update.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * 0 or 1 are the only valid values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * @phyaddr: buffer physical address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* Called under spin_lock(_irqsave)(&ichan->lock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static void ipu_update_channel_buffer(struct idmac_channel *ichan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int buffer_n, dma_addr_t phyaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) enum ipu_channel channel = ichan->dma_chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) uint32_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) spin_lock_irqsave(&ipu_data.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (buffer_n == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (reg & (1UL << channel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ipu_ic_disable_task(&ipu_data, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ichan->status = IPU_CHANNEL_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 0x0008UL, IPU_IMA_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (reg & (1UL << channel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ipu_ic_disable_task(&ipu_data, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ichan->status = IPU_CHANNEL_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Check if double-buffering is already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) reg = idmac_read_ipureg(&ipu_data, IPU_CHA_DB_MODE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!(reg & (1UL << channel)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) idmac_write_ipureg(&ipu_data, reg | (1UL << channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) IPU_CHA_DB_MODE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 0x0009UL, IPU_IMA_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) spin_unlock_irqrestore(&ipu_data.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Called under spin_lock_irqsave(&ichan->lock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static int ipu_submit_buffer(struct idmac_channel *ichan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct idmac_tx_desc *desc, struct scatterlist *sg, int buf_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) unsigned int chan_id = ichan->dma_chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct device *dev = &ichan->dma_chan.dev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (async_tx_test_ack(&desc->txd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * On first invocation this shouldn't be necessary, the call to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * ipu_init_channel_buffer() above will set addresses for us, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * could make it conditional on status >= IPU_CHANNEL_ENABLED, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * doing it again shouldn't hurt either.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ipu_update_channel_buffer(ichan, buf_idx, sg_dma_address(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ipu_select_buffer(chan_id, buf_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_dbg(dev, "Updated sg %p on channel 0x%x buffer %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) sg, chan_id, buf_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Called under spin_lock_irqsave(&ichan->lock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int ipu_submit_channel_buffers(struct idmac_channel *ichan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct idmac_tx_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) for (i = 0, sg = desc->sg; i < 2 && sg; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (!ichan->sg[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ichan->sg[i] = sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = ipu_submit_buffer(ichan, desc, sg, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) sg = sg_next(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct idmac_tx_desc *desc = to_tx_desc(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct idmac_channel *ichan = to_idmac_chan(tx->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct idmac *idmac = to_idmac(tx->chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct ipu *ipu = to_ipu(idmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct device *dev = &ichan->dma_chan.dev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (!list_empty(&desc->list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* The descriptor doesn't belong to client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dev_err(dev, "Descriptor %p not prepared!\n", tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) mutex_lock(&ichan->chan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) async_tx_clear_ack(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (ichan->status < IPU_CHANNEL_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct idmac_video_param *video = &ichan->params.video;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * Initial buffer assignment - the first two sg-entries from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * the descriptor will end up in the IDMAC buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dma_addr_t dma_1 = sg_is_last(desc->sg) ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) sg_dma_address(&desc->sg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) WARN_ON(ichan->sg[0] || ichan->sg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) cookie = ipu_init_channel_buffer(ichan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) video->out_pixel_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) video->out_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) video->out_height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) video->out_stride,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) IPU_ROTATE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) sg_dma_address(&desc->sg[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dma_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (cookie < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) dev_dbg(dev, "Submitting sg %p\n", &desc->sg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) cookie = dma_cookie_assign(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* ipu->lock can be taken under ichan->lock, but not v.v. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) spin_lock_irqsave(&ichan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) list_add_tail(&desc->list, &ichan->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* submit_buffers() atomically verifies and fills empty sg slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = ipu_submit_channel_buffers(ichan, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) spin_unlock_irqrestore(&ichan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) cookie = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) goto dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ichan->status < IPU_CHANNEL_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ret = ipu_enable_channel(idmac, ichan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) cookie = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) goto dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dump_idmac_reg(ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dequeue:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (cookie < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) spin_lock_irqsave(&ichan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) list_del_init(&desc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) spin_unlock_irqrestore(&ichan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) tx->cookie = cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ichan->dma_chan.cookie = cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) mutex_unlock(&ichan->chan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* Called with ichan->chan_mutex held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int idmac_desc_alloc(struct idmac_channel *ichan, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct idmac_tx_desc *desc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) vmalloc(array_size(n, sizeof(struct idmac_tx_desc)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct idmac *idmac = to_idmac(ichan->dma_chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* No interrupts, just disable the tasklet for a moment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) tasklet_disable(&to_ipu(idmac)->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ichan->n_tx_desc = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ichan->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) INIT_LIST_HEAD(&ichan->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) INIT_LIST_HEAD(&ichan->free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) while (n--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct dma_async_tx_descriptor *txd = &desc->txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) memset(txd, 0, sizeof(*txd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dma_async_tx_descriptor_init(txd, &ichan->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) txd->tx_submit = idmac_tx_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) list_add(&desc->list, &ichan->free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) desc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) tasklet_enable(&to_ipu(idmac)->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * ipu_init_channel() - initialize an IPU channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * @idmac: IPU DMAC context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * @ichan: pointer to the channel object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * @return 0 on success or negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static int ipu_init_channel(struct idmac *idmac, struct idmac_channel *ichan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) union ipu_channel_param *params = &ichan->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) uint32_t ipu_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) enum ipu_channel channel = ichan->dma_chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) uint32_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct ipu *ipu = to_ipu(idmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) int ret = 0, n_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) dev_dbg(ipu->dev, "init channel = %d\n", channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (channel != IDMAC_SDC_0 && channel != IDMAC_SDC_1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) channel != IDMAC_IC_7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) spin_lock_irqsave(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) case IDMAC_IC_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) n_desc = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) reg = idmac_read_icreg(ipu, IC_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) idmac_write_icreg(ipu, reg & ~IC_CONF_CSI_MEM_WR_EN, IC_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) case IDMAC_IC_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) n_desc = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) reg = idmac_read_ipureg(ipu, IPU_FS_PROC_FLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) idmac_write_ipureg(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ret = ipu_ic_init_prpenc(ipu, params, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) case IDMAC_SDC_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) case IDMAC_SDC_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) n_desc = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ipu->channel_init_mask |= 1L << channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* Enable IPU sub module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ipu_channel_conf_mask(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) spin_unlock_irqrestore(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (n_desc && !ichan->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) ret = idmac_desc_alloc(ichan, n_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dump_idmac_reg(ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * ipu_uninit_channel() - uninitialize an IPU channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * @idmac: IPU DMAC context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * @ichan: pointer to the channel object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static void ipu_uninit_channel(struct idmac *idmac, struct idmac_channel *ichan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) enum ipu_channel channel = ichan->dma_chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) uint32_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) unsigned long chan_mask = 1UL << channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) uint32_t ipu_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct ipu *ipu = to_ipu(idmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) spin_lock_irqsave(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (!(ipu->channel_init_mask & chan_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dev_err(ipu->dev, "Channel already uninitialized %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) spin_unlock_irqrestore(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* Reset the double buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) idmac_write_ipureg(ipu, reg & ~chan_mask, IPU_CHA_DB_MODE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ichan->sec_chan_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) case IDMAC_IC_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) reg = idmac_read_icreg(ipu, IC_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) idmac_write_icreg(ipu, reg & ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) IC_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) case IDMAC_IC_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) reg = idmac_read_icreg(ipu, IC_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) idmac_write_icreg(ipu, reg & ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) IC_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) case IDMAC_SDC_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) case IDMAC_SDC_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ipu->channel_init_mask &= ~(1L << channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ~ipu_channel_conf_mask(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) spin_unlock_irqrestore(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ichan->n_tx_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) vfree(ichan->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ichan->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * ipu_disable_channel() - disable an IPU channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * @idmac: IPU DMAC context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * @ichan: channel object pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * @wait_for_stop: flag to set whether to wait for channel end of frame or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * return immediately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * @return: 0 on success or negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) bool wait_for_stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) enum ipu_channel channel = ichan->dma_chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct ipu *ipu = to_ipu(idmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) uint32_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) unsigned long chan_mask = 1UL << channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (wait_for_stop && channel != IDMAC_SDC_1 && channel != IDMAC_SDC_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) timeout = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* This waiting always fails. Related to spurious irq problem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) while ((idmac_read_icreg(ipu, IDMAC_CHA_BUSY) & chan_mask) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) (ipu_channel_status(ipu, channel) == TASK_STAT_ACTIVE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) dev_dbg(ipu->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) "Warning: timeout waiting for channel %u to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "stop: buf0_rdy = 0x%08X, buf1_rdy = 0x%08X, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) "busy = 0x%08X, tstat = 0x%08X\n", channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) idmac_read_icreg(ipu, IDMAC_CHA_BUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) idmac_read_ipureg(ipu, IPU_TASKS_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) dev_dbg(ipu->dev, "timeout = %d * 10ms\n", 40 - timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* SDC BG and FG must be disabled before DMA is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (wait_for_stop && (channel == IDMAC_SDC_0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) channel == IDMAC_SDC_1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) for (timeout = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) timeout && !ipu_irq_status(ichan->eof_irq); timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) spin_lock_irqsave(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /* Disable IC task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ipu_ic_disable_task(ipu, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* Disable DMA channel(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) idmac_write_icreg(ipu, reg & ~chan_mask, IDMAC_CHA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) spin_unlock_irqrestore(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static struct scatterlist *idmac_sg_next(struct idmac_channel *ichan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct idmac_tx_desc **desc, struct scatterlist *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct scatterlist *sgnew = sg ? sg_next(sg) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (sgnew)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* next sg-element in this list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return sgnew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if ((*desc)->list.next == &ichan->queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* No more descriptors on the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* Fetch next descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) *desc = list_entry((*desc)->list.next, struct idmac_tx_desc, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return (*desc)->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * We have several possibilities here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * current BUF next BUF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * not last sg next not last sg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * not last sg next last sg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * last sg first sg from next descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * last sg NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * Besides, the descriptor queue might be empty or not. We process all these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * cases carefully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static irqreturn_t idmac_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct idmac_channel *ichan = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct device *dev = &ichan->dma_chan.dev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) unsigned int chan_id = ichan->dma_chan.chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct scatterlist **sg, *sgnext, *sgnew = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Next transfer descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct idmac_tx_desc *desc, *descnew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) bool done = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) u32 ready0, ready1, curbuf, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) struct dmaengine_desc_callback cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* IDMAC has cleared the respective BUFx_RDY bit, we manage the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) dev_dbg(dev, "IDMAC irq %d, buf %d\n", irq, ichan->active_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) spin_lock_irqsave(&ipu_data.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ready0 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ready1 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) err = idmac_read_ipureg(&ipu_data, IPU_INT_STAT_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (err & (1 << chan_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) idmac_write_ipureg(&ipu_data, 1 << chan_id, IPU_INT_STAT_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) spin_unlock_irqrestore(&ipu_data.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * Doing this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * ichan->sg[0] = ichan->sg[1] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * you can force channel re-enable on the next tx_submit(), but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * this is dirty - think about descriptors with multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * sg elements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) dev_warn(dev, "NFB4EOF on channel %d, ready %x, %x, cur %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) chan_id, ready0, ready1, curbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) spin_unlock_irqrestore(&ipu_data.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* Other interrupts do not interfere with this channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) spin_lock(&ichan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (unlikely((ichan->active_buffer && (ready1 >> chan_id) & 1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) (!ichan->active_buffer && (ready0 >> chan_id) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) )) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) spin_unlock(&ichan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) "IRQ with active buffer still ready on channel %x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) "active %d, ready %x, %x!\n", chan_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ichan->active_buffer, ready0, ready1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (unlikely(list_empty(&ichan->queue))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ichan->sg[ichan->active_buffer] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) spin_unlock(&ichan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) "IRQ without queued buffers on channel %x, active %d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) "ready %x, %x!\n", chan_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ichan->active_buffer, ready0, ready1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * active_buffer is a software flag, it shows which buffer we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * currently expecting back from the hardware, IDMAC should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * processing the other buffer already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) sg = &ichan->sg[ichan->active_buffer];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) sgnext = ichan->sg[!ichan->active_buffer];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (!*sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) spin_unlock(&ichan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) desc = list_entry(ichan->queue.next, struct idmac_tx_desc, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) descnew = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) dev_dbg(dev, "IDMAC irq %d, dma %#llx, next dma %#llx, current %d, curbuf %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) irq, (u64)sg_dma_address(*sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) sgnext ? (u64)sg_dma_address(sgnext) : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ichan->active_buffer, curbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* Find the descriptor of sgnext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) sgnew = idmac_sg_next(ichan, &descnew, *sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (sgnext != sgnew)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dev_err(dev, "Submitted buffer %p, next buffer %p\n", sgnext, sgnew);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * if sgnext == NULL sg must be the last element in a scatterlist and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * queue must be empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (unlikely(!sgnext)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (!WARN_ON(sg_next(*sg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dev_dbg(dev, "Underrun on channel %x\n", chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ichan->sg[!ichan->active_buffer] = sgnew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (unlikely(sgnew)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ipu_submit_buffer(ichan, descnew, sgnew, !ichan->active_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) spin_lock_irqsave(&ipu_data.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ipu_ic_disable_task(&ipu_data, chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) spin_unlock_irqrestore(&ipu_data.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) ichan->status = IPU_CHANNEL_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* Continue to check for complete descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* Calculate and submit the next sg element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) sgnew = idmac_sg_next(ichan, &descnew, sgnew);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (unlikely(!sg_next(*sg)) || !sgnext) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * Last element in scatterlist done, remove from the queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * _init for debugging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) list_del_init(&desc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) *sg = sgnew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (likely(sgnew) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ipu_submit_buffer(ichan, descnew, sgnew, ichan->active_buffer) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) dmaengine_desc_get_callback(&descnew->txd, &cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) list_del_init(&descnew->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) spin_unlock(&ichan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dmaengine_desc_callback_invoke(&cb, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) spin_lock(&ichan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* Flip the active buffer - even if update above failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ichan->active_buffer = !ichan->active_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dma_cookie_complete(&desc->txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) dmaengine_desc_get_callback(&desc->txd, &cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) spin_unlock(&ichan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (done && (desc->txd.flags & DMA_PREP_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) dmaengine_desc_callback_invoke(&cb, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static void ipu_gc_tasklet(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct ipu *ipu = from_tasklet(ipu, t, tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) for (i = 0; i < IPU_CHANNELS_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct idmac_channel *ichan = ipu->channel + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct idmac_tx_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) int j, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) for (j = 0; j < ichan->n_tx_desc; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) desc = ichan->desc + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) spin_lock_irqsave(&ichan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (async_tx_test_ack(&desc->txd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) list_move(&desc->list, &ichan->free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) for_each_sg(desc->sg, sg, desc->sg_len, k) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (ichan->sg[0] == sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) ichan->sg[0] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) else if (ichan->sg[1] == sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) ichan->sg[1] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) async_tx_clear_ack(&desc->txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) spin_unlock_irqrestore(&ichan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* Allocate and initialise a transfer descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) struct scatterlist *sgl, unsigned int sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) enum dma_transfer_direction direction, unsigned long tx_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct idmac_channel *ichan = to_idmac_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) struct idmac_tx_desc *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct dma_async_tx_descriptor *txd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) /* We only can handle these three channels so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (chan->chan_id != IDMAC_SDC_0 && chan->chan_id != IDMAC_SDC_1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) chan->chan_id != IDMAC_IC_7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (!is_slave_direction(direction)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) mutex_lock(&ichan->chan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) spin_lock_irqsave(&ichan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (!list_empty(&ichan->free_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) desc = list_entry(ichan->free_list.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct idmac_tx_desc, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) list_del_init(&desc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) desc->sg_len = sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) desc->sg = sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) txd = &desc->txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) txd->flags = tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) spin_unlock_irqrestore(&ichan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) mutex_unlock(&ichan->chan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) tasklet_schedule(&to_ipu(to_idmac(chan->device))->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* Re-select the current buffer and re-activate the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static void idmac_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) struct idmac_channel *ichan = to_idmac_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) struct idmac *idmac = to_idmac(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct ipu *ipu = to_ipu(idmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) /* This is not always needed, but doesn't hurt either */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) spin_lock_irqsave(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) ipu_select_buffer(chan->chan_id, ichan->active_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) spin_unlock_irqrestore(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * Might need to perform some parts of initialisation from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * ipu_enable_channel(), but not all, we do not want to reset to buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * 0, don't need to set priority again either, but re-enabling the task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * and the channel might be a good idea.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static int idmac_pause(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct idmac_channel *ichan = to_idmac_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) struct idmac *idmac = to_idmac(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) struct ipu *ipu = to_ipu(idmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) struct list_head *list, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) mutex_lock(&ichan->chan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) spin_lock_irqsave(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ipu_ic_disable_task(ipu, chan->chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* Return all descriptors into "prepared" state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) list_for_each_safe(list, tmp, &ichan->queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) list_del_init(list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ichan->sg[0] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ichan->sg[1] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) spin_unlock_irqrestore(&ipu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) ichan->status = IPU_CHANNEL_INITIALIZED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) mutex_unlock(&ichan->chan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static int __idmac_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) struct idmac_channel *ichan = to_idmac_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) struct idmac *idmac = to_idmac(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) struct ipu *ipu = to_ipu(idmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ipu_disable_channel(idmac, ichan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ichan->status >= IPU_CHANNEL_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) tasklet_disable(&ipu->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* ichan->queue is modified in ISR, have to spinlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) spin_lock_irqsave(&ichan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) list_splice_init(&ichan->queue, &ichan->free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (ichan->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) for (i = 0; i < ichan->n_tx_desc; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct idmac_tx_desc *desc = ichan->desc + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (list_empty(&desc->list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /* Descriptor was prepared, but not submitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) list_add(&desc->list, &ichan->free_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) async_tx_clear_ack(&desc->txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ichan->sg[0] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) ichan->sg[1] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) spin_unlock_irqrestore(&ichan->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) tasklet_enable(&ipu->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) ichan->status = IPU_CHANNEL_INITIALIZED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static int idmac_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) struct idmac_channel *ichan = to_idmac_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) mutex_lock(&ichan->chan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) ret = __idmac_terminate_all(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) mutex_unlock(&ichan->chan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static irqreturn_t ic_sof_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) struct idmac_channel *ichan = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) printk(KERN_DEBUG "Got SOF IRQ %d on Channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) irq, ichan->dma_chan.chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static irqreturn_t ic_eof_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct idmac_channel *ichan = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) printk(KERN_DEBUG "Got EOF IRQ %d on Channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) irq, ichan->dma_chan.chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static int ic_sof = -EINVAL, ic_eof = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static int idmac_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) struct idmac_channel *ichan = to_idmac_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) struct idmac *idmac = to_idmac(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /* dmaengine.c now guarantees to only offer free channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) BUG_ON(chan->client_count > 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) WARN_ON(ichan->status != IPU_CHANNEL_FREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) dma_cookie_init(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ret = ipu_irq_map(chan->chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) goto eimap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ichan->eof_irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * Important to first disable the channel, because maybe someone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * used it before us, e.g., the bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) ipu_disable_channel(idmac, ichan, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) ret = ipu_init_channel(idmac, ichan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) goto eichan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) ret = request_irq(ichan->eof_irq, idmac_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ichan->eof_name, ichan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) goto erirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (chan->chan_id == IDMAC_IC_7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) ic_sof = ipu_irq_map(69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (ic_sof > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ret = request_irq(ic_sof, ic_sof_irq, 0, "IC SOF", ichan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) dev_err(&chan->dev->device, "request irq failed for IC SOF");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) ic_eof = ipu_irq_map(70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (ic_eof > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) ret = request_irq(ic_eof, ic_eof_irq, 0, "IC EOF", ichan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) dev_err(&chan->dev->device, "request irq failed for IC EOF");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) ichan->status = IPU_CHANNEL_INITIALIZED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) chan->chan_id, ichan->eof_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) erirq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ipu_uninit_channel(idmac, ichan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) eichan:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ipu_irq_unmap(chan->chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) eimap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static void idmac_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) struct idmac_channel *ichan = to_idmac_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) struct idmac *idmac = to_idmac(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) mutex_lock(&ichan->chan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) __idmac_terminate_all(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (ichan->status > IPU_CHANNEL_FREE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (chan->chan_id == IDMAC_IC_7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (ic_sof > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) free_irq(ic_sof, ichan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) ipu_irq_unmap(69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) ic_sof = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (ic_eof > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) free_irq(ic_eof, ichan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) ipu_irq_unmap(70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) ic_eof = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) free_irq(ichan->eof_irq, ichan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) ipu_irq_unmap(chan->chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) ichan->status = IPU_CHANNEL_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) ipu_uninit_channel(idmac, ichan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) mutex_unlock(&ichan->chan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) tasklet_schedule(&to_ipu(idmac)->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static enum dma_status idmac_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) dma_cookie_t cookie, struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) return dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) static int __init ipu_idmac_init(struct ipu *ipu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) struct idmac *idmac = &ipu->idmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) struct dma_device *dma = &idmac->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) dma_cap_set(DMA_SLAVE, dma->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) dma_cap_set(DMA_PRIVATE, dma->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* Compulsory common fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) dma->dev = ipu->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) dma->device_alloc_chan_resources = idmac_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) dma->device_free_chan_resources = idmac_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) dma->device_tx_status = idmac_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) dma->device_issue_pending = idmac_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /* Compulsory for DMA_SLAVE fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) dma->device_prep_slave_sg = idmac_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) dma->device_pause = idmac_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) dma->device_terminate_all = idmac_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) INIT_LIST_HEAD(&dma->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) for (i = 0; i < IPU_CHANNELS_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) struct idmac_channel *ichan = ipu->channel + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) struct dma_chan *dma_chan = &ichan->dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) spin_lock_init(&ichan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) mutex_init(&ichan->chan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ichan->status = IPU_CHANNEL_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ichan->sec_chan_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) dma_chan->device = &idmac->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) dma_cookie_init(dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) dma_chan->chan_id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) list_add_tail(&dma_chan->device_node, &dma->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) idmac_write_icreg(ipu, 0x00000070, IDMAC_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) return dma_async_device_register(&idmac->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static void ipu_idmac_exit(struct ipu *ipu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) struct idmac *idmac = &ipu->idmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) for (i = 0; i < IPU_CHANNELS_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) struct idmac_channel *ichan = ipu->channel + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) idmac_terminate_all(&ichan->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) dma_async_device_unregister(&idmac->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) * IPU common probe / remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) static int __init ipu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) struct resource *mem_ipu, *mem_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) spin_lock_init(&ipu_data.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) mem_ic = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (!mem_ipu || !mem_ic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) ipu_data.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) platform_set_drvdata(pdev, &ipu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) goto err_noirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ipu_data.irq_fn = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) ret = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) goto err_noirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) ipu_data.irq_err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) dev_dbg(&pdev->dev, "fn irq %u, err irq %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) ipu_data.irq_fn, ipu_data.irq_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /* Remap IPU common registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) ipu_data.reg_ipu = ioremap(mem_ipu->start, resource_size(mem_ipu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (!ipu_data.reg_ipu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) goto err_ioremap_ipu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) /* Remap Image Converter and Image DMA Controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) ipu_data.reg_ic = ioremap(mem_ic->start, resource_size(mem_ic));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (!ipu_data.reg_ic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) goto err_ioremap_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) /* Get IPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) ipu_data.ipu_clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (IS_ERR(ipu_data.ipu_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) ret = PTR_ERR(ipu_data.ipu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) goto err_clk_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* Make sure IPU HSP clock is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) clk_prepare_enable(ipu_data.ipu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) dev_dbg(&pdev->dev, "%s @ 0x%08lx, fn irq %u, err irq %u\n", pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) (unsigned long)mem_ipu->start, ipu_data.irq_fn, ipu_data.irq_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) ret = ipu_irq_attach_irq(&ipu_data, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) goto err_attach_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /* Initialize DMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) ret = ipu_idmac_init(&ipu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) goto err_idmac_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) tasklet_setup(&ipu_data.tasklet, ipu_gc_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) ipu_data.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) dev_dbg(ipu_data.dev, "IPU initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) err_idmac_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) err_attach_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) ipu_irq_detach_irq(&ipu_data, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) clk_disable_unprepare(ipu_data.ipu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) clk_put(ipu_data.ipu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) err_clk_get:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) iounmap(ipu_data.reg_ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) err_ioremap_ic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) iounmap(ipu_data.reg_ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) err_ioremap_ipu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) err_noirq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) dev_err(&pdev->dev, "Failed to probe IPU: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) static int ipu_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) struct ipu *ipu = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) ipu_idmac_exit(ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) ipu_irq_detach_irq(ipu, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) clk_disable_unprepare(ipu->ipu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) clk_put(ipu->ipu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) iounmap(ipu->reg_ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) iounmap(ipu->reg_ipu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) tasklet_kill(&ipu->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) * We need two MEM resources - with IPU-common and Image Converter registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) * including PF_CONF and IDMAC_* registers, and two IRQs - function and error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static struct platform_driver ipu_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .name = "ipu-core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .remove = ipu_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static int __init ipu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) return platform_driver_probe(&ipu_platform_driver, ipu_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) subsys_initcall(ipu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) MODULE_DESCRIPTION("IPU core driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) MODULE_ALIAS("platform:ipu-core");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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