^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright © 2006, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef _ADMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define _ADMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_data/dma-iop32x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Memory copy units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DMA_CCR(chan) (chan->mmr_base + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DMA_CSR(chan) (chan->mmr_base + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DMA_DAR(chan) (chan->mmr_base + 0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DMA_NDAR(chan) (chan->mmr_base + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DMA_PADR(chan) (chan->mmr_base + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DMA_PUADR(chan) (chan->mmr_base + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DMA_LADR(chan) (chan->mmr_base + 0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DMA_BCR(chan) (chan->mmr_base + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DMA_DCR(chan) (chan->mmr_base + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Application accelerator unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AAU_ACR(chan) (chan->mmr_base + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AAU_ASR(chan) (chan->mmr_base + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AAU_ADAR(chan) (chan->mmr_base + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AAU_ANDAR(chan) (chan->mmr_base + 0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AAU_SAR(src, chan) (chan->mmr_base + (0x10 + ((src) << 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AAU_DAR(chan) (chan->mmr_base + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AAU_ABCR(chan) (chan->mmr_base + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AAU_ADCR(chan) (chan->mmr_base + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AAU_SAR_EDCR(src_edc) (chan->mmr_base + (0x02c + ((src_edc-4) << 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AAU_EDCR0_IDX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AAU_EDCR1_IDX 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AAU_EDCR2_IDX 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct iop3xx_aau_desc_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int int_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int blk1_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int blk2_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int blk3_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int blk4_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int blk5_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int blk6_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int blk7_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int blk8_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int blk_ctrl:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int dual_xor_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int tx_complete:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int zero_result_err:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int zero_result_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int dest_write_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct iop3xx_aau_e_desc_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int reserved:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int blk1_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int blk2_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int blk3_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int blk4_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int blk5_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int blk6_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int blk7_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int blk8_cmd_ctrl:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int reserved2:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct iop3xx_dma_desc_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int pci_transaction:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int int_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int dac_cycle_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int mem_to_mem_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int crc_data_tx_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int crc_gen_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int crc_seed_dis:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int reserved:21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int crc_tx_complete:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct iop3xx_desc_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 pci_src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 pci_dest_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 upper_pci_src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 upper_pci_dest_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 local_pci_src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 local_pci_dest_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 dest_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 desc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct iop3xx_dma_desc_ctrl desc_ctrl_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 crc_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct iop3xx_desc_aau {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 src[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 dest_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 desc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct iop3xx_aau_desc_ctrl desc_ctrl_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 e_desc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) } src_edc[31];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct iop3xx_aau_gfmr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int gfmr1:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int gfmr2:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int gfmr3:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int gfmr4:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct iop3xx_desc_pq_xor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 src[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 data_mult1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct iop3xx_aau_gfmr data_mult1_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 dest_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 desc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct iop3xx_aau_desc_ctrl desc_ctrl_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 e_desc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 data_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct iop3xx_aau_gfmr data_mult_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } src_edc_gfmr[19];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct iop3xx_desc_dual_xor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 src0_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 src1_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 h_src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 d_src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 h_dest_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 desc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct iop3xx_aau_desc_ctrl desc_ctrl_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 d_dest_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) union iop3xx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct iop3xx_desc_aau *aau;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct iop3xx_desc_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct iop3xx_desc_pq_xor *pq_xor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct iop3xx_desc_dual_xor *dual_xor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* No support for p+q operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) iop_chan_pq_slot_count(size_t len, int src_cnt, int *slots_per_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dma_addr_t addr, unsigned char coef)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) iop_chan_pq_zero_sum_slot_count(size_t len, int src_cnt, int *slots_per_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) iop_desc_set_pq_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dma_addr_t *src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static inline int iop_adma_get_max_xor(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static inline int iop_adma_get_max_pq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int id = chan->device->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case DMA0_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case DMA1_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return __raw_readl(DMA_DAR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case AAU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return __raw_readl(AAU_ADAR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 next_desc_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int id = chan->device->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case DMA0_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case DMA1_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __raw_writel(next_desc_addr, DMA_NDAR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case AAU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) __raw_writel(next_desc_addr, AAU_ANDAR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IOP_ADMA_STATUS_BUSY (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT (1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IOP_ADMA_XOR_MAX_BYTE_COUNT (16 * 1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IOP_ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static inline int iop_chan_is_busy(struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 status = __raw_readl(DMA_CSR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return (status & IOP_ADMA_STATUS_BUSY) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static inline int iop_desc_is_aligned(struct iop_adma_desc_slot *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int num_slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* num_slots will only ever be 1, 2, 4, or 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return (desc->idx & (num_slots - 1)) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* to do: support large (i.e. > hw max) buffer sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static inline int iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *slots_per_op = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* to do: support large (i.e. > hw max) buffer sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) *slots_per_op = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int *slots_per_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const char slot_count_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 1, 1, 1, 1, /* 01 - 04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 2, 2, 2, 2, /* 05 - 08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 4, 4, 4, 4, /* 09 - 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 4, 4, 4, 4, /* 13 - 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 8, 8, 8, 8, /* 17 - 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 8, 8, 8, 8, /* 21 - 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 8, 8, 8, 8, /* 25 - 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 8, 8, 8, 8, /* 29 - 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) *slots_per_op = slot_count_table[src_cnt - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return *slots_per_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) iop_chan_interrupt_slot_count(int *slots_per_op, struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) switch (chan->device->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case DMA0_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case DMA1_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return iop_chan_memcpy_slot_count(0, slots_per_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case AAU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return iop3xx_aau_xor_slot_count(0, 2, slots_per_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static inline int iop_chan_xor_slot_count(size_t len, int src_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int *slots_per_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (len <= IOP_ADMA_XOR_MAX_BYTE_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return slot_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) len -= IOP_ADMA_XOR_MAX_BYTE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) while (len > IOP_ADMA_XOR_MAX_BYTE_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) len -= IOP_ADMA_XOR_MAX_BYTE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) slot_cnt += *slots_per_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) slot_cnt += *slots_per_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return slot_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* zero sum on iop3xx is limited to 1k at a time so it requires multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int *slots_per_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return slot_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) slot_cnt += *slots_per_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) slot_cnt += *slots_per_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return slot_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) switch (chan->device->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case DMA0_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case DMA1_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return hw_desc.dma->byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case AAU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return hw_desc.aau->byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* translate the src_idx to a descriptor word index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static inline int __desc_idx(int src_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const int desc_idx_table[] = { 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0, 1, 2, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 5, 6, 7, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 9, 10, 11, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 14, 15, 16, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 18, 19, 20, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 23, 24, 25, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 27, 28, 29, 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return desc_idx_table[src_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct iop_adma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int src_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) switch (chan->device->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case DMA0_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case DMA1_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return hw_desc.dma->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case AAU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (src_idx < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return hw_desc.aau->src[src_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return hw_desc.aau->src_edc[__desc_idx(src_idx)].src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int src_idx, dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (src_idx < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) hw_desc->src[src_idx] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) hw_desc->src_edc[__desc_idx(src_idx)].src_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct iop3xx_desc_dma *hw_desc = desc->hw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct iop3xx_dma_desc_ctrl field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } u_desc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u_desc_ctrl.value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u_desc_ctrl.field.mem_to_mem_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) hw_desc->desc_ctrl = u_desc_ctrl.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) hw_desc->upper_pci_src_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) hw_desc->crc_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct iop3xx_aau_desc_ctrl field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } u_desc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u_desc_ctrl.value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u_desc_ctrl.field.dest_write_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) hw_desc->desc_ctrl = u_desc_ctrl.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static inline u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int i, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 edcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct iop3xx_aau_desc_ctrl field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) } u_desc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u_desc_ctrl.value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) switch (src_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case 25 ... 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) edcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) shift = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) for (i = 24; i < src_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) edcr |= (1 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) shift += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) src_cnt = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case 17 ... 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!u_desc_ctrl.field.blk_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) edcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) shift = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) for (i = 16; i < src_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) edcr |= (1 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) shift += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) src_cnt = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case 9 ... 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (!u_desc_ctrl.field.blk_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) edcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) shift = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) for (i = 8; i < src_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) edcr |= (1 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) shift += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) src_cnt = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case 2 ... 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) shift = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) for (i = 0; i < src_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u_desc_ctrl.value |= (1 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) shift += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u_desc_ctrl.field.dest_write_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) hw_desc->desc_ctrl = u_desc_ctrl.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return u_desc_ctrl.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) iop3xx_desc_init_xor(desc->hw_desc, src_cnt, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* return the number of operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct iop3xx_aau_desc_ctrl field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) } u_desc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) hw_desc = desc->hw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) i += slots_per_op, j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) iter = iop_hw_desc_slot_idx(hw_desc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u_desc_ctrl.field.dest_write_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u_desc_ctrl.field.zero_result_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) iter->desc_ctrl = u_desc_ctrl.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* for the subsequent descriptors preserve the store queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * and chain them together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) prev_hw_desc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) iop_hw_desc_slot_idx(hw_desc, i - slots_per_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) prev_hw_desc->next_desc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) (u32) (desc->async_tx.phys + (i << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct iop3xx_aau_desc_ctrl field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) } u_desc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u_desc_ctrl.value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) switch (src_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case 25 ... 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case 17 ... 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!u_desc_ctrl.field.blk_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case 9 ... 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!u_desc_ctrl.field.blk_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case 1 ... 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u_desc_ctrl.field.dest_write_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) hw_desc->desc_ctrl = u_desc_ctrl.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct iop_adma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u32 byte_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) switch (chan->device->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) case DMA0_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) case DMA1_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) hw_desc.dma->byte_count = byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) case AAU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) hw_desc.aau->byte_count = byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) switch (chan->device->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) case DMA0_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case DMA1_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) iop_desc_init_memcpy(desc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) hw_desc.dma->byte_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) hw_desc.dma->dest_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) hw_desc.dma->src_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case AAU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) iop_desc_init_null_xor(desc, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) hw_desc.aau->byte_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) hw_desc.aau->dest_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) hw_desc.aau->src[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) hw_desc.aau->src[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int slots_per_op = desc->slots_per_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) hw_desc->byte_count = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) iter = iop_hw_desc_slot_idx(hw_desc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) i += slots_per_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) iter = iop_hw_desc_slot_idx(hw_desc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) iter->byte_count = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct iop_adma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) switch (chan->device->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) case DMA0_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case DMA1_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) hw_desc.dma->dest_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) case AAU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) hw_desc.aau->dest_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct iop3xx_desc_dma *hw_desc = desc->hw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) hw_desc->src_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) iop_desc_set_zero_sum_src_addr(struct iop_adma_desc_slot *desc, int src_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) for (i = 0; (slot_cnt -= slots_per_op) >= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) i += slots_per_op, addr += IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) iter = iop_hw_desc_slot_idx(hw_desc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) iop3xx_aau_desc_set_src_addr(iter, src_idx, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int src_idx, dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) for (i = 0; (slot_cnt -= slots_per_op) >= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) i += slots_per_op, addr += IOP_ADMA_XOR_MAX_BYTE_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) iter = iop_hw_desc_slot_idx(hw_desc, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) iop3xx_aau_desc_set_src_addr(iter, src_idx, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 next_desc_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* hw_desc->next_desc is the same location for all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) iop_paranoia(hw_desc.dma->next_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) hw_desc.dma->next_desc = next_desc_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* hw_desc->next_desc is the same location for all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return hw_desc.dma->next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* hw_desc->next_desc is the same location for all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) hw_desc.dma->next_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) hw_desc->src[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static inline enum sum_check_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) iop_paranoia(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return desc_ctrl.zero_result_err << SUM_CHECK_P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static inline void iop_chan_append(struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u32 dma_chan_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dma_chan_ctrl |= 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) __raw_writel(dma_chan_ctrl, DMA_CCR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return __raw_readl(DMA_CSR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static inline void iop_chan_disable(struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dma_chan_ctrl &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) __raw_writel(dma_chan_ctrl, DMA_CCR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static inline void iop_chan_enable(struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dma_chan_ctrl |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) __raw_writel(dma_chan_ctrl, DMA_CCR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u32 status = __raw_readl(DMA_CSR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) status &= (1 << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) __raw_writel(status, DMA_CSR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u32 status = __raw_readl(DMA_CSR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) status &= (1 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) __raw_writel(status, DMA_CSR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u32 status = __raw_readl(DMA_CSR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) switch (chan->device->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) case DMA0_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) case DMA1_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) status &= (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case AAU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) status &= (1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) __raw_writel(status, DMA_CSR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return test_bit(5, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) switch (chan->device->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case DMA0_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case DMA1_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return test_bit(2, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) switch (chan->device->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case DMA0_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) case DMA1_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return test_bit(3, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) switch (chan->device->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case DMA0_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) case DMA1_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return test_bit(1, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #endif /* _ADMA_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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