Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef _IOAT_REGISTERS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define _IOAT_REGISTERS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define IOAT_PCI_DMACTRL_OFFSET			0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define IOAT_PCI_DMACTRL_DMA_EN			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define IOAT_PCI_DMACTRL_MSI_EN			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define IOAT_PCI_DEVICE_ID_OFFSET		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define IOAT_PCI_DMAUNCERRSTS_OFFSET		0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define IOAT_PCI_CHANERR_INT_OFFSET		0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define IOAT_PCI_CHANERRMASK_INT_OFFSET		0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* PCIe config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* EXPCAPID + N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IOAT_DEVCTRL_OFFSET			0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* relaxed ordering enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IOAT_DEVCTRL_ROE			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* MMIO Device Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IOAT_CHANCNT_OFFSET			0x00	/*  8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IOAT_XFERCAP_OFFSET			0x01	/*  8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IOAT_XFERCAP_4KB			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IOAT_XFERCAP_8KB			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define IOAT_XFERCAP_16KB			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define IOAT_XFERCAP_32KB			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IOAT_XFERCAP_32GB			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IOAT_GENCTRL_OFFSET			0x02	/*  8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IOAT_GENCTRL_DEBUG_EN			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IOAT_INTRCTRL_OFFSET			0x03	/*  8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IOAT_INTRCTRL_MASTER_INT_EN		0x01	/* Master Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IOAT_INTRCTRL_INT_STATUS		0x02	/* ATTNSTATUS -or- Channel Int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IOAT_INTRCTRL_INT			0x04	/* INT_STATUS -and- MASTER_INT_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL	0x08	/* Enable all MSI-X vectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IOAT_ATTNSTATUS_OFFSET			0x04	/* Each bit is a channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IOAT_VER_OFFSET				0x08	/*  8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IOAT_VER_MAJOR_MASK			0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IOAT_VER_MINOR_MASK			0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define GET_IOAT_VER_MAJOR(x)			(((x) & IOAT_VER_MAJOR_MASK) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define GET_IOAT_VER_MINOR(x)			((x) & IOAT_VER_MINOR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define IOAT_PERPORTOFFSET_OFFSET		0x0A	/* 16-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define IOAT_INTRDELAY_OFFSET			0x0C	/* 16-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define IOAT_INTRDELAY_MASK			0x3FFF	/* Interrupt Delay Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define IOAT_INTRDELAY_COALESE_SUPPORT		0x8000	/* Interrupt Coalescing Supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IOAT_DEVICE_STATUS_OFFSET		0x0E	/* 16-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define IOAT_DEVICE_STATUS_DEGRADED_MODE	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IOAT_DEVICE_MMIO_RESTRICTED		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IOAT_DEVICE_MEMORY_BYPASS		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IOAT_DEVICE_ADDRESS_REMAPPING		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IOAT_DMA_CAP_OFFSET			0x10	/* 32-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IOAT_CAP_PAGE_BREAK			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define IOAT_CAP_CRC				0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IOAT_CAP_SKIP_MARKER			0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IOAT_CAP_DCA				0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define IOAT_CAP_CRC_MOVE			0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define IOAT_CAP_FILL_BLOCK			0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define IOAT_CAP_APIC				0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IOAT_CAP_XOR				0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define IOAT_CAP_PQ				0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define IOAT_CAP_DWBES				0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IOAT_CAP_RAID16SS			0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define IOAT_CAP_DPS				0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define IOAT_PREFETCH_LIMIT_OFFSET		0x4C	/* CHWPREFLMT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define IOAT_CHANNEL_MMIO_SIZE			0x80	/* Each Channel MMIO space is this size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* DMA Channel Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define IOAT_CHANCTRL_OFFSET			0x00	/* 16-bit Channel Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK	0xF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IOAT3_CHANCTRL_COMPL_DCA_EN		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define IOAT_CHANCTRL_CHANNEL_IN_USE		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define IOAT_CHANCTRL_ERR_INT_EN		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define IOAT_CHANCTRL_ERR_COMPLETION_EN		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define IOAT_CHANCTRL_INT_REARM			0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define IOAT_CHANCTRL_RUN			(IOAT_CHANCTRL_INT_REARM |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 						 IOAT_CHANCTRL_ERR_INT_EN |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 						 IOAT_CHANCTRL_ERR_COMPLETION_EN |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 						 IOAT_CHANCTRL_ANY_ERR_ABORT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define IOAT_DMA_COMP_OFFSET			0x02	/* 16-bit DMA channel compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define IOAT_DMA_COMP_V1			0x0001	/* Compatibility with DMA version 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define IOAT_DMA_COMP_V2			0x0002	/* Compatibility with DMA version 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IOAT_CHANSTS_OFFSET		0x08	/* 64-bit Channel Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR	(~0x3fULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IOAT_CHANSTS_SOFT_ERR			0x10ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IOAT_CHANSTS_UNAFFILIATED_ERR		0x8ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IOAT_CHANSTS_STATUS	0x7ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IOAT_CHANSTS_ACTIVE	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IOAT_CHANSTS_DONE	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IOAT_CHANSTS_SUSPENDED	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IOAT_CHANSTS_HALTED	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IOAT_CHAN_DMACOUNT_OFFSET	0x06    /* 16-bit DMA Count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IOAT_DCACTRL_OFFSET         0x30   /* 32 bit Direct Cache Access Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IOAT_DCACTRL_TARGET_CPU_MASK   0xFFFF /* APIC ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* CB DCA Memory Space Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IOAT_DCAOFFSET_OFFSET       0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* CB_BAR + IOAT_DCAOFFSET value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IOAT_DCA_VER_OFFSET         0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IOAT_DCA_VER_MAJOR_MASK     0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IOAT_DCA_VER_MINOR_MASK     0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IOAT_DCA_COMP_OFFSET        0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IOAT_DCA_COMP_V1            0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IOAT_FSB_CAPABILITY_OFFSET  0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IOAT_FSB_CAPABILITY_PREFETCH    0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IOAT_PCI_CAPABILITY_OFFSET  0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IOAT_PCI_CAPABILITY_MEMWR   0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IOAT_FSB_CAP_ENABLE_OFFSET  0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IOAT_FSB_CAP_ENABLE_PREFETCH    0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IOAT_PCI_CAP_ENABLE_OFFSET  0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IOAT_PCI_CAP_ENABLE_MEMWR   0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IOAT_APICID_TAG_MAP_OFFSET  0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IOAT_APICID_TAG_MAP_TAG0    0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IOAT_APICID_TAG_MAP_TAG1    0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IOAT_APICID_TAG_MAP_TAG2    0x00000F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IOAT_APICID_TAG_MAP_TAG3    0x0000F000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IOAT_APICID_TAG_MAP_TAG4    0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IOAT_APICID_TAG_CB2_VALID   0x8080808080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IOAT_DCA_GREQID_OFFSET      0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IOAT_DCA_GREQID_SIZE        0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IOAT_DCA_GREQID_MASK        0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IOAT_DCA_GREQID_IGNOREFUN   0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IOAT_DCA_GREQID_VALID       0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IOAT_DCA_GREQID_LASTID      0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IOAT3_CSI_CAPABILITY_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IOAT3_CSI_CAPABILITY_PREFETCH    0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IOAT3_PCI_CAPABILITY_OFFSET 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IOAT3_PCI_CAPABILITY_MEMWR  0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IOAT3_CSI_CONTROL_OFFSET    0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IOAT3_CSI_CONTROL_PREFETCH  0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IOAT3_PCI_CONTROL_OFFSET    0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IOAT3_PCI_CONTROL_MEMWR     0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IOAT3_APICID_TAG_MAP_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IOAT3_APICID_TAG_MAP_OFFSET_LOW  0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IOAT3_DCA_GREQID_OFFSET     0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IOAT1_CHAINADDR_OFFSET		0x0C	/* 64-bit Descriptor Chain Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IOAT2_CHAINADDR_OFFSET		0x10	/* 64-bit Descriptor Chain Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IOAT_CHAINADDR_OFFSET(ver)		((ver) < IOAT_VER_2_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 						? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IOAT1_CHAINADDR_OFFSET_LOW	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IOAT2_CHAINADDR_OFFSET_LOW	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IOAT_CHAINADDR_OFFSET_LOW(ver)		((ver) < IOAT_VER_2_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 						? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IOAT1_CHAINADDR_OFFSET_HIGH	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IOAT2_CHAINADDR_OFFSET_HIGH	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IOAT_CHAINADDR_OFFSET_HIGH(ver)		((ver) < IOAT_VER_2_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 						? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IOAT1_CHANCMD_OFFSET		0x14	/*  8-bit DMA Channel Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IOAT2_CHANCMD_OFFSET		0x04	/*  8-bit DMA Channel Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IOAT_CHANCMD_OFFSET(ver)		((ver) < IOAT_VER_2_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 						? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IOAT_CHANCMD_RESET			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IOAT_CHANCMD_RESUME			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IOAT_CHANCMD_ABORT			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IOAT_CHANCMD_SUSPEND			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IOAT_CHANCMD_APPEND			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IOAT_CHANCMD_START			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IOAT_CHANCMP_OFFSET			0x18	/* 64-bit Channel Completion Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IOAT_CHANCMP_OFFSET_LOW			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IOAT_CHANCMP_OFFSET_HIGH		0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IOAT_CDAR_OFFSET			0x20	/* 64-bit Current Descriptor Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IOAT_CDAR_OFFSET_LOW			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IOAT_CDAR_OFFSET_HIGH			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IOAT_CHANERR_OFFSET			0x28	/* 32-bit Channel Error Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IOAT_CHANERR_SRC_ADDR_ERR	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IOAT_CHANERR_DEST_ADDR_ERR	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IOAT_CHANERR_NEXT_ADDR_ERR	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IOAT_CHANERR_CHANCMD_ERR		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR	0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IOAT_CHANERR_READ_DATA_ERR		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IOAT_CHANERR_WRITE_DATA_ERR		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IOAT_CHANERR_CONTROL_ERR	0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IOAT_CHANERR_LENGTH_ERR	0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IOAT_CHANERR_COMPLETION_ADDR_ERR	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IOAT_CHANERR_INT_CONFIGURATION_ERR	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IOAT_CHANERR_SOFT_ERR			0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IOAT_CHANERR_UNAFFILIATED_ERR		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IOAT_CHANERR_XOR_P_OR_CRC_ERR		0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IOAT_CHANERR_XOR_Q_ERR			0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR	0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IOAT_CHANERR_RECOVER_MASK (IOAT_CHANERR_READ_DATA_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 				   IOAT_CHANERR_WRITE_DATA_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IOAT_CHANERR_MASK_OFFSET		0x2C	/* 32-bit Channel Error Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IOAT_CHAN_DRSCTL_OFFSET			0xB6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IOAT_CHAN_DRSZ_4KB			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IOAT_CHAN_DRSZ_8KB			0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IOAT_CHAN_DRSZ_2MB			0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IOAT_CHAN_DRS_EN			0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IOAT_CHAN_DRS_AUTOWRAP			0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IOAT_CHAN_LTR_SWSEL_OFFSET		0xBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IOAT_CHAN_LTR_SWSEL_ACTIVE		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IOAT_CHAN_LTR_SWSEL_IDLE		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IOAT_CHAN_LTR_ACTIVE_OFFSET		0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IOAT_CHAN_LTR_ACTIVE_SNVAL		0x0000	/* 0 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IOAT_CHAN_LTR_ACTIVE_SNLATSCALE		0x0800	/* 1us scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IOAT_CHAN_LTR_ACTIVE_SNREQMNT		0x8000	/* snoop req enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IOAT_CHAN_LTR_IDLE_OFFSET		0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IOAT_CHAN_LTR_IDLE_SNVAL		0x0258	/* 600 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IOAT_CHAN_LTR_IDLE_SNLATSCALE		0x0800	/* 1us scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IOAT_CHAN_LTR_IDLE_SNREQMNT		0x8000	/* snoop req enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #endif /* _IOAT_REGISTERS_H_ */